JPH10290155A - Logic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the logic processing unit that is controlled from a CPU in which a content of logic processing is easily corrected or changed without using a mask ROM. SOLUTION: The device is provided with a hard wired logic circuit 1 that applies prescribed logic processing result to an input signal, a static RAM 2 that conducts the logic processing on behalf of the circuit 1, a selector 3 that selects an input signal and a selector 4 that selects an output signal respectively. When a CPU address is given to the RAM 2, correction data for logic processing are written to the RAM 2 through a CPU data bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic processing device controllable from a CPU, and more particularly to an integrated circuit such as an ASIC having a microcode control unit including a CPU core and a hard wired logic circuit.

[0002]

2. Description of the Related Art In recent years, integrated circuits having a logic (logic) processing function, such as one-chip microcomputers and ASICs, which are integrated circuits for specific applications, have been widely used in various electronic devices, industrial devices, OA devices, and the like. Is being used. For example, there is a system in which a large number of copying machines are connected to a host computer of a management center via a communication line, and when a trouble occurs in each copying machine, the trouble is automatically notified to a host side to enable remote diagnosis. Although developed, in such a case, an ASIC for executing a function necessary for remote diagnosis is mounted on the control unit of each copying machine.

Most of such integrated circuits are constituted by a CPU (Central Processing Unit), a RAM, a ROM, a hard wired logic circuit, and the like. And
A hard wired logic circuit for performing a logical operation at high speed can be largely compressed and configured by a recent logic synthesis technique even if a complicated description is made. Therefore, when mass-producing an integrated circuit as the same logic processing device, it can be provided at low cost.

[0004]

However, such a hard wired logic circuit cannot be modified once the chip is constructed, and when the modification is necessary, the chip itself is re-equipped. I have to remake it. Therefore, especially when designing and creating a new ASIC, it is necessary to modify the logic frequently, which is very inefficient and uneconomical. Also,
Even if there is a problem in the logic circuit after completion of the chip and it is necessary to make a correction or change the function, it cannot be performed easily.

On the other hand, a mask ROM can be used as a logic processing device for obtaining a specific output for a plurality of inputs. In the case of a mask ROM, it is possible to modify the contents relatively easily, so that the above-mentioned problem can be solved. However, since logical compression is impossible, the chip becomes large, Further, there is a problem that the cost increases because a masking step is added at the time of manufacturing.

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and a logic controllable from a CPU, which can easily modify or change the contents of logic processing without using a mask ROM. It is an object to provide a processing device.

[0007]

SUMMARY OF THE INVENTION The present invention is a logic processing device controllable from a CPU, and in order to achieve the above object, a hard wired logic for outputting a predetermined logic processing result with respect to an input signal. A circuit (hereinafter simply referred to as “logic circuit”), a static RAM (hereinafter simply referred to as “RAM”) that outputs a logic processing result according to data written in advance to an input signal,
By selecting an input signal and an address signal from the CPU, RA
It has a first selector for input to M, a second selector for selecting and outputting an output signal of the logic circuit and an output signal of the RAM, and means for connecting a CPU data bus to the RAM.

Then, the first selector selects the CP.
When an address signal from U is selected and input to the RAM, data for logic processing can be written to the RAM via the CPU data bus. When a plurality of logic processing devices are provided, each RAM
May be selectively activated by a chip select signal, and the address of the chip select signal viewed from the CPU may be a continuous address.

Alternatively, among the chip select signals for activating each RAM of the plurality of logic processing devices, each chip select signal of the RAM used for logic processing is selected so that the address as viewed from the CPU is continuous. Means for converting the address of the signal as viewed from the CPU may be provided.

Also, an address counter, a logic circuit for outputting a predetermined logic processing result in response to an input of an address signal, and a RAM for outputting a logic processing result in accordance with data previously written in response to the input of the address signal
And an address signal output by the address counter and the CPU
And a first selector for selecting an address signal from the CPU and inputting it to the logic circuit, and selecting an address signal output from the address counter and an address signal from the CPU to select an address signal.
A second selector for inputting to the AM, a third selector for selecting and outputting an output signal of the logic circuit and an output signal of the static RAM, and means for connecting a CPU data bus to the logic circuit and the RAM, respectively. A logic processing device having the same is also provided.

In this logic processing device, when an address signal from the CPU is selected by the first selector and input to the logic circuit, the output data of the logic circuit is converted to the C signal.
When the CPU reads the address signal from the CPU through the PU bus and selects the address signal from the CPU by the second selector and inputs the selected address signal to the static RAM, the data read into the CPU can be written into the RAM via the CPU bus.

Further, an address signal output from the address counter is inputted, and it is determined whether to use a logic circuit or a RAM for each address based on data held in advance, and the first and second addresses are determined. It is also possible to provide a determination switching means for switching and controlling the selectors.

The determination switching means is constituted by a RAM and a selector, and the RAM stores the data for determination as one.
The determination data held in each bit of the memory area of a predetermined bit for each address, and the determination data held in each bit of the memory area specified by the address of the upper plurality of bits of the address signal output by the address counter are simultaneously output, The selector inputs the data for determination and outputs the data for determination sequentially as a switch signal for the first and second selectors bit by bit in accordance with the address of a plurality of lower bits of the address signal output from the address counter. With such a configuration, the data for determination can be largely compressed and stored in the RAM.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram of a logic processing device according to the first embodiment. This logic processing device has two controllable CPUs (central processing units).
Although it is constituted by logic processing devices in stages, a large number of logic processing devices are actually connected in series or in parallel in a single-chip integrated circuit.

The CPU may be provided as a CPU core in the same chip, but when provided in another chip, at least the CPU interface unit is provided in the logic processing device. The first-stage and second-stage logic processing devices shown in FIG.
(SRAM) 2, selector 3 (first selector), selector 4 (second selector), and buffer 5. In the following description and drawings, the static RAM is simply referred to as RAM.

The logic circuit 1 is a hard wired logic circuit formed by a combination of a gate circuit that outputs a predetermined logic processing result with respect to an input signal, and does not include a latch circuit or a feedback circuit inside. In such a logic circuit, when given input data is given, fixed data is output after a certain delay time.
The relationship between the input and the output is the same as the relationship between the address of the memory and the data.

The RAM 2 is a memory which can be accessed at high speed, is selectively activated by a chip select signal CS1 or CS2, and outputs a logic processing result according to pre-written data when an input signal is inputted,
Substitute the function of the hard wired logic circuit 1.

The selector 3 receives the switching signal S1 or S2
Thus, the input signal and the address signal from the CPU are selected and input to the RAM 2. The selector 4 selects an output signal of the logic circuit 1 and an output signal of the RAM 2 according to the switching signal S1 or S2 and outputs the selected signal.

For example, when the switching signal S1 or S2 is "0", the selector 3 stores the CPU address in the RAM.
The selector 4 switches the output of the logic circuit 1 to a signal output so that the input signal is input to the RAM 2, and when the switching signal S1 or S2 is "1", the selector 3 inputs the input signal to the RAM 2. And the selector 4 is switched so that the output of the RAM 2 becomes a signal output.

The buffer 5 has a control signal BS1 or BS2.
On / off control to connect / disconnect the input / output data bus of the RAM 2 to / from the CPU data bus.
After the signal output of the first-stage selector 4 is latched and synchronized with the first-stage operation clock by the latch circuit 6,
The signal is input to the second-stage logic processor together with the new signal input.

According to the logic processing device of this embodiment, the signal input is logically converted by the logic circuit 1 and output via the selector 4 immediately after creation or when there is no problem in the function of the logic circuit 1. Also, by the selector 3,
The CPU address, which is an address signal from the CPU, is
When inputting to M2, the buffer 5 is turned on and R
The input / output data bus of AM2 is connected to the CPU data bus, and data for logic processing can be written from the CPU to the memory area of the designated address in RAM 2 through the CPU data bus.

Therefore, logic processing data obtained by partially modifying the logic of the logic circuit 1 or adding logic can be easily written in the RAM 2. After that, when the selector 3 is switched to the signal input side and the selector 4 is switched to the RAM 2 side, the input signal is input to the RAM 2, logically converted and output, and output via the selector 4. Logic processing in which functions are partially changed or added can be easily performed.

The second-stage logic processing device logically converts a signal obtained by latching the signal output of the first-stage logic processing device by the latch circuit 6 or another signal input by the logic circuit 1 or the RAM 2 and outputs the converted signal. I do.
The first-stage and second-stage RAMs 2 are arranged at different addresses, and data for logic processing can be individually written from the CPU side.
It can be individually activated and used by S2. The same applies to the case where a multi-stage logic processing device is provided.

Since most of the inside of an integrated circuit such as an ASIC is a repetition of such a logic circuit and a latch circuit, a portion of the logic circuit that is likely to be changed is replaced with a RAM in this way. This allows the logic to be modified after the chip is completed.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram of a logic processing device according to the second embodiment. This second
This embodiment is provided with a plurality (three in the example of FIG. 2) of logic processing devices including the logic circuit 1, the RAM (SRAM) 2, and the selectors 3 and 4 shown in the first embodiment. Each logic processing device shown in FIG.
It has a bus including a buffer that connects the input / output data bus of AM2 to the CPU data bus, but is not shown.

Of the three logic processing devices,
(A) indicates that when the chip select signal CS1 becomes "1", R
AM2 becomes active, and the selectors 3 and 4 are switched by the switching signal S1. In (B), when the chip select signal CS2 becomes "1", the RAM2 becomes active, and the selectors 3 and 4 are switched by the switching signal S2. In (C), when the chip select signal CS3 becomes "1", the RAM 2 becomes active, and the selectors 3 and 4 are switched by the switching signal S3. All of these logic processing devices (A) to (C) can operate with either the logic circuit 1 or the RAM 2.

As shown in FIG. 3, the chip select signals CS1 to CS3 respectively correspond to three consecutive address areas in the RAM address space viewed from the CPU. CS1 to CS3 are generated. By making the addresses in the RAM area continuous in this manner, the entire logic processing devices (A), (B), and (C) shown in FIG.
When operating with R, each R not used for logic processing
The AM 2, 2, and 2 form a continuous RAM address space as viewed from the CPU, and can be accessed from the CPU side in the same manner as a normal RAM.

Next, a third embodiment of the present invention will be described with reference to FIGS. This third embodiment is shown in FIG.
As in the second embodiment shown in FIG. 7, the logic circuit is composed of a plurality of logic processing devices. Are made continuous so that the CPU can use the RAM 2 that is not used as a substitute for the logic circuit 1 as a normal RAM area.

For example, there are N logic processing units,
Each of the RAMs 2 is connected to a chip select signal CS1 to CS1.
In the one that can be activated by CSN to substitute for the logic circuit 1, only the RAM2 of the first, second, and third logic processing devices activated by the chip select signals CS1, CS4, and CS5 are used. The case of using for proxy will be described.

In this case, the chip select signals CS2, C
RAM activated by S3 and CS6-C
Since the RAM activated by the SN is not used as a substitute for the logic circuit 1, the CPU wants to use it as a normal RAM area. However, since the RAM address space seen from the CPU side is not continuous, its use is restricted. I will. For example, even if it is desired to use the second and third RAMs activated by the chip select signals CS2 and CS3 as stack areas, there are only two continuous RAM areas, and the fourth RAM substitutes for a logic circuit. And cannot be used. Therefore, the stack flows immediately, and the stack cannot operate satisfactorily.

In order to solve this problem, a switching circuit 7 as shown in FIG. 4 is provided in the third embodiment.
The switching circuit 7 is also a variable logic circuit composed of a RAM or the like, and receives input chip select signals CS1 to CS1.
The chip select signal for activating the RAM 2 by switching the order of the CSN is continuous in ascending order of the address in the RAM address space as viewed from the CPU side, and thereafter the RAM
2 are rearranged and output so that chip select signals that do not activate 2 are continuous.

In the example shown in FIG. 4, the chip select signals CS1 to CSN inputted to the switching circuit 7 are CS1 and CSN.
Are rearranged in the order of S4, CS5, CS2, CS3, CS6,... And output. As a result, as shown in FIG. 5, the area of the RAM (the RAM activated by the chip select signals CS1, CS4 and CS5) used as a substitute for the logic circuit is allocated to the first area in the RAM address space as viewed from the CPU side. , And the other RAM areas can be used as continuous address areas.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a logic processing device according to the fourth embodiment. This logic processing device generates a signal input in each of the above-described embodiments by reading a microprogram by an address counter 10 and generating the logic circuit 1 or a RAM (SRA).
M) The output signal subjected to logic processing by 2 is commanded
The data is decoded by the decoder 14 to perform register control, arithmetic control, jump control, and the like.

The logic circuit 1 and the RAM 2 are the same as those shown in FIG. Then, the address signal output from the address counter 10 and the address signal (CP
Selector 11 (first selector) for selecting the U address) and inputting it to the logic circuit 1, and a selector 12 (selecting the address signal output from the address counter 10 and the address signal from the CPU and inputting them to the RAM 2). The second selector), the output signal of the logic circuit 1 and the RAM
Selector 13 (third output signal) for selecting and outputting the second output signal.
Selector). Each selector 11, 1
The lines of the switching signals 2 and 13 are not shown.

A bus having a buffer 5 for connecting the CPU data bus to the input / output data bus of the RAM 2;
Buffer 1 connected to output data bus of logic circuit 1
5 having a bus.

When a CPU address is selected by the selector 11 and input to the logic circuit 1, the output data of the logic circuit 1 can be read into the CPU via the CPU bus by turning on the buffer 15.
Thereafter, by selecting the CPU address by the selector 12 and inputting it to the RAM 2 and turning on the buffer 5, the data previously read by the CPU can be transferred to the RAM 2 via the CPU bus and written.

By repeating this operation while changing the CPU address, it is possible to write all the contents of the logic processing of the logic circuit 1 into the RAM 2. In this way, after writing the contents of the logic circuit 1 in the RAM 2, by modifying the data only in the necessary places, the microprogram for logic processing can be easily modified, and the data acting on behalf of the Rossic circuit 1 can be stored in the RAM 2. Can be stored.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a block diagram showing a logic processing device according to the fifth embodiment. In FIG. 7, parts corresponding to the respective parts in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. Note that the logic processing device shown in FIG. 7 does not include a bus having the selector 11 and the buffer 15 provided in the logic processing device of FIG. 6, but these may be provided.

In this embodiment, the switching RAM
20 is provided. Switching RA
M20 receives a counter address, which is an address signal output from the address counter 10, and determines, for each address, whether to use the logic circuit 1 or the RAM 2 based on the determination data held in advance, This is a determination switching unit that controls switching of the first and second selectors 12 and 13, and in this example, an SRAM is used.

In the above-described fourth embodiment, whether to use the SRAM 2 comprising the logic circuit 1 for the logic processing microprogram is determined collectively. In this case, if the microcode program is stored and operated in the RAM 2, even if there is an unused memory area in the RAM 2, it cannot be used as a normal RAM from the CPU side.

Therefore, in the logic processing device according to the fifth embodiment shown in FIG. 7, a switching RAM 20 is provided, and a switching RAM 20 is provided for each address corresponding to all the addresses of the RAM 2.
As shown in (a) of FIG.
One-bit determination data “0” or “1” indicating whether to use AM2 is stored. When "0" is stored, the logic circuit 1 is used. When "1" is stored, the RAM 2 is used.
Is used to perform a logic operation.

FIG. 8B shows microcode data for each address on the logic circuit 1 side, and FIG.
The microcode data for each address on the M2 side is shown with halftone dots. The portion where the halftone dot is not applied in FIG. 8C, that is, the memory area of the address where the data of FIG. 8A is “0” can be used as a normal SRAM by the CPU.

However, when the CPU actually accesses that part of the RAM 2, the bus uses the address counter 10.
Therefore, it is necessary to apply a wait to the command decoder 14 and control the units subsequent to the command decoder 14 so as not to operate.

Next, a sixth embodiment of the present invention will be described with reference to FIGS. Switching RA in FIG.
In M20, 1-bit determination data "0" or "1" is stored for each address corresponding to all addresses of the RAM 2 where logic processing is performed. Therefore, for example, 1024 addresses from 0 to 1023 are required. In this case, one word is 16
Using a bit RAM, as shown in FIG.
A memory capacity of 6 × 1024 = 16384 bits is used, and data for determination is stored only in the last bit (bit 15) of each word, for example.

In this case, most of the memory area of the RAM 20 is wasted, and it is wasteful to use it as a normal RAM. In order to be able to use this RAM 20 as a normal RAM depending on the mode, it is necessary to change (compress) the data structure.

Therefore, in the logic processing device according to the sixth embodiment, this determination switching means is provided as shown in FIG.
A selector 21 is provided on the input side and a selector 22 is provided on the output side, in addition to the switching RAM 20 using an SRAM. Also, the input / output data length of the RAM 20 is expressed as CP
A buffer 23 connected to the U data bus is also provided. This buffer 23 is turned on / off by a buffer control signal BS.
Controlled off.

When data is read / written by the CPU, the selector 21 is switched to the CPU address side by the switching signal S, and the CPU address A6
A1 are input to the switching RAM 20 through the selector 21 and are used as a 64-word RAM. At that time, the buffer 23 is also turned on so that the CPU can transfer write data and read data read from the switching RAM 20 to the CPU.

As a result, as shown in FIG. 11, every 64 words at addresses 0-63 of the switching RAM 20 (one word is composed of 16 bits 0-15) are shown in FIG. In the storage state, data for determination of 16 addresses can be stored, and 64 data can be stored.
The word can store the data for determination of 1024 addresses as in the case shown in FIG.

The memory capacity is 16 × 64 = 1024
Just a bit. This is 1/10 of the case shown in FIG.
As described below, an extremely small-capacity SRAM can be used as the switching RAM 20, but when an SRAM having the same capacity as that in FIG. 10 is used, most of the remaining memory area can be used as a normal RAM by the CPU. .

The address counter 1 shown in FIG.
When reading the data for switching the judgment by 0,
The selector 21 is switched to the counter address side by the switching signal S, and the buffer 23 is turned off. Thereby, the upper bits A9 to A4 of the counter address from the address counter 10 are input to the switching RAM 20 via the selector 21, and the addresses 0 to 0 shown in FIG.
63 data of 64 words are read out 16 times per word and input to the selector 22.

On the other hand, the lower bit A3 of the counter address
To A0 as a switching signal to the selector 22, and the data read from the switching RAM 20 is sequentially selected bit by bit to select the selectors 12 and 13 shown in FIG.
Is output as a switching signal.

For example, if the addresses of A9 to A0 are 0 to 15,
Up to this point, the upper A9 to A4 remain "0", so that the determination data of one word (16 bits) at address 0 is read from the switching RAM 20 16 times. During this time, the lower A3 to A0 sequentially change from “0 to 15”, so that the selector 22 sequentially selects the determination data from the 0th bit to the 15th bit of the read 16-bit data one bit at a time. Then, it is output as a switching signal.

In this way, data for determination of 1024 address spaces can be stored with 64-word data.
When the proxy processing by the RAM 2 shown in FIG. 7 is not performed at all addresses, not only the RAM 2 but also the entire area of the switching RAM 20 is transferred from the CPU to the normal RA.
M can be used. In addition, switching RA
Rewriting of the determination data into M20 can be easily performed by the CPU.

[0054]

As described above, the logic processing device according to the present invention can correct the logic even after the completion of the integrated circuit chip without using the mask ROM. In addition, when the logic is not modified, the SRAM for the logic circuit can be used as a normal RAM. Further, the RAM address of each SRAM which can be used as a normal RAM, as viewed from the CPU side, can be continuous, so that the memory can be used more flexibly.

Further, by allocating the logic processing data of the hard wired logic circuit to an address space as viewed from the CPU, the logic processing data is read by the CPU address, and the data is transferred and written to the SRAM. By partially correcting the written data, the logic can be easily corrected.

Furthermore, since it is possible to switch between using a logic circuit and using a RAM for each address, areas other than the addresses where the logic processing is corrected by the RAM can be used as a normal RAM by the CPU. Then, the data for switching determination is compressed and stored in a normal SRAM, so that the S for storage is stored.
The capacity of the RAM is greatly reduced, and the area where the data for the determination is not stored, and when not all the data is stored, the entire area can be used as a normal RAM area by the CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a logic processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a logic processing device according to a second embodiment of the present invention;

FIG. 3 is a graph showing R as viewed from a CPU for each RAM 2;
FIG. 3 is a diagram illustrating a usage state of a part of an AM address space.

FIG. 4 is an explanatory diagram of a chip select signal switching circuit provided in a logic processing device according to a third embodiment of the present invention;

FIG. 5 is a diagram showing a usage state of a part of a RAM address space viewed from a CPU after switching by the switching circuit 7;

FIG. 6 is a block diagram showing a logic processing device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a logic processing device according to a fifth embodiment of the present invention.

8 is a diagram showing the determination data stored in the switching RAM 20 and the usage status of each address area of the logic circuit 1 and the RAM 2. FIG.

FIG. 9 is a block diagram of a judgment switching means provided in a sixth embodiment of the present invention.

FIG. 10 is a diagram showing a storage state of data for determination in a switching RAM 20 in FIG. 7;

FIG. 11 is a diagram showing a storage state of data for determination in a switching RAM 20 in FIG. 9;

[Explanation of Signs] 1: Logic circuit (hard wired logic circuit) 2: RAM (static RAM: SRAM) 3: Selector (first selector) 4: Selector (second selector) 5, 15, 23: Buffer 10: Address counter 11: Selector (first selector) 12: Selector (second selector) 13: Selector (third selector) 14: Command decoder 20: Switching RAM 21, 22: Selector

Claims (6)

[Claims] 1. A logic processing device controllable by a CPU, comprising: a hard wired logic circuit for outputting a predetermined logic processing result with respect to an input signal; A static RAM that outputs a logic processing result, a first selector that selects the input signal and an address signal from the CPU and inputs the selected signal to the static RAM, an output signal of the hard wired logic circuit, A second selector for selecting and outputting an output signal of a static RAM; and a means for connecting a CPU data bus to the static RAM, wherein the first selector selects an address signal from a CPU and When input to the static RAM,
A logic processing device, wherein data for logic processing can be written to the static RAM through the CPU data bus. 2. A plurality of logic processing devices according to claim 1, wherein each of the static RAMs is selectively activated by a chip select signal, and an address of the chip select signal as viewed from the CPU is continuous. A logic processing device, wherein the address is set to a predetermined address. 3. The logic processing device according to claim 2, wherein, of the chip select signals for activating each static RAM of the plurality of logic processing devices, the C of the chip select signal of the RAM used for logic processing is selected.
A logic processing device comprising means for converting addresses of each chip select signal as viewed from the CPU so that addresses as viewed from the PU are continuous. 4. A logic processing device controllable by a CPU, comprising: an address counter; a hard wired logic circuit for outputting a predetermined logic processing result in response to an input of an address signal; RAM that outputs a logic processing result according to data written in advance
And an address signal output from the address counter and C
A first selector for selecting an address signal from a PU and inputting the selected signal to the hard wired logic circuit; an address signal output by the address counter;
A second selector for selecting an address signal from a PU and inputting the selected signal to the static RAM; and a third selector for selecting and outputting an output signal of the hard wired logic circuit and an output signal of the static RAM. And a means for connecting a CPU data bus to the hard wired logic circuit and the static RAM, respectively, wherein the first selector selects an address signal from the CPU and inputs the hard wired logic circuit. Then, when the output data of the hard wired logic circuit is read into the CPU via the CPU bus, an address signal from the CPU is selected by the second selector and input to the static RAM. Loaded into RAM into the CPU Logic processing device characterized by being configured to over data to be written through the CPU bus. 5. A logic processing device controllable by a CPU, comprising: an address counter; a hard wired logic circuit for outputting a predetermined logic processing result in response to an input of an address signal; RAM that outputs a logic processing result according to data written in advance
And an address signal output from the address counter and C
A first selector for selecting an address signal from a PU and inputting it to the static RAM; and a second selector for selecting and outputting an output signal of the hard wired logic circuit and an output signal of the static RAM. Means for connecting a CPU data bus to the static RAM; and inputting an address signal output from the address counter to determine whether to use the hard wired logic circuit or the static RAM for each address. And a switching unit that controls the switching between the first and second selectors based on data stored in advance. 6. The logic processing device according to claim 5, wherein the determination switching means comprises a static RAM and a selector, and the static RAM stores the determination data in a predetermined bit for each address. The determination data held in each bit of the memory area, and the determination data held in each bit of the memory area specified by the address of the upper plurality of bits of the address signal output by the address counter are simultaneously output, and the selector performs the determination. Input data, and output the determination data sequentially as a switching signal for the first and second selectors, one bit at a time, in accordance with the address of a plurality of lower bits of the address signal output by the address counter. A logic processing device, comprising: