JPH10290151A - Gate control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use the gate control circuit that applies on/off control to a gate control element such as a DMOS connecting to a power supply voltage with a low voltage signal with high accuracy even when the power supply voltage changes over a wide range. SOLUTION: The circuit includes a control transistor(TR) 10 that is connected to a low voltage side, receives a low voltage signal Sd and is operated in on/off operation, a Zener diode 20 connected between a gate of a power supply control element and a power supply voltage point V in a reverse bias direction, a current mirror circuit consisting of a reference TR 11 and a follower TR, and a current path 30 that is opened/closed with the on/off operation of the control TR 10 as the follower TR. A breakdown voltage of the Zener diode 20 is set higher than an operation threshold voltage of a gate of the gate control element 1 and lower than a dielectric voltage so that the gate control element 1 is conductive at all times by a prescribed breakdown voltage of the Zener diode 20 thereby avoiding the effect of the power supply voltage V.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display driving circuit operating under a power supply voltage of several tens to several hundreds of volts for driving a plasma display panel, an electroluminescence display panel, a fluorescent display panel, or the like according to video data. More particularly, the present invention relates to a gate control circuit suitable for controlling on / off of a gate control element such as a MOS transistor connected to a high voltage side by a low voltage signal of about 5V.

[0002]

2. Description of the Related Art In a drive circuit for a display panel or the like described above, a power supply voltage for a load of, for example, 20 to 200 V is applied to an output circuit of an inverter type. In order to perform the on / off operation with a low voltage signal of 5 V, a so-called level shift circuit needs to be interposed between the low voltage signal and the high voltage side transistor. FIG. 5 shows a conventional example of an output circuit incorporating such a level shift circuit.

The right side of FIG. 5 is an output CMOS inverter having a p-channel transistor 1 and an n-channel transistor 2 between a power supply voltage point V and a ground point E.
As described above, while the transistors 1 and 2 are alternately turned on and off as usual, an output voltage Vo for driving the load is taken out from an interconnection point between the two. For example, a control transistor 3 is provided on the ground point E side for turning on / off the high-voltage transistor 1 by a low-voltage signal Sd which is video data, and is connected to the power supply voltage point V via two resistors 3a and 3b. Connecting. A complementary signal of the low voltage signal Sd is supplied to the output transistor 2 on the side of the ground point E, and the low voltage signal Sd obtained by inverting the complementary signal by the inverter 4 including the complementary transistors 4a and 4b is supplied to the control transistor 3.

The control transistor 3 and its series resistors 3a and 3b
Is a level shift circuit for transmitting the low voltage signal Sd to the transistor 1 on the high voltage side. The transistor 1 is turned on only when the control transistor 3 is turned on by operating the gate by the voltage drop generated in the resistor 3a. Voltage signal
The same on / off operation as that of the control transistor 3 according to the high / low state of Sd is performed. The transistor 2 on the ground point side receiving the complementary signal of the low voltage signal Sd performs the reverse on / off operation.

[0005]

As described above, in the conventional level shift circuit, the power supply voltage V is divided by the resistors 3a and 3b to generate a control voltage for the gate of the transistor 1 on the high voltage side. Make sure transistor 1
There is a restriction that the level shift circuit must be set higher than the gate operation threshold value and lower than the gate withstand voltage. Therefore, an output circuit incorporating this level shift circuit as a gate control circuit operates at a power supply voltage V suitable for various uses. There is a problem that cannot be done.

[0006] For example, in an output circuit for driving a display panel, a power supply voltage V in a range of 20 to 200 V depending on the type of the display panel.
The gate of the transistor 1 on the high voltage side generally has an operation threshold of about 2 V and a withstand voltage of about 20 V. Now, if the power supply voltage V is divided by 1/10 by the resistors 3a and 3b to create a control voltage for the gate of the transistor 1, the value becomes 2V when the power supply voltage V is 20V and 20V when the power supply voltage V is 200V. Therefore, the above-described operation threshold and the restriction on the breakdown voltage are temporarily satisfied. However, in practice, this gate control voltage is set to 4 V or more, which is twice the operation threshold, to ensure the operation of the transistor 1. In order to guarantee the safety of the gate, it is necessary to set the voltage to 10 V or less which is half of the withstand voltage.

Therefore, the range of the power supply voltage V to which such an output circuit can be applied is actually 40 to 100 V. Of course, if the setting of the voltage dividing ratio of the power supply voltage V by the resistors 3a and 3b is changed, the applicable voltage range can be shifted to the high voltage side or the low voltage side, but the gate control voltage is changed as described above. As long as there is a restriction of 4 V or more and 10 V or less, the ratio between the lower limit and the upper limit of the voltage range can be easily understood. It does not exceed the ratio of 2.5 times. It should be noted that lowering the operating threshold value of the gate of the transistor 1 for the output circuit and raising the withstand voltage value can alleviate the constraint. However, since both characteristics are in a mutually contradictory relationship as is well known, this solution is generally taken. Have difficulty.

It is an object of the present invention to provide a gate control circuit which can solve the above-mentioned problems of the prior art and can be applied even when the power supply voltage changes over a wide range.

[0009]

According to the present invention, there is provided a circuit for controlling on / off of a gate control element connected to a high voltage side by a low voltage signal, wherein the circuit is connected to the low voltage side. A control transistor that turns on and off in response to a low voltage signal, a zener diode connected in the opposite direction between the gate of the gate control element and the high voltage power supply point,
A current path opened and closed by the on / off operation of the control transistor by mutually coupling the gate of the gate control element and the control transistor, wherein the breakdown voltage of the Zener diode is higher than the gate operation threshold of the gate control element and the gate withstand voltage thereof A current mirror circuit that uses a driven transistor of a current mirror circuit that starts and stops operation in response to a low voltage signal for a control transistor by setting the lower transistor to a lower voltage than a high voltage transistor This is achieved by making the shape of the side transistor the same.

The gate control element is, for example, a MOS or DMOS transistor. With the current mirror circuit having the above configuration, a constant current consumption flows through the current path regardless of the power supply voltage. As described above, the breakdown voltage of the Zener diode is set in accordance with the operating threshold value and the withstand voltage value of the gate of the gate control element, but it is usually preferable to set it in the range of 4 to 10 V, especially in the range of 7 to 10 V. It is preferable to set within. When such a Zener diode is incorporated in an integrated circuit device, a diode layer having a high impurity concentration for the Zener diode is provided with a MOS type or a DM type as a gate control element.
It is advantageous to make the OS type transistor by simultaneous diffusion with the source layer of the same conductivity type in order to simplify the wafer process as much as possible.

According to the present invention, since the gate control voltage for the gate control element on the power supply voltage side is formed by resistance division as in the prior art, the voltage range applicable to the gate control circuit is as described above, no matter how the division ratio is set. Paying attention to the fact that the operation threshold and withstand voltage value of the gate of the controlled element cannot escape the restriction, the Zener breakdown voltage is set to be lower than the operation threshold of the gate of the controlled element as described in the configuration of the preceding section. A Zener diode set high and lower than the withstand voltage is connected in the reverse direction between this gate and the high voltage power supply point to generate a constant breakdown voltage as an ON control voltage for the controlled element, and Connecting the gate to a control transistor that is turned on and off by receiving a low voltage signal via a current path (this transistor is a driven transistor of a current mirror circuit) Thus, it is obtained so as to be easily applied always kept constant regardless of the gate control voltage for turning on the operation of the controlled device to the supply voltage, thus the gate control circuit in a wide range of supply voltages.

In the current mirror circuit, the shape of a low-voltage side transistor (hereinafter referred to as a reference transistor) is changed to a high-voltage side transistor (the aforementioned control transistor).
In this case, the variation in the constant current value of the current mirror circuits formed in a large number in the semiconductor chip can be reduced, and the variation in the switching characteristics and the power consumption of the gate control element can be reduced.

[0013]

FIG. 1 shows an embodiment in which a driven transistor of a current mirror circuit is used as a control transistor. The same reference numerals are given to the portions corresponding to FIG. 5 described before this figure, and the description of the overlapping portions will be omitted as appropriate. FIG. 4 shows a structural example when the gate control circuit according to the present invention is incorporated in an integrated circuit device.

An inverter type output circuit shown on the right side of FIG. 1 is for driving each pixel of a display panel, for example, and is a p-channel type M which is a gate control element 1 on the high voltage power supply V side.
The OS transistor and the DMOS transistor are alternately turned on and off by a low voltage signal Sd of 5 V, for example, video data. On / off control is performed. In order to control the gate control element 1 on the high voltage side, an n-channel type control transistor 10 is connected to the ground point E on the low voltage side as in the prior art, and a high-low logic of the low voltage signal Sd received at the gate is provided. On / off operation is performed according to the state.

In the present invention, a Zener diode 20 is connected between the gate of the gate control transistor 1 on the high voltage side and the high voltage power supply point V in a direction in which a reverse bias is applied, and
In addition to coupling with the control transistor 10 via 30, the breakdown voltage of the Zener diode 20 is set higher than the operating threshold of the gate of the gate control element 1 and lower than the breakdown voltage. When the operation threshold value is 2 V and the withstand voltage value is 20 V, the breakdown voltage is preferably set to 4 to 10 V, more preferably 7 to 10 V. The current path 30 is opened and closed as the control transistor 10 is turned on and off, and transmits the designation of the on / off operation by the low voltage signal Sd to the gate control element 1. In this embodiment, the current flowing when the control transistor 10 is turned on is set in this. For this purpose, a current mirror circuit using the control transistor 10 as a driven transistor is used.

The reference transistor 11 of this current mirror circuit
For example, a current mirror circuit is provided by applying a reference current through a resistor 12 receiving a stabilized constant power supply voltage Vd of 5 V, and turning on and off a transistor 13 connected in parallel to the reference transistor 11 according to a low voltage signal Sd. The constant current equal to the reference current is caused to flow through the current path 30 by the control transistor 10 which is a driven transistor. It is preferable that the reference current, that is, the current flowing through the current path 30 is set to about 100 μA by using a resistor having a resistance of several tens of kΩ. Other parts of the embodiment of FIG. 3 are the same as those of FIG.

Since the reference transistor 11 of the current mirror circuit operates with the constant power supply voltage Vd of 5 V as described above, it is generally formed with a CMOS structure (see 1 in FIG. 4) described later. It is. Usually, a large number of such mirror circuits are integrated in a semiconductor chip and drive a plurality of gate control elements 1. If there is a difference between the characteristics of the reference transistor 11 and the characteristics of the control transistor 10 on the high voltage side, the constant current value varies between the mirror circuits, and the switching characteristics and the current consumption vary between the driven gate control elements 1. The problem of coming out occurs. As a countermeasure, the reference transistor 11 on the low voltage side also has a DMOS structure having the same shape as the control transistor 10 on the high voltage side, and is arranged adjacent to the reference transistor 11 so that the characteristics of the reference transistor 11 and the control transistor 10 are matched. This DMOS structure is the same as 2 in FIG. 4 described later.

FIG. 2 shows the output characteristics of the transistors 10 and 11, and FIG. 3 shows the main part of the current mirror circuit. 4 and 5, the current flowing through the reference transistor 11 is represented by I
_R0, and the current flowing through the control transistor 10 is I _R. The drain-to-source voltage of the reference transistor 11 V _R
And the drain-source voltage of the control transistor 10 is V
If you and DS, V _R is the both of the gate voltage. When both transistors are fabricated to have the same characteristics, I _R0
= I _R , resulting in an ideal mirror circuit. However, if the characteristics of the two transistors vary, a current difference of ΔI _R [(absolute value of (I _R −I _{R 0} )]) occurs, as shown in FIG.

Next, an example of the structure of main circuit elements suitable for incorporating the gate control circuit 40 of the present invention into an integrated circuit device will be described with reference to FIG. Zener diode in the upper part of Fig. 4
20 and a p-channel DMOS transistor as the gate control element 1, an n-channel DMOS transistor as the gate control element 2 in the middle stage, an n-channel transistor 11 for low breakdown voltage and a p-channel depletion type as the constant current element 32 in the lower stage Each shows a cross-sectional structure of a transistor. Also, terminals derived from these circuit elements are denoted by reference numerals corresponding to FIG.

As shown in the drawing, an n-type buried layer 52 is diffused on the surface of a p-type semiconductor substrate 51 on the wafer of the integrated circuit device 50, and an n-type epitaxial layer 53 is grown. Using a diffusion of the p-type junction isolation layer 54 in the range,
A major portion of the surface is covered with a thick oxide film 55 by an L0COS method or the like for an element isolation film or a field oxide film. In the Zener diode 20 shown on the left side of the upper part of the figure, an n-type wall layer 56 is deeply diffused from the surface of the epitaxial layer 53 to reach the buried layer 52, and then a p-type diode layer 64 and an n-type
As shown in the figure, a diode layer 67 of the p-type is diffused in the surface portion with a high impurity concentration of 1020 atoms / cm3 or more, and the current at the time of Zener breakdown is reduced from the p-type diode layer 67 or the epitaxial layer 53. Flows into layer 64.

The p-channel DMOS gate control element 1 on the right side has a gate oxide film 58 and a gate 59 provided on the surface of an epitaxial layer 53, a p-type drain layer 61, and an n-type And a p-type source layer 63 with a high impurity concentration on the surface of the latter. It is advantageous to form the p-type diode layer 64 of the Zener diode 20 by simultaneous diffusion with the source layer 63 in order to simplify the wafer process as much as possible.

An n-channel DMOS shown in the middle part of FIG.
The gate control element 2 of FIG. 1 first diffuses the n-type drain connection layer 56 deeply from the surface of the epitaxial layer 53 so as to reach the buried layer 52, and arranges the gate 59; And an n-type source layer
66 is diffused with a high impurity concentration. This n-channel type D
For the MOS, it is advantageous to simplify the wafer process by forming the n-type diode layer 67 of the Zener diode 20 by simultaneous diffusion with the n-type source layer 66. The gate control element 2 and the control transistor 10 of FIG.
And the reference transistor 11 have the same structure.

From the above-mentioned circuit elements, terminals are led out by a usual aluminum wiring film 69 disposed at a key point thereof, and an output circuit incorporating the gate control circuit 40 of the present invention by wiring as shown in the drawing is provided. I do. Further, the surface of the integrated circuit device 50 is covered with a usual protective film, but is omitted in FIG. 4 to avoid complication.

[0024]

As described above, in the gate control circuit according to the present invention, the control transistor is turned on and off in response to the low voltage signal, and is connected in the opposite direction between the gate of the gate control element and the power supply voltage point. A Zener diode,
The gate of the gate control element is composed of a current path that is opened and closed by turning on and off the control transistor by combining the gate of the control transistor with the control transistor. By setting the breakdown voltage of the Zener diode higher than the operating threshold of the gate of the gate control element and lower than the breakdown voltage, the gate control voltage that turns on the gate control element on the high voltage side is independent of the power supply voltage , The range of the power supply voltage applicable to the gate control circuit can be expanded.

By making the reference transistor and the control transistor the same shape, the characteristics of the reference transistor and the control transistor can be made uniform, and the current value of the control transistor can be matched with the current value of the reference transistor. Thus, the current consumption flowing through the control transistor does not become excessive, and the power consumption can be accurately set to a predetermined value.

When the circuit of the present invention is incorporated in an integrated circuit, the high impurity concentration diode layer of the Zener diode is simultaneously diffused with the source layer of the MOS transistor,
This has the effect of simplifying the wafer process and reducing the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram in which a driven transistor of a current mirror circuit is used as a control transistor in one embodiment of the present invention.

FIG. 2 is an output characteristic diagram of transistors 10 and 11

FIG. 3 is a diagram of a main part of a current mirror circuit.

FIG. 4 is a sectional view of a wafer showing a structural example of main circuit elements constituting a gate control circuit according to the present invention incorporated in an integrated circuit device;

FIG. 5 is a circuit diagram of a conventional level shift type gate control circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 High voltage side gate control element or MOS transistor 2 Low voltage side gate control element or MOS transistor 10 Control transistor 11 Reference transistor of current mirror circuit 20 Zener diode 21 Parallel resistance of Zener diode 30 Current path 40 Gate control circuit 50 Integrated circuit device 63 p-type source layer of MOS transistor 64 p-type diode layer of zener diode 66 n-type source layer of MOS transistor 67 n-type diode layer of zener diode E Ground potential point or ground potential Sd Low voltage signal V High voltage power supply point or power supply voltage Vd Low voltage power supply voltage

Claims (2)

[Claims] 1. A circuit for controlling on / off of a gate control element connected to a high voltage side by a low voltage signal,
A control transistor connected to the low voltage side to perform on / off operation in response to a low voltage signal, a zener diode connected in a reverse direction between the gate of the gate control element and the high voltage power supply point, and a gate control of the gate control element A current path opened and closed by the on / off operation of the control transistor by interconnecting the transistors, wherein the breakdown voltage of the Zener diode is set higher than the gate operation threshold value of the gate control element and lower than its gate withstand voltage value. The current mirror circuit uses a driven transistor of a current mirror circuit that starts and stops operation in response to a low voltage signal for a control transistor, and the shape of the low voltage transistor is the same as the shape of the high voltage transistor. And a gate control circuit. 2. The circuit according to claim 1, wherein the Zener diode is incorporated in the integrated circuit together with a MOS transistor as a gate control element, and a high impurity concentration diode layer of the Zener diode is simultaneously diffused with a source layer for the MOS transistor. A gate control circuit.