JPH10285560A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processor capable of reducing the possibility of erroneously detecting synchronizing signals, appropriately detecting the synchronizing signals and generating HDTV parallel digital data. SOLUTION: Serial data Ds inputted to an HD-SDI data receiver 30 are inputted through a cable equalizer 31 to a serial/parallel conversion part 32 and converted into parallel data composed of the signals of the two sets of the luminance signals Y of 10 bits and the color difference signals C of 10 bits. In a synchronizing signal detection part 33, for the four words of the data of 20 bits for which the luminance signals Y and the color difference signals C are gathered, whether or not they are appropriate as a stipulated video timing reference code is inspected. Then, in the case of detecting the video timing reference code, set bit data are extracted from the data of the forth word and the synchronizing signals Sync are generated and outputted along with the luminance signals Y and the color difference signals C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial digital video signal for high definition television (HDTV) transmitted through a serial interface.
The present invention relates to a video signal processing device that appropriately detects a synchronization signal and restores an original parallel digital video signal.

[0002]

2. Description of the Related Art SMPTE (Society of Motion Picture and T
(Elevision Engineers) 125M and a system defined by SMPTE259M as this serial interface are common. Using this method, a video signal is usually processed as 10-bit parallel data, and when transmitted via a coaxial cable or the like, is converted from parallel to serial and transmitted serially. After the transmission is completed, the data is converted from serial to parallel again and processed as parallel data.

In these video signal interfaces, a specific code called a video timing reference code is defined. By detecting this code, a digital field, a digital field blanking, an effective video signal A synchronization signal for defining a start point and an end point of the area is generated. This video timing reference code is 3FFh, 0
00h, 000h, XYZh (h indicates hexadecimal notation). The first three words are prefix information of a fixed value.
Digital field blanking, "SAV (Start of
Active Video) "ka" EAV (End of Active Video
) "Or information indicating". "

Therefore, in order to synchronize with the transmitted video signal, first, as shown in FIG.
Is detected (step S11), then 000h is detected (step S12), and further 000h is detected (step S13). When these are properly detected, a synchronization signal is generated based on the next word. Generate (Step S1
4)

In recent years, a high-definition television having a larger number of scanning lines, 1125 lines, and a wider transmission frequency band than a current television broadcast to obtain clear images and high-quality sound. (HDTV: High Denfinition Te
levision) is becoming increasingly popular. This serial digital interface for HDTV (HD-SDI: High
Definition Television-Serial Digital Interface)
Is also defined based on the plan of SMPTE259M,
The above-mentioned video timing reference code is similarly defined.

[0006]

However, the method of detecting a synchronization signal using the video timing reference code as described above has a problem that erroneous detection may occur, and improvement is particularly desired in the case of HD-SDI. Was rare. That is, data in which all bits are 1 (3FFh),
Data in which all bits are 0 (000h) is relatively easy to produce and has a high appearance probability. Therefore, 3FFh to 000h
In such a case, an erroneous synchronization signal may be output in spite of not being the timing of the synchronization signal.

Accordingly, an object of the present invention is to reduce the possibility of erroneously detecting a synchronization signal in an HDTV serial digital interface (HD-SDI), and to properly detect the synchronization signal to generate HDTV parallel digital data. To provide a video signal processing device capable of performing the above.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, when detecting a synchronizing signal using a video timing reference code for a video signal whose format is defined by HD-SDI, a larger number of signals than in the prior art is used. By using the reference code, the probability that the same data as the reference code is generated in an arbitrary signal is reduced, and the possibility of erroneously detecting the synchronization signal is reduced.

Therefore, the image processing apparatus of the present invention comprises a predetermined number of words of data each having a predetermined value converted into serial bit data and a predetermined number of words of data including predetermined information in a predetermined format. A video signal processing device for converting video data having a specified video timing reference code into original parallel video data, wherein the input serial bit data is converted to substantially parallel video data having a predetermined bit width. Serial-parallel conversion means for converting into a format luminance signal and color difference signal, and detecting the video timing reference code by detecting data of all the specified words from each of the converted luminance signal and color difference signal. A reference code detecting means for detecting the video timing reference code from each of the luminance signal and the color difference signal by the detection; When but it detected at the same timing, and a reference code determining means for determining the video timing reference code is detected for the video data.

[0010] More specifically, the video timing reference codes each have a value of 3FFh, 000h, 000h.
The data defined by three words of 0-bit data and one word of 10-bit data defined in a format as shown in Table 3, wherein the reference code determination unit performs the processing based on each of the luminance signal and the color difference signal. When the same video timing reference code is detected at the same timing, it is determined that a video timing reference code has been detected for the video data.

[0011]

[Table 3]

Here, F = 0: first field period, 1: second field period, V = 0: digital active field period, 1: digital field blanking period, H = 0: SAV, 1: EAV, P3 to P0: protection bit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the video signal (H) for HDTV transmitted as serial digital data.
HD-SDI data reception that is used in a video signal processing device that performs various processes on D-SDI data) and receives the transmitted serial data and outputs it as HDTV parallel digital video data that can be arbitrarily processed The device will be described.

First, HDTV digital video data used in this embodiment will be described with reference to FIG. FIG.
FIG. 2 is a diagram for explaining the format of the HDTV parallel digital video data. In the data shown in FIG. 1, EAV and SAV are video timing reference codes for detecting such a format of a video signal for each line. In the EAV and the SAV, the same information is transmitted at the same timing for the luminance signal Y and the color difference signal C.

LNO is a line number word, C
RCC (Cyclic Redundancy CheckCode) is a cyclic redundancy check code. This CRCC is given as a calculation section from the SAV of the previous line to the immediately preceding EAV and the line number word. By comparing the transmitted CRCC word with the recalculated CRCC result, an error in that section is generated. Can be detected.

Table 4 shows the specific contents of the video timing reference code.

[0017]

[Table 4]

Here, F = 0: first field period, 1: second field period, V = 0: digital active field period, 1: digital field blanking period, H = 0: SAV, 1: EAV, P3 to P0: protection bit.

As shown in Table 4, the first three words of the video timing reference code are 3FFh, 000h, 000.
This is prefix information of a fixed value h. In the fourth word, digital field, digital field blanking, identification information of EAV or SAV is set, and a protection bit is determined according to these values. Therefore, the fourth word is any of the eight types of data shown in Table 5.

[0020]

[Table 5]

Such parallel data is usually converted into serial data by arranging each word in order from the LSB (bit 0) direction, and is provided for transmission or the like.

Next, the configuration of the HD-SDI data receiving apparatus of this embodiment will be described. Figure 2 shows the HD-SD
FIG. 2 is a block diagram showing a configuration of an I data receiving device 30.
The HD-SDI data receiving device 30 includes a cable equalizer 31, a serial-parallel converter 32, and a synchronization signal detector 33. The cable equalizer 31 corrects a distortion generated when the transmission data passes through the cable 20, reproduces the original signal, and outputs the original signal to the serial-parallel conversion unit 32. The serial-parallel converter 32 converts the serial data input from the cable equalizer 31 into 20-bit parallel data consisting of 10 bits of a luminance signal Y and 10 bits of a color difference signal C, and outputs the parallel data to a synchronization signal detector 33.

The synchronizing signal detector 33 detects a video timing reference code from the luminance signal Y and the color difference signal C input from the serial-parallel converter 32, generates a synchronizing signal based on the video timing reference code, and generates the synchronizing signal. And a video signal to be subjected to signal processing together with the color difference signal C. As described above, in the luminance signal Y and the color difference signal C, the video timing reference codes EAV and S
AV is transmitted at the same timing. Therefore, the synchronizing signal detecting unit 33 can process the luminance signal Y and the color difference signal C as a set, assuming that the data is 20-bit parallel data. By this processing, a specified video timing reference code of 4 words is detected.

The process of detecting the video timing reference code and generating the synchronization signal in the synchronization signal detecting section 33 will be described with reference to the flowchart shown in FIG.
In the synchronization signal detection unit 33, first, the data YDATA and CDATA for each word of the luminance signal Y and the color difference signal C input from the serial-parallel conversion unit 32.
Are both 3FFh (step S1). If both are 3FFh,
Next, the input data YDATA, CDATA is 000.
h is checked (step S2). If both are 000h, it is further checked whether or not the next input data YDATA, CDATA is 000h (step S3).

Then, in step S3, the data Y
If DATA and CDATA are both 000h, it is checked whether the next input data YDATA and CDATA are appropriate data as the fourth word of the video timing reference code. That is, it is checked whether the data is any of the eight types of data shown in Table 5 (step S4). If it is determined in step S4 that the input data YDATA, CDATA is appropriate data as the fourth word of the video timing reference code, it is determined that the series of four input words is the video timing reference code. Then, a synchronization signal is generated with reference to the bit content of the fourth word (step S5).

FIG. 4 shows a specific configuration example of a circuit for performing the processing of detecting the video timing reference code of the synchronization signal detecting section 33. FIG. 4 is a diagram illustrating a specific configuration example of the synchronization signal detection unit 33. The synchronization signal detector 33 includes a 20-input NAND element 331, a 21-bit OR element 333, 21
A bit NOR element 335, three 1-bit delay elements 332, 334, 336, and a 21-bit comparison circuit 337 are provided. The 20-bit data of the luminance signal Y and the chrominance signal C input to the synchronization signal detection unit 33 are supplied to the 20-input NAND elements 331, 2 via the data line 338.
1-bit OR element 333, 21-bit NOR element 33
The data is input to the 5-bit and 21-bit comparison circuit 337, and each element checks whether the input data is appropriate as the data of each word of the aforementioned 4-word video timing reference code.

That is, first, the 20-input NAND element 33
1 checks whether all the 20 bits of the input data are 1 or not, and outputs 0 only when all the bits are 1. The check result of the 20-input NAND element 331 is input to the first 1-bit delay element 332 and is delayed by one clock period. Next, the 21-bit OR element 333 calculates the total of the 20 bits of the input data and the check result one clock before in the 20-input NAND element 331 input from the first 1-bit delay element 332. It is checked whether all 21 bits are 0, and 0 is output only when all bits are 0. That is, the 21-bit OR element 333 outputs 0 only when 000h is input after 3FFh. This 21
The check result of the bit OR element 333 is input to the second 1-bit delay element 334 and is delayed by one clock period.

Next, the 21-bit NOR element 335 is
Check whether all of the 20 bits of the input data, that is, all the 20 bits, and the check result of the 21-bit OR element 333 input from the second 1-bit delay element 334 one clock before are all 0. Then, 1 is output only when all the bits are 0. That is, the 21-bit NOR element 335 is 3FFh, 000h, 000
1 is output only when h is continuously input. This 21
The check result of the bit by the NOR element 335 is input to the third 1-bit delay element 336 and is delayed by one clock period.

The 21-bit comparison circuit 337 determines whether the 20-bit data of the input data is appropriate as the fourth word of the video timing reference code as shown in Table 5, and 21-bit NO input from third 1-bit delay element 336
The check result one clock before in the R element 335 is 1
Check whether or not. That is, in the 21-bit comparison circuit 337, 3FFh, 000h, 000h, X
YZh, which is suitable as a video timing reference code of 4
It is checked whether or not words are continuously input, and if a video timing reference code is input, necessary data is extracted from the fourth word and a synchronization signal is output.

The operation of the HD-SDI data receiving device 30 will be described together. As shown in FIG. 2, an HD-SDI data receiving device 30 provided in various video signal processing devices
For the serial data D _S which is obtained by converting the parallel digital video data D _p for HDTV in HD-SDI transmission module 10 is input via a coaxial cable 20 as a transmission path. HD-SDI serial data D _S which is input to the data receiving apparatus 30 is serially via the cable equalizer 31 - parallel converter 3
2 is converted into parallel data composed of two sets of 10-bit luminance signal Y and 10-bit color difference signal C.

Then, the synchronization signal detector 33 detects a video timing reference code from each of the luminance signal Y and the color difference signal C. In the synchronization signal detector 33,
It is checked whether four words of 20-bit data including the luminance signal Y and the color difference signal C are appropriate as specified video timing reference codes. If the video timing reference code is detected,
The set bit data is extracted from the data of the word, a synchronization signal Sync is generated, and the synchronization signal Sync is output together with the luminance signal Y and the color difference signal C. In the subsequent video signal processing section, these parallel data and the synchronization signal Sy
The desired signal processing is performed using nc.

As described above, in the HD-SDI data receiving apparatus 30 of this embodiment, both the luminance signal Y and the color difference signal C are used, and the XYZ signal including not only the prefix information of the fixed value but also the protection bit is used. Since the synchronization signal is detected using all 80 bits up to the word, the false detection rate of the synchronization signal is significantly reduced. Specifically, HD-SD
The I data receiving device 30 detects a video timing signal by comparing 20 bits × 4 words, that is, 80 bits. Conventionally, 10 bits x 3
Because we compared in 31-bit words plus 1 bit, the probability of detecting the video timing reference code incorrectly in any data will be decreased to 1/2 ^49.

The present invention is not limited to the present embodiment, and various and suitable modifications can be made within the scope of the present invention. For example, the serial data input to the HD-SDI data receiving device is not limited to data transmitted by a coaxial cable, but may be data transmitted by an arbitrary medium, data reproduced as serial data, and the like. Further, the configuration of the synchronization signal detection unit is not limited to the example shown in FIG. 4 and may be any configuration.

[0034]

As described above, according to the video signal processing apparatus of the present invention, in the HDTV serial interface, the possibility of erroneously detecting a synchronization signal is further reduced, and the HDTV parallel interface is appropriately detected by detecting the synchronization signal appropriately. A video signal processing device capable of generating digital data can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a format of HDTV parallel digital video data.

FIG. 2 is a block diagram illustrating a configuration of an HD-SDI data receiving device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a synchronization signal detection process performed by a synchronization signal detection unit of the HD-SDI data receiving device illustrated in FIG. 2;

FIG. 4 is a diagram illustrating a specific configuration example of a synchronization signal detection unit of the HD-SDI data reception device illustrated in FIG. 2;

FIG. 5 is a flowchart for explaining a conventional synchronization signal detection method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... HD-SDI transmission module, 20 ... Coaxial cable, 30 ... HD-SDI data receiver, 31 ... Cable equalizer, 32 ... Serial-parallel conversion part, 33
... Synchronization signal detector, 331 ... 20-input NAND element, 3
32: first 1-bit delay element, 333: 21-bit OR element, 334: second 1-bit delay element, 3
35 ... 21-bit NOR element, 336 ... third 1-bit delay element, 337 ... 21-bit comparison circuit

Claims (2)

[Claims] 1. A video timing reference code which is converted into serial bit data and defined by data of a predetermined number of words each having a predetermined value and data of a predetermined number of words including predetermined information in a predetermined format. A video signal processing device for converting video data into parallel video data, which converts input serial bit data into a substantially parallel luminance signal and color difference signal composed of words of a predetermined bit width. Parallel conversion means; reference code detection means for detecting the video timing reference code by detecting data of all the specified words from each of the converted luminance signal and color difference signal; and When the video timing reference code is detected at the same timing from each of the luminance signal and the color difference signal, the video Video signal processing device and a reference code determining means for determining the video timing reference code is detected for the data. 2. The video timing reference code includes three words of 10-bit data each having a value as shown in Table 1.
The reference code determination means determines the same video timing reference code based on each of the luminance signal and the chrominance signal by using one word of 10-bit data defined in a format as shown in Table 2. 2. The video signal processing device according to claim 1, wherein when video signals are detected at the same timing, it is determined that a video timing reference code has been detected for the video data. [Table 1] [Table 2]