JPH06343165A - Transmitter - Google Patents

Abstract

PURPOSE:To transmit and reproduce improved video images and sound by adding a flag to sound data corresponding to the head of a field, transmitting them, varying the delay time of video data by using the flag added to the sound data, matching the phases of the sound data and the video data and thereby matching lip-sync. CONSTITUTION:This transmitter is provided with video and sound processing parts 11 and 13, a flag adding circuit 15 for adding the flag for indicating the head of the field or frame of the video data from the video processing part 11 to the sound data from the sound processing part 13, a serializing circuit 12 for serializing the video and sound data front the video and sound processing parts 11 and 13, a control circuit for controlling a delay amount based on the video data and the flag in serial data from the serializing circuit 12 and a delay circuit for matching the phase of the sound data with the phase of the video data based on the output of the control circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission device suitable for application to, for example, a transmission device for transmitting video and audio signals using a serial interface.

[0002]

2. Description of the Related Art Video and audio signals are transmitted, for example, to AS / EBU.
As a transmission device for transmission using a serial interface such as the one shown in FIG. The transmission device shown in FIG. 5 receives video and audio data supplied from a signal source (not shown) through the input terminal 1 at the receiving circuit 2, and then sends the video data to the video processing circuit 3 and the audio data to the audio processing circuit. 4, the video processing circuit 3 performs various types of processing on the video data, the audio processing circuit 4 performs various types of processing on the audio data, and then the transmission circuit 5 converts the video and audio data into serial data and outputs the serial data. Transmit via terminal 6.

At this time, the transmission circuit 5 inserts the voice data Ad into the section of the horizontal blanking period Hbt and transmits it, as shown in FIG. That is, the video data Vd and the audio data Ad corresponding thereto are included in the horizontal scanning line period Ht.

Further, as shown in FIG. 6, video data Vd
Indicates SAV (Start) indicating the beginning of the video data Vd.
of Active Video) and EAV (End of Active V) indicating the end of video data
video) is added. Further, as shown in FIG. 7, the time code Tc of the video data is added to the vertical blanking period Vbt of the field period Vt.

By the way, there is SMPTE 259M as a serial interface standard, but a method for detecting a transmission error has not been defined therein. However, recently, a method called EDH (Error Detection Handling) for adding a check word as auxiliary data in units of one image field has been proposed and standardized.

[0006]

By the way, when transmitting video and audio data using the serial interface as described above, there is a problem that the phase of the video and the audio is deviated by the processing in the circuit.

As shown in FIG. 7, when the relationship between the phases of the original video and audio data is such that the head of the video data Vd is the audio data As1, the video processing circuit 3 and the audio processing circuit. Due to the difference in the processing time in No. 4, the original phase relationship, such as the relationship between the video data Vd and the audio data As2, is shifted during transmission.

The most obvious example of the problem that occurs when the phase difference between the image and the sound becomes large is the relationship between the image and the sound when a person is having a conversation or singing, that is, There is something called lip sync.
If the lip sync does not match, there arises inconvenience such as the relationship between the movement of the person's mouth and the voice actually output does not match.

Further, when the method of adding a check word as auxiliary data in video 1 field unit is adopted in the above-mentioned transmission apparatus, since it is defined as auxiliary data, it is unlikely to be used in all devices. , It is not possible to take compatibility between devices on this. Further, since the check word is in units of one field, and therefore, even if an error is detected, the position of the error in the field cannot be detected, so that there is a disadvantage that the video data including the transmission error cannot be corrected. It was

Further, in the above-mentioned transmission device, since the time code is transmitted only once in one field, when a transmission error occurs and the time code is destroyed, the video corresponding to this time code is transmitted. Also, there are inconveniences such that the audio data cannot be transmitted correctly.

The present invention has been made in consideration of the above points, and makes it possible to maintain the original phase relationship between the phases of video and audio data and to correct video data including transmission errors. Moreover, the present invention is intended to propose a transmission device capable of correctly transmitting video and audio data corresponding to a time code.

[0012]

According to the present invention, video and audio signal sources 11 and 13 and the beginning of the field or frame of the video signal from the video signal source 11 are added to the audio signal from the audio signal source 13. Flag adding means 15 for adding the indicated flag, and video and audio signal generation sources 11 and 1
3, serializing means 12 for serializing the video and audio signals, the control means 25 for controlling the delay amount based on the video signal and the flag in the serial signal from the serializing means 12, and the output of the control means 25. Phase control means 21, 2 for adjusting the phase of the audio signal to the phase of the video signal based on
4 and.

The present invention also provides a video and audio signal generator 1
1 and 13, a serializing means 12 for serializing the video and audio signals from the video and audio signal generating sources 11 and 13, and at least one horizontal to the video signal of the serial signals from the serializing means 12. Error detection signal adding means 16 for adding a signal for error detection every cycle
And error detecting means 20 and 23 for detecting an error in the video signal in the serial data from the serializing means 12 based on the error detecting signal added by the error detecting signal adding means 16.

The present invention also provides a video and audio signal generator 1
1 and 13, a serializing means 12 for serializing the video and audio signals from the video and audio signal generation sources 11 and 13, and a time code of one field according to the reproduction position of the video signal from the video signal generation source 11. And a time code generating means 10 for outputting at least twice.

[0015]

According to the structure of the present invention described above, the flag adding means 15 adds a flag indicating the beginning of the field or frame of the video signal from the video signal generating source 11 to the audio signal from the audio signal generating source 13. The video and audio signals are serialized by the serialization means 12, the delay amount is controlled by the control means 25 based on the video signal and the flag in the serial signal, and the phase of the audio signals is controlled by the phase control means 21, 24. Match the phase of.

Further, according to the above-described configuration of the present invention, the video and audio signals from the video and audio signal generation sources 11 and 13 are serialized by the serializing means 12, and an error is generated with respect to the video signal of the serial signals. Detection signal adding means 1
At 6, an error detection signal is added at least every horizontal period, and the error detection means 20 and 23 detect an error in the video signal based on the error detection signal.

According to the configuration of the present invention described above, the video and audio signals from the video and audio signal sources 11 and 13 are serialized by the serializing means 12 and the time code generating means 10 outputs the video and audio signals from the video signal generating source 11. The time code is output at least twice in one field according to the reproduction position of the video signal.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the transmission apparatus of the present invention will be described in detail below with reference to FIGS.

First, the transmission side will be described with reference to FIG.
In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, 10 is a time code generation circuit, which serially outputs a time code generated by multiplex operation three or more times in one horizontal period (horizontal blanking period) or in one field period (vertical blanking period). Supply to the digitization circuit 12.

Reference numeral 11 denotes a video processing unit, for example, when the transmitting side is a VTR, after subjecting the video signal reproduced by a mechanism for recording a video signal or an audio signal to a video tape cassette (not shown) to a predetermined signal processing, It is supplied to the flag addition circuit 15 and the serialization circuit 12, respectively. Here, AS / EBU is used as the serial interface.

Reference numeral 13 denotes an audio processing unit, for example, when the transmitting side is a VTR, after performing a predetermined signal processing on the audio data reproduced by a mechanism for recording video data and audio data in a video tape cassette (not shown), It is supplied to the packetizing circuit 14. The packetizing circuit 14 compresses the audio data from the audio processing unit 13 into packets. The packetized voice data is supplied to the flag addition circuit 15.

The flag adding circuit 15 detects a field from the video signal from the video processing unit 11 (from the vertical synchronizing signal of the video signal), and adds the field to the audio data from the audio processing unit 13 corresponding to the beginning of the field of the video data. Is added to the serialization circuit 12. The audio data to which the flag is added is supplied to the serialization circuit 12.

The serializing circuit 12 serializes the video data from the video processing section 11 and the audio data to which the flag indicating the head of the field from the flag adding circuit 15 is added. At this time, the serialization circuit 12 supplies the time code from the time code generation circuit 10 to the CRC addition circuit 16 after adding the time code for each line of the video data or three times or more within the vertical blanking period.

CRC (Cyclic Redundan)
The cy check) addition circuit 16 is a serialization circuit 12
A CRC code obtained by a CRC calculation circuit, which will be described later, is added to the serial data from and then transmitted through the output terminal 17.

Here, referring to FIG. 3, the CRC adding circuit 1
An example of the CRC calculation circuit configuration in 6 will be described. As shown in FIG. 3, the CRC calculation circuit in the CRC adding circuit 16 cascades the registers R0 to R3, cascades the registers R4 to R10, and registers R11 to R11.
R15 is connected in cascade, the output end of the register R0 is connected to one input end of the adder circuit (exclusive OR circuit) 28, and the input end of the register R3 is connected to the output end of the adder circuit (exclusive OR circuit) 29. Then, one input end of the adder circuit 29 is connected to the output end of the register R4, the input end of the register R10 is connected to the output end of the adder circuit (exclusive OR circuit) 30, and the adder circuit 30 is connected.
The output end of the register R11 is connected to one input end of the register R15, the output end of the adder circuit 28 is connected to the other input end of the adder circuits 29 and 30, and the other input of the adder circuit 28 is connected. At the end, the serialization circuit 12 shown in FIG.
Connected to the input terminal 27 to which serial data is supplied, and the other output terminals of the registers R0 to R15 are connected in parallel-
The input terminal of the serial conversion circuit 31 is connected, and the output terminal of the parallel-serial conversion circuit 31 is connected to the output terminal 32 also shown in FIG.

Next, the operation of the transmission side of the transmission device shown in FIG. 1 will be described. The video data from the video processing unit 11 is supplied to the serialization circuit 12 and the flag addition circuit 15, and the time code from the time code generation circuit 10 is at least three times (continuously) for each line or each field. May be separated by a predetermined distance) to the serialization circuit 12.

On the other hand, the voice signal from the voice processing circuit 13 is supplied to the packetizing circuit 14, and the packetizing circuit 1
After being packetized by compression processing in 4, the data is supplied to the flag addition circuit 15. In the flag adding circuit 15, the head of the field is detected based on the video signal from the video processing unit 11, the flag is added before the audio data corresponding to the detected head of the field, and the flag-added audio data is added. Is supplied to the serialization circuit 12.

In the serialization circuit 12, the video data from the video processing unit 11 and the audio data from the audio processing unit 13 are converted into serial data, and the time code from the time code generation circuit 10 is added and then the CRC adding circuit 16 is added. Supply to.

The serial data is, for example, 16 data shown in FIG.
Individual registers R0 to R15 and adder circuits 28, 29 and 3
0 and the CRC calculation circuit in the CRC addition circuit 16 including the parallel-serial conversion circuit 31 are supplied via the input terminal 27. CRC addition circuit 16 via input terminal 27
The serial data supplied to the CRC calculation circuit therein is added by the adder circuit 28 and then supplied to the adder circuits 29 and 30 and the register R15, respectively. The serial data supplied to the register R15 is sequentially supplied to the registers R14 to R11, further subjected to addition processing in the adding circuit 30, and then sequentially supplied to the registers R10 to R4, and then to the adding circuit 2.
9 and is subjected to addition processing, and further registers R3 to R0
Are sequentially supplied to the adder circuit 28 and then to the adder circuit 28 again.

Then, this process is repeated for a fixed time, and the outputs of the registers R0 to R15 are supplied to the parallel-serial conversion circuit 31. The parallel data supplied to the parallel-serial conversion circuit 31 is converted into serial data, which is used as a CRC code. Generated CR
The C code is output through the output terminal 32 and added to the video data in the CRC adding circuit 16. This CR
The video data to which the C code is added is transmitted to the receiving side shown in FIG. 2 via the output terminal 17.

FIG. 4 shows the format on the transmitting side shown in FIG. 1. As shown in FIG. 4, the horizontal scanning line period Ht
In the figure, SAV is added to the head of the video data Vd, EAV is added to the end thereof, and a CRC code is further added. In the CRC code calculation process in the CRC addition circuit 16 shown in FIG. 3, first, at a time point a shown in FIG. 4, all the registers R0 to R15 are reset, and then the process described above is performed. The calculation of the CRC code for the horizontal scanning line period Ht is completed at the time point b.

Further, as shown in FIG. 4, if the time code Tc is added for each line, for example, it is added during the horizontal blanking period Hbt. Further, the audio data Ad may also be a vertical blanking period inserted in this period Hbt). Also, when the time code is inserted within the vertical blanking period, for example, 3 before the audio data.
One at a time, or one at the front and two at the back (or vice versa)
Just insert it.

The serial data having the structure shown in FIG. 4 is supplied to the receiving circuit 19 through the input terminal 18 on the receiving side shown in FIG.

Next, the receiving side will be described with reference to FIG. In FIG. 2, reference numeral 20 includes a circuit for performing various kinds of video processing in the video processing circuit, and internally has a CRC calculation circuit, an error correction circuit and a time code majority decision circuit which are similar to the circuit shown in FIG. In this video processing circuit 20, a CRC code is calculated from the video data from the reception circuit 19 by the internal CRC calculation circuit by the same processing as described in FIG. 3, and the CRC code obtained by the calculation and the reception circuit 1
By comparing with the CRC code from No. 9, it is detected whether or not the video data has a transmission error.

If there is a transmission error, the error correction circuit corrects the error line by line. If there is an error in the data of that line, for example, replace the data of the previous and next lines with the data of the new line obtained by averaging, or replace with the data of the previous line to prevent the error from being output. .

In addition, the majority of the transmitted time code is determined for each field, and the time code of the most received value is adopted as the correct time code. In the case of further transmitting from the receiving side, all erroneous time codes may be replaced with correct time codes. The transmission path actually used has a very low transmission error rate, and therefore the probability that the time code as auxiliary data transmitted a plurality of times will make an error more than once is very low. Therefore, by actually setting the number of times of transmitting the time code for each field to be three and adopting the data transmitted two or more times as correct data, it is possible to transmit the time code practically without a transmission error.

Although the time code is used in this example, various flags and parameters may be used as long as they are auxiliary data.

The video data processed in this way is supplied to the delay circuit 21 and the control circuit 24, respectively. Reference numeral 23 is a voice processing circuit, which has a CRC calculation circuit and an error correction circuit, which are similar to the circuit shown in FIG. In the voice processing circuit 23, a CRC code is calculated from the voice data from the receiving circuit 19 by the internal CRC calculating circuit by the same process as described in FIG. 3, and the CRC code obtained by the calculation and the receiving circuit 19 By comparing with the CRC code, it is detected whether or not the voice data has a transmission error. If there is a transmission error, the error correction circuit corrects the error line by line or field by field. If there is an error in the data of that line, for example, replace the data of the previous and next lines with the data of the new line obtained by averaging, or replace with the data of the previous line to prevent the error from being output. .

The audio data from the audio processing circuit 23 is supplied to the delay circuit 24 and the control circuit 25, respectively. The delay circuit 24 is, for example, a memory such as a FIFO (first in first out), and has a fixed delay amount. That is, the timing of reading with respect to writing is fixed.

The delay circuit 21 is, for example, a memory such as a FIFO and has a variable delay amount. That is, the timing of reading with respect to writing is variable.

The control circuit 25 determines the delay time of the delay circuit 21 based on the flags added to the video data from the video processing circuit 20 and the audio data from the audio processing circuit 23.
That is, the timing of reading with respect to writing is changed.

That is, the control circuit 25 stops the reading of the data written in the delay circuit 21 until the flag of the audio data is detected, and controls the delay circuit 21 to start the reading when the flag is detected. To do. As a result, the phases of the audio data output from the delay circuit 24 and the video data output from the delay circuit 21 can be matched. The video and audio data from the delay circuits 21 and 24 are respectively supplied to the transmission circuit 22 and then supplied to another device (not shown) or another circuit of a device having a circuit on the receiving side through the output terminal 26. To be done.

If the device connected to the output terminal 26 is a device capable of monitoring video and audio, or if the device connected to the output terminal 2
If 6 is a total of 3 terminals for video and 2 audio, or if it is a circuit for monitoring video and audio instead of the transmission circuit 22, the phases of the video and audio match. For example, when a video of a person talking and its audio are monitored, since the lip sync is matched, the video and the audio are matched, and very good viewing can be performed.

As described above, in this example, auxiliary data such as a time code is added to each line or each field at least three times or more, and a CRC code is added to each line. A flag is added to the voice data to be transmitted, the error is detected and corrected by the CRC code on the receiving side, and the correct time code is detected by majority decision of the time code. By using the variable delay time of the video data to match the phase of the audio data and the video data, the correct data can be transmitted by obtaining the correct time code and the transmission error can be corrected. In addition, the lip sync can be adjusted to achieve good video and audio transmission and reproduction. It can be.

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0047]

According to the present invention described above, the flag indicating the beginning of the field or the frame of the video signal from the video signal source is added to the audio signal from the audio signal source by the flag adding means, and this video and Since the audio signal is serialized by the serialization means, the delay amount is controlled by the control means based on the video signal and the flag in the serial signal, and the phase of the audio signal is matched with the phase of the video signal by the phase control means. , And the lip sync can be adjusted, which enables good transmission and reproduction of video and audio.

Further, according to the present invention described above, the video and audio signals from the video and audio signal generating source are serialized by the serializing means, and at least the error detection signal adding means is added to the video signal of the serial signals. A signal for error detection is added for each horizontal period, and the error detection means performs error detection of the video signal based on this error detection signal, so that the error can be corrected, and thereby good transmission of video and audio, Reproduction can be realized.

Further, according to the present invention described above, the video and audio signals from the video and audio signal source are serialized by the serializing means, and the time code generating means determines the reproduction position of the video signal from the video signal source. And time code 1
Since the data is output at least twice in the field, the data can be transmitted correctly and the receiving side can perform the accurate processing by using the correct time code.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a transmission side of an embodiment of a transmission device of the present invention.

FIG. 2 is a block diagram showing a receiving side of an embodiment of a transmission apparatus of the present invention.

FIG. 3 is a configuration diagram showing a part of an embodiment of a transmission device of the present invention.

FIG. 4 is an explanatory diagram showing an example of a transmission format used for explaining an embodiment of the transmission device of the present invention.

FIG. 5 is a configuration diagram showing an example of a conventional transmission device.

FIG. 6 is an explanatory diagram showing an example of a transmission format used for explaining an example of a conventional transmission device.

FIG. 7 is an explanatory diagram for explaining an example of a conventional transmission device.

[Explanation of symbols]

 10 time code generation circuit 11 video processing unit 12 serialization circuit 13 audio processing unit 14 packetization circuit 15 flag addition circuit 16 CRC addition circuit 19 reception circuit 20 video processing circuit 21, 24 delay circuit 22 transmission circuit 23 audio processing circuit 25 control circuit

Claims (3)

[Claims] 1. A video and audio signal generation source, and flag addition means for adding a flag indicating the beginning of a field or frame of the video signal from the video signal generation source to the audio signal from the audio signal generation source, Serializing means for serializing the video and audio signals from the video and audio signal source; control means for controlling the delay amount based on the video signal and the flag in the serial signal from the serializing means; Phase control means for adjusting the phase of the audio signal to the phase of the video signal based on the output of the means. 2. A video and audio signal generation source, a serialization means for serializing the video and audio signals from the video and audio signal generation source, and a video signal of the serial signals from the serialization means. Error detection signal adding means for adding an error detection signal at least every horizontal period, and the video signal of the serial data from the serializing means by the error detection signal added by the error detection signal adding means. And an error detecting means for detecting the error. 3. A video and audio signal generation source, serializing means for serializing the video and audio signals from the video and audio signal generation source, and a reproduction position of the video signal from the video signal generation source. A transmission device, comprising: a time code generation means for outputting a time code at least twice in one field.