JPH10285034A - Analog to digital converter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an analog to digital(A/D) converter circuit excellent in dynamic characteristic and capable of reducing conversion error due to synchronization deviation of a clock signal. SOLUTION: Jumpers 10-70 jumpering different clock signal lines around comparators adjacent to each other in the operation among clock signal lines LCK1-LCK8 driven by pluralities of clock drivers DRV1-DRV8 are provided. Thus, since the synchronization of clock signals fed to the comparators adjacent to each other in the operation is maintained, a linearity error in a dynamic characteristic of the A/D converter circuit is reduced to suppress a dynamic error at high speed conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog / digital conversion circuit, and more particularly to a flash type analog / digital conversion circuit.

[0002]

2. Description of the Related Art A flash type analog / digital conversion circuit compares an analog voltage inputted by a plurality of comparators with a reference voltage obtained from a voltage dividing resistor, and outputs an output signal of these comparators to a digital code by an encoder. Convert. Figure 2 shows an example of a flash type analog / digital converter for converting the analog signal V _in 4 digital signal bits D3, the D2, D1, D0. As shown, 16 resistance elements R16, R15, ..., R1, R0 are connected in series between the reference voltages _Vref1 and _Vref0 . The connection points of these resistance elements are connected to the inverting input terminals (-) of the fifteen comparators C15, C14,..., C1 and C0, respectively.
4, ..., the non-inverting input terminal of C1, C0 (+), the analog signal V _in is input. Comparators C15, C
,..., C1 and C0 output signals or inverted signals thereof are respectively connected to 15 AND gates A15, A14,.
.., A1 and A0. For example, the comparator C
15 is input to both input terminals of an AND gate A15, and its inverted signal is output to an AND gate A1.
4, and the output signal of the comparator C14 is input to the other input terminal of the AND gate A14.

[0003] AND gates A15, A14, ..., A1,
The output signal of A0 is input to the encoder ECD. The encoder ECD includes AND gates A15, A14,.
The 15 signals input from A1 and A0 are converted into 4-bit digital signals D3, D2, D1 and D0. The encoder ECD is configured by, for example, a ROM circuit formed on a substrate. The ECD part in FIG. 2 is a conceptual diagram showing the operation principle, and the double circle symbol in the figure indicates a logic element for calculating the logical sum of the signal. For example, as shown, the most significant bit (MSB) D3 of the digital signals D3, D2, D1 and D0 is connected to AND gates A15 to A8.
, And the least significant bit (LSB) D0 is obtained by AND gates A15, A13, A
It is obtained by the logical sum of eight output signals of 11, A9, A7, A5, A3 and A1. That is, the illustrated encoder E
The CD converts the output signals of the AND gates A15 to A1 into binary codes. Also, AND gate A15
A1 and the encoder ECD may be considered together as an encoder. The encoder in this case is a comparator C15
C1 has a function of converting the 15 output signals into binary codes.

In the above-mentioned flash type analog / digital conversion circuit, a reference voltage divided into 16 is generated by 16 resistor elements R16 to R1 connected in series.
15 to C1 are input to the inverting input terminals (-). The non-inverting input terminal of the comparator C15~C1 (+), the analog signal V _in is input, the comparator operates in response to a clock signal (not shown), for example, an analog signal V _in and the reference voltage at the rising edge of the clock signal And outputs a high-level or low-level signal to the output terminal according to the comparison result.

FIG. 3 shows an example of the conversion operation of the analog / digital conversion circuit. In FIG. 3, "H" indicates a state where the signal line is held at a high level, and "L" indicates a state where the signal line is held at a low level. In this example, for example, the analog signal V _in input is higher than the reference voltage V _r9 inputted to the inverting input terminal of the comparator C9, reference voltage V inputted to the inverting input terminal of the comparator C10
_Let it be lower than _r10 . In this case, the comparators C9-C
1 is at the high level "H", and the output signals of the comparators C15 to C10 are at the low level "L".
All signals other than the output signal of the AND gate A9 are held at the low level. The output signals D3, D2, D1 and D0 of the encoder ECD become "HLLH", which corresponds to, for example, "1001" of a binary code. Thus, the flash type analog / digital converter, a digital code corresponding to the level of the analog signal V _in input is obtained.

FIG. 4 schematically shows a layout diagram of an actual 8-bit flash type analog / digital conversion circuit. Since it is not realistic to arrange 255 comparators in series on an actual circuit configuration, 256 comparators are arranged in an eight-column arrangement with 32 comparators in each row. Hereinafter, a row composed of each comparator is referred to as a comparator bank (CMP BANK). A total of four 6-bit encoders are arranged between two comparator banks, and output data of these encoders is output to an 8-bit encoder ECDA. The reference resistor that generates the reference voltage is an aluminum wiring (hereinafter referred to as aluminum wiring) that is arranged in the series in a meandering manner as shown in the figure.
It consists of.

The operation timing of each comparator is controlled by a clock signal CLK. FIG. 5 shows the overall configuration of an analog / digital conversion circuit including a clock signal CLK supply circuit. As shown in the figure, the clock signal CLK is input to eight clock drivers DRV1 to DRV8 via the first-stage clock driver DRV0. Eight clock drivers DRV1
To DRV8 are output from eight clock signal lines LC, respectively.
K1 to LCK8. The eight clock signal lines LCK1 to LCK8 are wired to eight columns of comparator banks, respectively, and supply clock signals to each comparator. In order to synchronize the clock signals supplied to the respective comparators, the clock drivers DRV1 to DRV8 and the clock signal lines LCK1 to LCK8 are all arranged symmetrically.

[0008] Four 6-bit encoders ECD1 to ECD4 are arranged between two banks of comparator banks. A 6-bit digital code is generated according to the comparison result of each comparator. Encoder ECD
1 to ECD4 output code is 8-bit encoder ECD
A, which generates 8-bit digital codes D0, D1,..., D7, and outputs data to the output buffer BUF.
Is output via.

FIG. 6 is a circuit diagram showing an example of the comparator. As shown in the figure, the comparator includes three parts: an amplifier AMP, a comparator CMP, and a latch LAT. The amplifier AMP is an NPN transistor Q
1 and Q2, and a differential amplifier including NPN transistors Q5 and Q6 and resistance elements R3 and R4. The comparison unit CMP includes NPN transistors Q8, Q9, Q12 and resistance elements R6, R7.
And a differential amplifier consisting of Latch section L
AT is composed of NPN transistors Q10, Q11 and Q13. The signal latched by the latch unit LAT is N
It is output by an emitter follower composed of PN transistors Q15 and Q16.

In the comparator shown, NPN transistors Q3, Q4, Q7, Q14, Q17, Q18 and resistance elements R1, R2, R5, R8, R9, R10 form a current source circuit. The bases of these transistors are all connected to the input terminal of the bias voltage BAIS, and a current corresponding to the bias voltage BIAS input from the outside is supplied to the amplification unit AMP, the comparison unit CMP, and the latch unit LA.
Supply to T.

In the amplifier AMP, the transistor Q1
The base is connected to the input terminal of the analog signal V _in, the base of the transistor Q2 is connected to the input terminal of the reference voltage V _ref. The collector of the transistor Q1, Q2 is connected to the supply line of the power supply voltage V _CC, and the emitter is respectively connected to the collectors of the transistors Q3 and Q4.
The bases of transistors Q5 and Q6 forming a differential amplifier are connected to the emitters of emitter followers Q1 and Q2, respectively. It is connected to the supply line of the transistors Q5, respectively Q6 collector resistor element R3, via the R4 power supply voltage V _CC, an emitter connected in common to the collector of the transistor Q7. In the comparator CMP, the collectors of the transistors Q8 and Q9 are respectively connected to the resistor R
6, through R7 are connected to the supply line of the power supply voltage V _CC, an emitter connected in common to the collector of the transistor Q12. The base of the transistor Q12 is connected to the input terminal of the inverted signal CLKN of the clock signal CLK, and the emitter is connected to the collector of the transistor Q14 serving as a current source. In the latch section LAT, the collector of the transistor Q10 is connected to a connection node ND1 between the resistance element R6 and the collector of the transistor Q8, and the base is connected to a connection node ND2 between the resistance element R7 and the collector of the transistor Q9. Transistor Q11 has a collector connected to node ND2 and a base connected to node N2.
D1. The emitters of the transistors Q10 and Q11 are commonly connected to the collector of the transistor Q13, and the base of the transistor Q13 is connected to the clock signal CL.
K is connected to the input terminal, and the emitter is connected to the transistor Q1.
Transistor Q14 which forms a current source with the emitter of
Connected to the collector.

The comparator shown in FIG.
It operates according to LK and its inverted signal CLKN. Analog signal V _in and the reference voltage V _ref is respectively via an emitter follower Q1, Q2 transistors Q5, Q6
Is entered at the base of After being amplified by the differential amplifier including the transistors Q5 and Q6,
It is input to the bases of P transistors Q8 and Q9. The collector potentials of the transistors Q8 and Q9 are set according to the input signal, and are further latched by the latch unit LAT. The signal latched by the latch unit LAT is output via the emitter followers Q15 and Q16 to output voltage V
_out , and output as V _{/ out} .

FIG. 7 is a waveform chart showing the operation of the comparator. Hereinafter, the operation of the comparator will be described with reference to the circuit diagram of FIG. 6 and the waveform diagram of FIG. First, the clock signal CLK is at a low level and its inverted signal CLKN
Is high, the comparator is in comparison mode. In this case, transistor Q12 is on, and transistor Q13 is off. The current flowing through the collector of the transistor Q14 forming the current source
P. In this case the potential of the node ND1, ND2 is set in accordance with the potential difference between the analog signal V _in and the reference voltage V _ref input. For example, when the analog signal V _in is higher than the reference voltage V _ref, the node ND1 node ND
Is held higher than 2 levels, conversely, the analog signal V _in
Is lower than the reference voltage _Vref , the node ND1 is kept at a lower potential than the node ND2.

Next, when the clock signal CLK is at the high level and its inverted signal CLKN is at the low level, the comparator is in the latch mode. In this case, the transistor Q12
Are in a non-conductive state, and the transistor Q13 is in a conductive state.
Since all the current supplied by the transistor Q14 serving as a current source flows to the latch unit LAT, the comparison unit CMP does not operate, and only the latch unit LAT operates. Latch section LAT
Accordingly, for example, in the comparator CMP, even a slight potential difference between the node ND1 and the node ND2 is amplified and held as a high level “H” and a low level “L”. And
The levels of the nodes ND1 and ND2 are held as they are, and are maintained until the next comparison mode is entered. Latch section L
The signal held by the AT is the transistor Q1.
5, Q16, and output by an emitter follower. The output signal of the comparator is input to the encoder. The input signals from the plurality of comparators are converted into digital codes by the encoder.

[0015]

In the above-mentioned conventional flash type analog / digital conversion circuit, in order to supply a clock signal CLK to each comparator constituting a comparator bank at a uniform timing, FIG. Although clock drivers DRV1 to DRV8 are provided symmetrically as shown in the figure, the clock signal CLK is supplied through separate paths regardless of the function of the adjacent comparators depending on the arrangement position of each comparator. Slew rate (Slew rate)
If a high analog signal V _in of is input, since the subtle displacement of the operating time of the comparators occurs, there is the disadvantage that the output error between the comparator occurs. As a result, an erroneous digital code may be output from the encoder.

For example, as shown in FIG. 4, although the comparators C31 and C32 are adjacent to each other, their operation timings are controlled by clock signals from different clock drivers DRV1 and DRV2 due to the layout relationship. . Similarly, the operation timing is controlled by the clock signals from the clock drivers DRV2 and DRV3, respectively, while the comparators C63 and C64 are adjacent to each other. In addition, for example, the comparators C191 and C192, the comparator C223 and the comparator C224 also have a similar problem.

[0017] In the case of performing analog / digital conversion on a high slew rate analog signal V _in, which may be a very small shift of the operation timing of the comparator of next to each other resulting in large errors. Hereinafter, this will be described.
FIG. 8 is a diagram illustrating the concept of linearity of an analog / digital conversion circuit. Here, for example, an analog / digital conversion circuit that outputs a 3-bit digital code for an input signal is shown as an example.
ILE in the figure is the integral linearity error (Integral Linearity E
rror), DLE is differential linearity error (Differential Linea
rity Error). Further, the voltage V ₀ corresponding to 1 LSB is obtained by the following equation.

[0018]

V ₀ = V _PP / 2 ⁿ (1) where V _PP is the dynamic range of the analog / digital conversion circuit, and n is the number of bits of the digital code.

For example, when the dynamic range V _PP of the analog / digital conversion circuit is 2 V and the conversion code is 8 bits, the voltage V ₀ corresponding to 1 LSB is about 8 millivolts (mV).

[0020] As shown, when the DLE and ILE are both 0 LSB, but ideal conversion codes according to the input signal V _in is obtained, otherwise, converted as shown in FIG. 8 (b) There is an error in the code. In other words, the digital code obtained by the analog / digital conversion circuit, do not accurately reflect the voltage level of the input signal V _in.

FIG. 9 shows an example of the linearity of an 8-bit analog / digital conversion circuit. This is one of when the low frequency of the analog signal V _in, ILE
And DLE are both kept within the range of -0.5 LSB to 0.5 LSB. As described above, the clock signal C
When the LK is supplied to each comparator through a separate path, the synchronization of the clock signal CLK may be slightly shifted between adjacent comparators. Therefore, the slew rate of the voltage of the input signal V _in is high, for example,
If the frequency of the input signal V _in increases, Dari distorted more waveform from the static properties, or no far apart Sparkle (Sparkle) noise analog signal V _in may occur.

[0022] FIG. 10 is a waveform diagram showing an error of an analog / digital converter when the analog signal V _in the low speed and high speed has been input. Here, a sine wave waveform is used as an input signal, which is converted into a digital code by an analog / digital conversion circuit, and the obtained digital code is again converted into an analog signal by a digital / analog conversion circuit. The analog output signal obtained after conversion by comparing the original input signal V _in, can check the error of the analog / digital converter. Here, an ideal waveform is an input signal V _in before conversion, and an actual waveform is an output signal of a digital / analog conversion circuit. Here, it is assumed that a high-precision digital-to-analog conversion circuit is used, and errors caused by the conversion are only errors of the analog-to-digital conversion circuit.

[0023] FIG. 10 (a) is the input signal V _in is low frequency, for example, fin = 1 kHz, the frequency fclk of the clock signal CLK, the example, in the case of 100 MHz, shows the waveform of the input signal V _in and the output signal, respectively. As shown, when the input signal V _in is low-frequency, small error generated by the conversion, the output signal can be faithfully reproduced nearly original input signal V _in.

On the other hand, the frequency fcl of the clock signal CLK is
k is the same 100 MHz, the frequency fin of the input signal V _in is higher than the frequency of the clock signal CLK, for example, in the case of 100 MHz + 100kHz, FIG 10 (b)
As shown, in the portion having a high slew rate of the input signal V _in, sparkle noise is generated, also, the error is caused by the static characteristics of the analog / digital converter circuit at a low slew rate portion. Therefore, when the frequency of the input signal V _in high, an output signal of the digital / analog conversion circuit becomes different from the signal and the original input signal V _in.

The cause of the error in the linearity of the static characteristic of the flash type analog / digital conversion circuit is the reference voltage V
Reference voltage error due to variations in aluminum wiring width and thickness for generating _ref , wiring processing of bent aluminum wiring, variations in offset voltage of comparator input stage, and variations in bias voltage and offset voltage of comparator And so on. On the other hand, the causes of errors in the linearity of the dynamic characteristics of the analog / digital conversion circuit include nonlinearities in the input stage of the comparator, variations in the speed of the input stage of the comparator, variations in the signal delay and clock delay in the input stage, and clock jitter. Can be considered. Further, the above-described error in the static characteristic is added to the error in the dynamic characteristic.

FIG. 11 is a diagram for explaining variations in clock delay due to a high slew rate of an input signal. Here, since the input signal V (t) is a sine wave and the slew rate of the signal is a derivative with respect to time, the following equation is obtained.

[0027]

V (t) = Asin2πft dV (t) / dt = 2πfAcos2πft dV (t) / dt (max) = 2πfA (2)

That is, at the portion where the slew rate of the input signal V (t) is the highest, the time Δt for changing the signal level by 1 LSB is obtained by the following equation.

Δt = ΔV / 2πfA (3)

Here, ΔV is a signal V corresponding to 1 LSB.
_in , which is the same as V _{0 in} equation (1). For example, when the dynamic range V _PP of the input signal V _in is 2V, conversion code is 8 bits, [Delta] V is approximately 8mV. Further, when the 50MHz frequency fin of the input signal V _in, by the equation (3), a Delta] t = 25 picoseconds (psec).

That is, in the analog / digital conversion circuit, in order to suppress the conversion error due to clock synchronization deviation to within 1 LSB, in the above example, the synchronization deviation of the clock signal CLK supplied to each comparator is reduced by 25 ps.
ec. In each comparator, if the variation of the delay time of the clock signal CLK exceeds this, sparkle noise may occur.

[0031] In the example of FIG. 12, for example, the analog signal V _in input is higher than the reference voltage V _r9 inputted to the inverting input terminal of the comparator C9, reference voltage V is inputted to the inverting input terminal of the comparator C10 _r10 Let it be lower. In a normal state, the output signals of the comparators C15 to C10 should be at the low level "L" and the output signals of the comparators C9 to C1 should be at the high level "H" as in the operation example shown in FIG. . However, the output signal of the comparator C7 becomes high level “H” due to, for example, a deviation in synchronization of the clock signal. Thus, in addition to the AND gate A9, the output signal of the AND gate A7 is also held at the high level. As a result, the output signals D3, D2, D1, D0 of the encoder ECD become “HHH”.
H ”, which is, for example, the binary code“ 111 ”.
1 "and the digital code" 10
A digital code far from 01 "is output, and sparkle noise occurs.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an analog / digital conversion circuit which can reduce a conversion error due to a clock synchronization deviation and has good dynamic characteristics.

[0033]

To achieve the above object, the present invention comprises a plurality of comparing means for comparing the level of an input signal with a reference voltage obtained from a plurality of voltage dividing resistors connected in series; An analog / digital conversion circuit for generating a digital code according to a comparison result from the plurality of comparison means, wherein the plurality of comparison means are arranged in a matrix and each of the plurality of comparison means is arranged in the same column. A comparison operation is performed in response to a clock supplied via a common clock signal wiring, and a connection line is provided between the clock signal wirings in different columns in the vicinity of comparison means adjacent to each other in operation.

Further, in the present invention, there is provided clock supply means for supplying a clock signal to the clock signal wiring of each column, and the clock supply means is symmetrically arranged on a layout.

Further, in the present invention, the voltage dividing resistor is constituted by a wiring formed on the substrate between the first voltage and the second voltage, for example, a metal wiring.

According to the present invention, in the plurality of comparing means arranged in a matrix, a clock signal is supplied to the comparing means of each column (or each row) through a common signal line. The timing of the comparing operation of each comparing means is controlled in accordance with the supplied clock signal. A connection line is formed between signal lines for supplying a clock signal between columns (rows) in the vicinity of comparison means that are operatively adjacent to each other, and a clock signal line between different columns (rows) is short-circuited to form a clock signal. A conversion error due to a synchronization shift of the analog / digital conversion circuit can be reduced, and an analog / digital conversion circuit having good dynamic characteristics can be realized.

[0037]

FIG. 1 is a layout diagram showing an embodiment of an analog / digital conversion circuit according to the present invention. In this embodiment, the layout configuration of an 8-bit analog / digital conversion circuit is shown as an example. As shown, the clock signal CLK is a clock driver DRV
., DVR8, which are arranged symmetrically, via eight clock drivers DRV1, DRV2,..., DVR8. These clock drivers DRV1 to DRV1
V8, one clock signal line LCK
1, LCK2,..., LCK8 are driven.

In order to obtain an 8-bit digital code, it is necessary to arrange 255 voltage-dividing resistance elements having the same resistance value in series and further provide 255 comparators. On an actual semiconductor substrate, arranging all of these elements in series is impractical in view of the layout area and the like, and the actual layout is the pattern shown in FIG. As shown in the figure, the voltage-dividing resistance element is constituted by an aluminum wiring which is arranged in a series while winding. Reference voltages VRT and VRB are respectively applied to both ends of the aluminum wiring, and a voltage drop generated on the aluminum wiring is input to each comparator as a reference voltage of the comparator. A total of eight comparator banks consisting of 32 comparators are arranged between the aluminum wirings. Furthermore, between the two comparator banks, the 6-bit encoders ECD1 and ECD are respectively provided.
2, ECD3 and ECD4 are arranged.

The reference voltage V _ref generated on the aluminum wiring to each comparator, the analog signal V _in and the clock signal C
LK are input. All the comparison results of the comparator are input to the 6-bit encoders ECD1 to ECD4. These encoders first generate a 6-bit digital code. And each encoder EC
Conversion code of D1 to ECD4 is 8-bit encoder EC
DA, and an 8-bit digital code D0, D
1,..., D7 are generated. Conversion codes D0, D1,
, D7 are output to the outside via the output buffer BUF.

As described above, in order to suppress the dynamic characteristic linearity error of the analog / digital conversion circuit, it is necessary to suppress the synchronization deviation of the clock signal input to each comparator. However, in the layout structure shown in FIG. 1, while the comparators are next to each other,
There are comparators that receive a clock signal supplied through different supply paths. For example, the comparators C31 and C32 operate by receiving clock signals from the clock signal lines LCK1 and LCK2, respectively. Further, the comparator C63,
C64, comparators C223, C224, etc. have similar problems.

In this embodiment, in order to maintain the synchronization of the clock signal, as shown in FIG. 1, several places of the clock signal lines are connected by short-circuit lines 10, 20,.
The synchronization of clock signals supplied to adjacent comparators is maintained. For example, clock drivers DRV2 and DRV
Clock signal lines LCK2 and LCK near the output terminal
3, a short-circuit line 10 is provided, whereby the synchronization of clock signals supplied to the adjacent comparators C63 and C64 is maintained. Similarly, the clock signal line LCK
1 and the far end of LCK2, ie, comparators C31 and C3
Short circuit line 4 connecting these clock signal lines near 2
Wire 0. Thereby, the synchronization of the clock signals supplied to the adjacent comparators C31 and C32 is maintained.

As described above, by arranging a plurality of short-circuit lines between the clock signal lines, clock signals which are synchronized with each other are supplied to adjacent comparators in operation, and a dynamic characteristic linearity error of the analog / digital conversion circuit is obtained. Can be reduced.

It should be noted that the short-circuit lines 10,
By wiring 20,..., 70, the length and thickness of the clock signal line are equivalently increased, and the capacity of the signal line is increased. From the viewpoint of the clock driver, the load capacity of the driving target increases. However, since the clock signal lines connected by the plurality of clock drivers DRV1 to DRV8 are driven, the driving capability of the entire clock driver is large, and the occurrence of waveform distortion on the clock signal line can be avoided.

As described above, according to this embodiment,
For the clock signal lines LCK1 to LCK8 driven by the plurality of clock drivers DRV1 to DRV8,
By arranging short-circuit lines 10 to 70 connecting different clock signal lines near the place where the adjacent comparators are arranged in operation, the synchronization of the clock signals supplied to the adjacent comparators is maintained. The linearity error of the dynamic characteristic of the digital conversion circuit can be reduced, and the dynamic error in high-speed conversion can be suppressed.

[0045]

As described above, according to the analog / digital conversion circuit of the present invention, even when the slew rate of the analog signal is high, the synchronization of the clock signal supplied to the adjacent comparator is maintained, and the high speed conversion is achieved. Has a merit that a flash type analog / digital conversion circuit having good dynamic characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an analog / digital conversion circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating an example of an analog / digital conversion circuit.

FIG. 3 is an example showing an operation of the analog / digital conversion circuit.

FIG. 4 is a layout diagram of a comparator of the 8-bit analog / digital conversion circuit.

FIG. 5 is a layout diagram showing an entire configuration of an 8-bit analog / digital conversion circuit.

FIG. 6 is a circuit diagram illustrating an example of a comparator.

FIG. 7 is a waveform chart showing an operation of the comparator.

FIG. 8 is a conceptual diagram showing the linearity of an analog / digital conversion circuit.

FIG. 9 is a diagram illustrating an example of the linearity of an analog / digital conversion circuit.

FIG. 10 is a waveform chart showing a conversion error of the analog / digital conversion circuit.

FIG. 11 is a diagram showing variations in clock signal delay;

FIG. 12 is a diagram illustrating generation of sparkle noise due to variation in clock signal delay.

[Explanation of symbols]

10, 20, ..., 70 ... short-circuit line, DRV0, DRV1,
…, DRV8… Clock driver, LCK1, LCK
2,..., LCK8... Clock signal lines, ECD1, ECD
2, ECD3, ECD4 ... 6-bit encoder, ECD
A: 8-bit encoder, BUF: Output buffer, C
0, C1, C2,..., C255.
R2,..., R16... Voltage dividing resistors, A1, A2,.
... AND gate, V _CC ... the power supply voltage, V _SS ... common potential.

Claims (5)

[Claims] 1. A plurality of comparing means for comparing the level of an input signal with a reference voltage obtained from a plurality of voltage dividing resistors connected in series, and a digital code corresponding to a comparison result from the plurality of comparing means. Wherein the plurality of comparing means are arranged in a matrix and respond to a clock supplied via a common clock signal wiring to each of the comparing means arranged in the same column. An analog / digital conversion circuit having a connection line formed between said clock signal lines between different columns in the vicinity of comparison means adjacent to each other in operation. 2. The analog / digital conversion circuit according to claim 1, further comprising clock supply means for supplying a clock signal to said clock signal wiring of each column. 3. The analog / digital conversion circuit according to claim 1, wherein said clock supply means comprises a buffer symmetrically arranged on a layout. 4. The analog / digital conversion circuit according to claim 1, wherein said voltage dividing resistor is constituted by a wiring formed on a substrate between a first voltage and a second voltage. 5. The analog / digital conversion circuit according to claim 1, wherein said voltage dividing resistor is constituted by a metal wiring formed on a substrate between a first voltage and a second voltage.