JPH10284997A - Afc circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize reduction in a time for AFC operation in the AFC circuit for a receiver where an intermediate frequency signal is FM-detected and the oscillating frequency of a local oscillator is controlled depending on a detection voltage obtained by smoothing the detected intermediate frequency signal. SOLUTION: Lapse time change information f(x, y) of a frequency offset stored in an ROM 19 is called based on absolute time information such as year/month/day and time obtained from a calendar clock IC 22, and a frequency offset correction coefficient α(x, y) stored in an erasable memory 24 is used to calculate a reception frequency offset Δf=α(x, y)×f(x, y). A frequency division ratio P to correct a reception frequency is obtained by the reception frequency offset in the initial state of AFC operation to conduct AFC control. Furthermore, the correction coefficient α(x, y) is properly updated based on an actual value Δfr to avoid the effect of temperature fluctuation difference from each area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AFC circuit for various broadcast receiving devices such as a satellite broadcast receiver and a CATV (cable television) terminal device, and more particularly to an AFC circuit for acquiring a predetermined frequency in a short time. The present invention relates to an AFC circuit.

[0002]

2. Description of the Related Art For example, DBS (Direct Bro)
adcast Satellite) 1 like a service
In the case of a signal transmitted from a satellite in a 2 GHz band, a received transmission wave is transmitted through an LNB (Low Noi) at an antenna.
se Block) After being down-converted to a 1 GHz band by a down converter, it is brought into the house with a coaxial cable or the like,
Input to the receiving device.

In this type of receiving apparatus, AFC is used to cope with fluctuations in the receiving frequency supplied via the LNB.
(Automatic frequency control) circuit is provided.

For example, as a frequency control circuit,
There is a frequency control circuit described in Japanese Patent Application Laid-Open No. 4-29012. FIG. 2 is a block diagram showing a configuration of a receiving device having a conventional AFC circuit.

In this figure, 1 is an antenna, and L
The frequency is down-converted by NB2, and the received signal (frequency fin) is supplied to the tuner unit 3 of the receiving device. The tuner unit has a frequency mixer therein and mixes with the oscillation output (frequency fL) of the local oscillator 6 to output an intermediate frequency signal (frequency fIF = fin−fL). After the necessary band is selected by the band-pass filter 4, the intermediate frequency signal is subjected to FM detection by the next-stage FM detector 5, and its detection output is supplied to the subsequent-stage signal processing circuit 7.
The voltage is smoothed via the variable gain amplifier 26 and the low-pass filter 8 and is detected as a detection output voltage V by the voltage comparators 9H and 9H.
L. Further, the D / A converter 27 is connected to the CPU 1
8 through the I / O 23 for gain control data G
D is converted into an analog signal and supplied to the variable gain amplifier 26. At this time, the gain control data GD is set so that the gain of the variable gain amplifier 26 becomes small in the initial stage of the AFC operation so that the correction amount of the dividing ratio P can be increased.
At the end of the AFC operation, the gain of the variable gain amplifier 26 is set to increase so that the AFC error decreases.

The local oscillator 6 is constituted by a VCO (Voltage Controlled Oscillator), and the oscillation frequency fL of the local oscillator 6 is divided by the programmable divider 12 in the PLL tuning circuit 25 into I / P. The obtained signal of the frequency fA is supplied to one input terminal of the phase comparator 14. A signal having a frequency fB obtained by dividing the oscillation frequency of the reference crystal oscillator 11 into I / N by the frequency divider 13 is supplied to the other input terminal of the phase comparator 14.
Then, the phase comparator 14 compares the phases of the frequencies fA and fB, and outputs a voltage corresponding to the phase difference. After the high-frequency component is removed by the low-pass filter 15, the voltage corresponding to the phase difference is applied to the varicap 28 functioning as a tuning capacitor in the local oscillator 6, thereby controlling the oscillation frequency fL of the local oscillator 6. You.

The above-mentioned programmable divider 12, frequency divider 13, phase comparator 14, and low-pass filter 15 constitute a PLL tuning circuit 25. Also, the local oscillator 6 → programmable divider 12 → phase comparator 1
A PLL (phase-locked loop) 24 is constituted by a loop that makes a round with 4 → low-pass filter 15 → local oscillator 6.

Reference numeral 16 denotes a keyboard operated when selecting a reception channel or the like, and 17 denotes a CPU.
(Central processing unit) 18, ROM (read only memory) 19, RAM (random access memory) 20
And an I / O (input / output circuit) 23. Then, when the receiving channel is selected by the keyboard 16, the CPU 16 reads the frequency division ratio P required for this channel from the ROM 19, and sets the frequency division ratio P in the programmable divider 12 via the I / O 23. Then, the PLL 24 sets the output frequency fA of the programmable divider 12 and the frequency divider 1
3 so that the oscillation frequency fL of the local oscillator 6 is accurately locked to a value corresponding to the frequency division ratio P set in the programmable divider 12. By the function of this PLL24,
The fluctuation of the local oscillation frequency fL due to a change in the ambient temperature or the like is suppressed.

On the other hand, the voltage comparator 9H includes a detection output voltage V corresponding to the intermediate frequency fIF supplied through the low-pass filter 8 and a first AFC supplied from the reference power supply 10.
This is a comparison with the reference voltage VH. (Detection output voltage V)
> (Reference voltage VH), the output thereof becomes “L”.
The level changes from “H” level to “H” level. Further, the voltage comparator 9L is configured to divide the detection output voltage V and the voltage VH of the reference power supply 8 by resistors r1 and r2 to obtain a second AFC.
This is a comparison with the reference voltage VL, and (detection output voltage)>
At the point in time when (reference voltage VL) is reached, its output changes from "L" level to "H" level. In this case, the first A
The FC reference voltage VH and the second AFC reference voltage VL are
The intermediate frequency fIF is a predetermined value f higher than the normal intermediate frequency fs.
d, the outputs of the voltage comparators 9H, 9L both become "H" level. When the intermediate frequency fIF becomes lower than the normal intermediate frequency fs by a predetermined value fd 'or more, the voltage comparator 9H , 9L are set to the “L” level.

When a receiving channel is selected by the keyboard 16, the CPU 18 once sets the frequency dividing ratio P corresponding to this channel in the programmable divider 12, and then executes the AFC operation described below.

This AFC operation is performed by the voltage comparators 9H and 9L.
Of the intermediate frequency fIF, the intermediate frequency allowable error range A (= fd +
fd '), and a correction operation for increasing or decreasing the frequency division ratio P of the programmable divider 12 by a predetermined amount based on the determination result. And
The above-described determination operation and correction operation are repeatedly performed until the output of the voltage comparator 9H becomes “L” level and the output of the voltage comparator 9L becomes “H” level. The error is corrected within the error range A.

Thereafter, even when the reception frequency fin fluctuates and the intermediate frequency fIF deviates from the intermediate frequency allowable error range A, the CPU 18 executes the above-described AFC operation so that the intermediate frequency fIF is always set to the intermediate frequency allowable range. It is kept within the error range A.

[0013]

Since such downconverters are usually mounted on the antenna of the receiver, these downconverters are subject to extreme temperature fluctuations throughout the year as well as throughout the day, resulting in an operational accuracy. And the inherent accuracy of the downconverter itself. Therefore, the frequency-downconverted signal is supplied to the input terminal of the tuner unit at a conversion frequency having a frequency offset more than expected, and there is a problem that the time required for capturing the signal is deteriorated.

An object of the present invention is to provide an AFC circuit that can solve the above-mentioned problem.

[0015]

The AFC circuit of the present invention comprises:
PLL receiving a high frequency input signal and having a variable frequency function
Means for predicting a frequency offset of the received signal in an AFC circuit that converts the received signal to a predetermined frequency by a circuit and controls an output frequency of the PLL circuit based on a demodulated signal of the received signal, and an initial operation of the AFC Means for updating the frequency offset of the received signal every time.

The means for predicting the frequency offset includes:
The present invention is characterized in that a frequency offset at a current time is obtained from temporal change information based on past frequency offset data.

The current time is determined by a timer IC.
And the information stored in the ROM is used as the aging information.

Further, the means for updating the frequency offset includes a storage means for storing a correction coefficient for correcting an error between the aging information and an actual frequency offset amount, and a memory for storing the AFC according to the contents of the storage means. It is characterized by updating means for updating the correction coefficient for each initial operation.

An AFC circuit according to the present invention comprises a tuner unit having a local oscillator for tuning to a selected reception channel, a reference frequency generating means for generating a reference frequency of the tuner unit, and a predetermined frequency dividing output of the local oscillator. Variable frequency dividing means for setting a ratio, phase comparing means for supplying a control voltage corresponding to a phase difference between an output of the reference frequency generating means and an output of the variable frequency dividing means to the local oscillator, and an output of the tuner unit. Demodulating means, a variable gain amplifier for amplifying the output of the demodulating means to a predetermined output, a first voltage comparing means for comparing the output of the variable gain amplifier with a first reference voltage, Second voltage comparing means for comparing a second reference voltage obtained by dividing the first reference voltage with an output of the variable gain amplifier, and comparing the first and second voltage with each other. Control means for controlling the frequency division ratio of the variable frequency dividing means based on the comparison result of the stages, wherein the control means controls the frequency division ratio of the variable frequency dividing means; If the comparison results of the voltage comparison means are equal, the amplification degree of the variable gain amplifier is reduced, and the correction amount per one time of the frequency division ratio is increased, and the comparison between the first and second voltage comparison means is performed. If the result is different, the amplification degree is increased and the correction amount per one time of the frequency division ratio is reduced. Further, at the beginning of the AFC operation, the date and time information stored by the timer IC and the date stored in the ROM are read. Means for determining the frequency division ratio of the frequency dividing means based on the time-dependent change information of the frequency offset obtained based on the information of the time and the time, and correcting the error between the time-dependent change information and the actual frequency offset amount. Store correction coefficient Characterized by comprising the stage, and means for updating the correction coefficient for each initial operation of the AFC operation.

[0020]

Next, an embodiment of the present invention will be described in detail with reference to FIG. In this figure, FIG.
The difference is that the calendar clock IC22 and the EEPROM
21 is connected to the CPU 18.

Referring to FIG. 1, reference numeral 22 denotes a calendar IC for obtaining date and time information, and a correction coefficient of frequency offset information calculated on the basis of the date and time information is stored in an EEPROM (Electronic Memory). (Erasable programmable ROM) 21. Further, since it is sufficient that 21 is a rewritable memory, it can be replaced with, for example, a flash memory.

The CPU 18 stores the A
Based on the FC operation program, the gain of the variable gain amplifier 26 is controlled, and the same judgment operation as that of the related art is performed based on the output levels of the voltage comparators 9H and 9L. Is performed to increase or decrease the frequency dividing ratio P by a predetermined amount. In this case, at the beginning of the AFC operation, the variable gain amplifier 26
And the programmable divider 12
The amount of correction per one division ratio P is large. As a result, the detection voltage V is supplied from the variable gain amplifier 26 to the voltage comparators 9H and 9L via the low-pass filter 8, and a relatively wide intermediate frequency allowable range is set.

Here, in setting the initial value of the frequency division ratio P to be set, first, the date x and the time y are called from the calendar IC 22 and the time based on the past frequency offset data stored in the ROM 19 is stored. Change information f (x,
y). The temporal change information f (x, y) is, for example,
The frequency offset can be obtained by calculation based on past weather data, or can be obtained based on actual frequency offset measurement data. Next, the frequency offset correction coefficient α in the initial state stored in the EEPROM 21
(X, y) is called to derive the frequency offset Δf (= α (x, y) × f (x, y)) at the beginning of the AFC operation, correct the reception frequency to be set, and determine the frequency division ratio P. Set.

When the AFC pull-in operation is completed, the gain of the variable gain amplifier 26 is increased,
The amount of correction per division ratio P of the programmable divider 12 is reduced, and a relatively narrow intermediate frequency range is set. Then, once the AFC pull-in operation is completed, the actual frequency offset Δfr is obtained from the set frequency at that time, and the correction coefficient α (x, y) is updated so as to reduce the frequency error ΔF = Δf−Δfr. At this time, even if the value of the frequency error ΔF = Δf−Δfr is extremely large, the average is updated by time averaging so that the correction coefficient α (x, y) is not extremely changed.

In the above configuration, when the receiving channel is selected by the keyboard 16 for the first time after the power is turned on, the frequency dividing ratio P is set in the programmable divider 12 in consideration of the above Δf, and the AFC operation is started. Also,
When the receiving channel is changed by the keyboard 16, the above-mentioned Δfr is already known.
The AFC operation is started by setting the frequency division ratio P.

In the above-described embodiment, F
The case where the present invention is applied to an FM receiver having the M detector 5 has been described as an example.
An AM detector may be provided instead of the detector 5.

[0027]

As described above, according to the present invention, in the initial state of the AFC operation when the power of the receiving apparatus is turned on, the year trend of the frequency offset corresponding to the date and time information and the day trend information are obtained. By setting the reception frequency by estimating the value of the frequency offset using the frequency offset correction coefficient, the effect of shortening the time until the AFC pull-in operation is completed can be obtained.

When the setting of the reception frequency is changed, the time until the AFC operation is pulled in can be reduced by setting the reception frequency by correcting with the immediately preceding frequency offset value.

Although the year trend and the day trend of the frequency offset are stored as fixed data, the frequency offset correction coefficient is stored in a rewritable memory and appropriately updated. Even if the temperature fluctuations and the like are different, there is an effect that control can be performed so as to bridge the gap by repeating the operation.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a receiving device including an AFC according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a receiving device including a conventional AFC.

[Explanation of symbols]

Reference Signs List 1 antenna 2 LNB 3 tuner unit 4 band pass filter (BPF) 5 FM detector 6 local oscillator 7 post-stage signal processor 8 low pass filter (LPF) 9 voltage comparator (9H, 9L) 10 reference voltage generator 11 reference crystal oscillator DESCRIPTION OF SYMBOLS 12 Programmable divider (variable frequency dividing means) 13 Fixed frequency divider 14 Phase comparator 15 Low-pass filter (LPF) 16 Keyboard 17 Microcomputer (control means) 18 CPU (central processing unit) 19 ROM (read only memory) 20 RAM ( 21 Random Access Memory 21 EEPROM (Electrically Erasable Programmable ROM) 22 Calendar Clock IC 23 I / O 24 PLL (Phase Locked Loop) 25 PLL Tuning Circuit 26 Variable Gain Amplifier 27 D / A Converter 28 Oscillation Frequency Number tuning varicap r1, r2 resistance

Claims (7)

[Claims] An AFC circuit that receives a high-frequency input signal, converts the signal into a reception signal of a predetermined frequency by a PLL circuit having a variable frequency function, and controls an output frequency of the PLL circuit based on a demodulated signal of the reception signal. AF comprising: means for predicting a frequency offset of the received signal; and means for updating the frequency offset of the received signal for each initial operation of the AFC.
C circuit. 2. The AFC circuit according to claim 1, wherein said means for predicting the frequency offset obtains a frequency offset at a current time from aging information based on past frequency offset data. 3. The AFC circuit according to claim 2, wherein the current time uses a timer IC, and the aging information uses contents stored in a ROM. 4. A means for updating the frequency offset, a storage means for storing a correction coefficient for correcting an error between the time-dependent change information and an actual frequency offset amount, and the AFC of the AFC according to the contents of the storage means. 4. The AFC circuit according to claim 3, wherein said AFC circuit is configured to update the correction coefficient for each initial operation. 5. A tuner unit having a local oscillator for tuning to a selected reception channel; a reference frequency generating means for generating a reference frequency of the tuner unit; and a variable for setting an output of the local oscillator to a predetermined frequency division ratio. Frequency dividing means; phase comparing means for supplying a control voltage corresponding to a phase difference between an output of the reference frequency generating means and an output of the variable frequency dividing means to the local oscillator; and a demodulating means for demodulating an output of the tuner unit. A variable gain amplifier that amplifies the output of the demodulation unit to a predetermined output; a first voltage comparison unit that compares an output of the variable gain amplifier with a first reference voltage; Second voltage comparing means for comparing the divided second reference voltage with the output of the variable gain amplifier; and a comparison result of the first and second voltage comparing means. And Zui, a control means for controlling a division ratio of the variable frequency division means, the control means controls the frequency division ratio of said variable frequency division means,
When the comparison results of the first and second voltage comparison means are equal, the amplification of the variable gain amplifier is reduced and the correction amount per cycle of the frequency division ratio is increased, and the first and second voltage comparison means are adjusted. If the comparison results of the voltage comparison means are different,
In addition to increasing the amplification degree, the amount of correction per one time of the frequency division ratio is reduced.
C means for determining the frequency division ratio of the frequency dividing means based on the time and change information of the frequency offset obtained based on the date and time information by C and the date and time information stored in the ROM; An AFC circuit comprising: means for storing a correction coefficient for correcting an error between change information and an actual frequency offset amount; and means for updating the correction coefficient for each initial AFC operation. 6. The AFC circuit according to claim 4, wherein said storage means uses a rewritable memory. 7. The demodulation means comprises FM demodulation or AM demodulation.
6. The AFC circuit according to claim 5, wherein demodulation is performed.