JPH10284942A - Multiplier for high frequency circuit and frequency converter using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a harmonic spurious level characteristic from being deteriorated by improving a multiple efficiency of the high frequency circuit multiplier in the high frequency circuit multiplier and frequency converter using it which are used for a mobile communication equipment such as a portable telephone set, a cordless telephone set and a pager. SOLUTION: A multiple number of a high frequency circuit multiplier 99 is shared by a 1st transistor(TR) 41 and a 2nd TR 42, the 1st TR 41 and the 2nd TR are configured with one package of 6-terminal structure and at least two ground terminals or over are used among the 6 terminals, then the multiple efficiency of the high frequency circuit multiplier 99 is improved and deterioration in the harmonic spurious level characteristic is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplier for a high-frequency circuit used in mobile communication equipment such as a portable telephone, a cordless telephone and a pager, and a frequency converter using the same.

[0002]

2. Description of the Related Art Conventionally, this type of frequency multiplier for a high-frequency circuit has the configuration shown in FIG. 8, 10 is a transistor array, 11 is a first capacitor, 12 is a second capacitor, 13 is a third capacitor, and 21 is a first capacitor.
, 22 is a second resistor, 31 is a parallel resonator, 33 is a bandpass filter, 93 is a power supply terminal, 94 is an input terminal,
An output terminal 95 is composed of one transistor to obtain a desired multiplication, and the ground of the band-pass filter 33 is connected to the ground of another circuit part in the device.

[0003]

However, in the above-mentioned prior art configuration, when a multiplication device is constituted by one transistor in order to obtain a desired multiplication, a harmonic spurious level adjacent to a desired frequency increases. In order to reduce this, there is a problem that the characteristics of the band-pass filter must be improved. In this frequency multiplier for a high-frequency circuit, it is required to improve the multiplication efficiency and to reduce the harmonic spurious.

The present invention improves the multiplication efficiency of a high-frequency circuit multiplier by distributing the multiplier of the high-frequency circuit multiplier to two transistors and separating the ground of the band-pass filter from the ground of the multiplier. An object is to prevent deterioration of harmonic spurious level characteristics.

[0005]

According to the present invention, there is provided a frequency multiplier for a high-frequency circuit according to the present invention, wherein an emitter of a first transistor is grounded, and a base of the first transistor is connected via a first capacitor. Connected to the input terminal via a first resistor, and connected to the collector of the first transistor via a first resistor, and the collector of the first transistor connected to one end of a second resistor via a first parallel resonator. Connected to the base of a second transistor via a first band-pass filter, one end of the second resistor is grounded via a second capacitor, and the other end of the second resistor is connected to a power supply terminal. , And grounded via a third capacitor, the base of the second transistor is connected to one end of a fourth resistor via a third resistor, and the collector of the second transistor is connected. It was connected to the second parallel resonator of the fourth end of the resistor through the fourth end of the resistor of the fourth
And the other end of the fourth resistor is connected to a power supply, the collector of the second transistor is connected to the output terminal via a second band-pass filter, and the first transistor And the second transistor is constituted by one package having a six-terminal structure, and is divided into at least two or more ground terminals.

In the frequency converter according to the present invention, the output terminal of the frequency multiplier for a high frequency circuit is connected to a local input terminal of a mixer, and the RF input terminal of the mixer is connected to a signal input terminal. An IF output terminal of the mixer is connected to an input terminal of a filter, an output terminal of the filter is connected to an input terminal of a limiter amplifier, an output terminal of the limiter amplifier is connected to a signal output terminal, and an RSSI output of the limiter amplifier. Is connected to the RSSI output terminal,
The mixer and the limiter amplifier are constituted by one semiconductor device, and the multiplying device for a high-frequency circuit and the semiconductor device are constituted on one double-sided substrate. Thereby, the multiplication efficiency of the multiplication device for a high-frequency circuit is improved, and the harmonic spurious level can be reduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to a first aspect of the present invention, an emitter of a first transistor is grounded and the first transistor is grounded.
The base of the transistor is connected to the input terminal via a first capacitor, and the first transistor is connected via a first resistor.
And the collector of the first transistor is connected to one end of a second resistor via a first parallel resonator, and the base of a second transistor is connected via a first band-pass filter. Connected to the second
, One end of the resistor is grounded via a second capacitor, the other end of the second resistor is connected to a power supply terminal and grounded via a third capacitor, and the base of the second transistor is connected to a third capacitor. The collector of the second transistor is connected to one end of the fourth resistor via a second parallel resonator, and the collector of the fourth transistor is connected to one end of the fourth resistor via the fourth resistor.
One end of the resistor is grounded via a fourth capacitor, the other end of the fourth resistor is connected to a power supply, and the collector of the second transistor is connected to an output terminal via a second band-pass filter. The first transistor and the second transistor are formed in one package having a six-terminal structure;
Divided into at least two or more ground terminals,
This has the effect of improving the multiplication efficiency and reducing the harmonic spurious level.

According to a second aspect of the present invention, there is provided the frequency multiplier for a high-frequency circuit according to the first aspect, wherein the first band-pass filter and the second band-pass filter are each constituted by a single-pole capacitively-coupled band-pass filter. This has the effect of reducing the number of stages of the band-pass filter.

According to a third aspect of the present invention, there is provided a third band-pass filter comprising a resonance frequency of a first parallel resonator and a third band-pass filter.
2. The frequency multiplier according to claim 1, wherein the resonance frequency of the parallel resonator is the same, and the resonance frequency of the second parallel resonator is lower than the resonance frequency of the fourth parallel resonator constituting the second band-pass filter. This device has the effect of improving the frequency characteristics of the harmonic spurious level adjacent to the desired multiplied frequency.

According to a fourth aspect of the present invention, the third resistor and the fourth resistor are connected to each other.
2. The high frequency circuit multiplier according to claim 1, wherein components other than the above-mentioned resistors are mounted on one surface of the double-sided board, and the third resistor and the fourth resistor are printed resistors on the other side of the double-sided board. An output of the multiplier constituted by the first transistor and an input of the multiplier constituted by the second multiplier are prevented from intersecting on one surface of the double-sided substrate, and the multiplication efficiency of the multiplier is obtained. Has the effect of preventing a decrease in

According to a fifth aspect of the present invention, there is provided a high frequency circuit for a high frequency circuit according to the first aspect, wherein the multiplier of the multiplier constituted by the first transistor and the multiplier of the multiplier constituted by the second transistor are the same. This is a multiplier, and has the effect of reducing the harmonic spurious level.

According to a sixth aspect of the present invention, the output terminal of the high frequency circuit multiplier of the first aspect is connected to a local input terminal of a mixer, and the RF input terminal of the mixer is connected to a signal input terminal. Of the filter is connected to the input terminal of the filter, the output terminal of the filter is connected to the input terminal of the limiter amplifier, the output terminal of the limiter amplifier is connected to the signal output terminal,
The SI output is connected to an RSSI output terminal, and the mixer and the limiter amplifier are constituted by one semiconductor device, and the frequency conversion device is configured such that the high-frequency circuit multiplier and the semiconductor device are constituted on one double-sided substrate. And has the effect of reducing the mounting area to half or less.

According to a seventh aspect of the present invention, the signal output terminal and the R
7. The frequency converter according to claim 6, wherein the SSI output terminals are arranged so as to be adjacent to each other.
This has the effect of preventing the SI output from being coupled to another terminal and causing the limiter amplifier to oscillate.

According to an eighth aspect of the present invention, there is provided the frequency converter according to the sixth aspect, wherein any two terminals of the signal input terminal, the input terminal of the filter, and the output terminal of the filter are arranged so as not to be adjacent to each other. Has the effect of preventing deterioration of the filter characteristics.

According to a ninth aspect of the present invention, the signal input terminal, the input terminal of the filter, and the output terminal of the filter are arranged so as not to be adjacent to the signal output terminal, and are arranged so as not to be adjacent to the RSSI output terminal. And has an action of preventing the limiter amplifier from oscillating.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 is an electric circuit diagram showing a frequency multiplier for a high-frequency circuit according to a first embodiment of the present invention. The first capacitor 11 is connected between the input terminal 94 and the first transistor 41, and has a capacitance value so as to have a low impedance with respect to an input signal. The first resistor 21 is a bias resistor of the first transistor 41, and the second resistor 22 gives a voltage between the collector and the emitter of the first transistor 41 so as to operate at １ ／ or less of the power supply voltage. The first transistor 41 is turned on with the minimum current. In the present embodiment, the multiplication number of the multiplication circuit by the first transistor 41 is three. Note that the multiplication number may be an integer.

The second capacitor 12 is provided for grounding the first parallel resonator 31 at a high frequency. The first parallel resonator 31 is configured by connecting a coil and a capacitor in parallel, and has a resonance frequency equal to or close to the multiplication frequency. In the present embodiment, the resonance frequency is set to a value slightly higher than the multiplication frequency. With this setting, the influence of the capacitance between the collector and the emitter of the first transistor 41 is taken into account, and as a result, it is possible to resonate optimally at the actual multiplication frequency.

The third capacitor 13 is a bypass capacitor for the power supply terminal 93, removes a noise component input from the power supply terminal 93, and removes only a DC component from the second resistor 12
And the fourth resistor 24. The first band-pass filter 33 is provided to selectively pass the multiplied frequency multiplied by the first transistor 41 and to reduce other harmonic spurious components. It is connected between the bases of two transistors 42. The second transistor 42 has a first transistor
Is provided to further multiply the signal multiplied by the transistor 41 of FIG. In the present embodiment, the multiplication number of the multiplication circuit by the second transistor 42 is also set to three. In addition,
The multiplication number may be an integer. Therefore, the input terminal 9
The signal input from 4 is multiplied by 9 at the output terminal 95.

The third resistor 23 is connected to the second transistor 4
2 bias resistor, and the second resistor
When the voltage between the collector and the emitter of the transistor 42 is given to operate at 1/3 or less of the power supply voltage, the second transistor 42 is turned on with the minimum current. At this time, the collector of the first transistor 41
The relationship between the emitter-to-emitter voltage (V1) and the collector-to-emitter voltage (V2) of the second transistor 42 is V1 <V2
The voltage value is set so that With such a design, the signal multiplied by the first transistor 41 can be multiplied by the second transistor 42 more or less efficiently. Note that the third resistor 23 may be connected between the base and the collector of the second transistor 42.

The fourth capacitor 14 is provided for grounding the second parallel resonator 32 at a high frequency. The second parallel resonator 32 is configured by connecting a coil and a capacitor in parallel, and has a resonance frequency equal to or close to the multiplication frequency. In the present embodiment, the resonance frequency is set to a value slightly higher than the multiplication frequency. With this setting, the influence of the capacitance between the collector and the emitter of the second transistor 42 is taken into consideration, and as a result, it is possible to resonate optimally at the actual multiplied frequency.

The second band-pass filter 34 is provided for selectively passing the multiplied frequency multiplied by the second transistor 42 and reducing other harmonic spurious. Collector and output terminal 9
5 is connected.

As shown in FIG. 1, in the present embodiment, the transistor array 10 is used, and the transistor array 10 is configured in a single package with the first transistor 41 and the second transistor 42 being independent. Accordingly, the static characteristics of the first transistor 41 and the second transistor 42 can be made extremely close. This makes it possible to reduce the deviation of the high-frequency characteristics between the frequency multiplier composed of the first transistor 41 and the frequency multiplier composed of the second transistor 42. In this state, the high frequency circuit multiplier 99 is configured, and the ground terminal of the first band-pass filter 33 is divided from the other ground terminal 92 of the high frequency circuit multiplier 99.

As described above, the first band-pass filter 33
Is independent, the grounding of the first band-pass filter 33 can be performed at a high frequency even if the grounding terminal 91 of the high frequency circuit multiplier 99 deviates from the ideal high-frequency grounding state. Circuit multiplier 9
9. Extract only the desired multiplied signal multiplied by 9.
Unnecessary harmonic spurious can be reduced.

(Embodiment 2) FIG. 2 is an electric circuit diagram of a frequency multiplier for a high-frequency circuit according to a second embodiment of the present invention. Note that the same components as those of the first embodiment are denoted by the same reference numerals, and detailed description is omitted. FIG.
1 in that the first band-pass filter 3
The third and second band-pass filters 34 are constituted by capacitive coupling band-pass filters having a one-pole structure. That is, the first band-pass filter 33 and the second band-pass filter 34 are realized by a circuit configuration in which a parallel resonator formed by connecting a coil and a capacitor in parallel is connected between the midpoint of two capacitors connected in series and the ground. doing. The first band-pass filter 33 and the second band-pass filter 34 can be configured in any form. However, when the multiplication factor in one transistor circuit is four or more, the present embodiment By dividing the multiplying circuit as described above, the number of stages of the first band-pass filter 33 and the second band-pass filter 34 for extracting a desired multiplied signal can be reduced.
With a circuit configuration as shown in FIG.
Can be realized.

A second embodiment of the present invention will be described with reference to FIG. The resonance frequency of the first parallel resonator 31 connected to the collector of the first transistor 41 and the resonance frequency of the parallel resonator forming the first band-pass filter 33 are the same or a value close thereto. As a result, the load viewed from the collector of the first transistor 41 has a configuration similar to a band-pass filter having a two-pole structure in high frequency, and unnecessary harmonic spurious generated in the frequency multiplier can be further reduced. Becomes

In this state, the second parallel resonator 3 connected to the collector of the second transistor 42
2 resonance frequency (f1) and the second bandpass filter 34
The relationship of the resonance frequency (f2) of the parallel resonator constituting
1 <f2.

With such a relationship, the frequency characteristics of the harmonic spurious components adjacent to the desired multiplied output signal extracted from the output terminal 95 can be made uniform, and as a result, the harmonic spurious components can be reduced. Become.

(Embodiment 3) FIG. 3 is a top plan view of a frequency multiplier for a high-frequency circuit according to a third embodiment of the present invention, and FIG. 4 is a bottom plan view thereof. This is a diagram specifically realizing the circuit configuration shown in FIG. As shown in the figure, components other than the third resistor 23 and the fourth resistor 24 are arranged at intervals of 0.2 mm. The input terminal 94 and the output terminal 95 are arranged so as not to be arranged on the same end face, thereby preventing the efficiency of the high frequency circuit frequency multiplier 99 from decreasing. The monitor terminal 97 is provided to monitor the multiplied signal of the output terminal 95 so that it operates normally.
The first transistor 41 shown in FIG. 2 and the second transistor 42 shown in FIG. 2 are constituted by the transistor array 10 contained in a package having a six-terminal structure. The power supply terminal 93 is provided to supply power to the high frequency circuit frequency multiplier 99. The terminal 96 is provided for connecting the fourth resistor 24 to the power supply terminal 93 and one end of the second parallel resonator 32. This connection may be made using a through hole. In the present embodiment, as shown in FIG.
And the fourth resistor 24 are used. Third resistor 2
Third and fourth resistors 24 are resistors formed by a thick film printing method, and have a thickness of 100 μm or less.

With this configuration, the signal multiplied by the first transistor 41 in FIG.
8, the signal is input to the base of the second transistor 42 shown in FIG. 2 and can be arranged so as not to cross the input terminal 94 on the upper surface of the double-sided substrate. As a result, the multiplication device 99 for the high-frequency circuit is multiplied. Efficiency can be improved. In the present embodiment, the ground of the first band-pass filter 33 and the ground of the emitter of the first transistor 41 are grounded by the first ground terminal 91. However, the ground of the emitter of the first transistor 41 is grounded. Note that the second ground terminal 92 may be grounded.

In the present embodiment, the multiplication factor by the first transistor 41 and the multiplication factor by the second transistor 42 have the same value, but they may be particularly different. However, for the multiplication factor by the first transistor 41 and the multiplication factor by the second transistor 42, a square root value or an integer as close as possible is selected as a division method for obtaining a desired multiplication factor. . For example, when a total of 12 multiplication is desired, a combination of 2 multiplication, 6 multiplication, 3 multiplication and 4 multiplication occurs, but only the latter is used.

(Embodiment 4) FIG. 5 is an electric circuit diagram of a frequency converter using a high frequency circuit multiplier according to a fourth embodiment of the present invention. As shown in FIG. 5, the frequency multiplier 99 for a high-frequency circuit corresponds to a portion indicated by a dashed line, and it is clear that this is nothing but the circuit portion shown in FIG. The local input terminal of the mixer 61 is connected to the output terminal 95 of the frequency multiplier 99, and the RF input of the mixer 61 is set to the RF input terminal 85.
1 is connected to an input of an externally disposed filter 68 as an input terminal 81 of the filter, and an output of the externally disposed filter 68 is connected to a limiter amplifier 62.
Are connected to the output terminal 82.

The input terminal 94 is connected to the frequency multiplier 9 for the high frequency circuit.
Reference numeral 9 denotes a signal input terminal, and a power supply terminal 93 is provided for supplying power to the frequency multiplier 99 for a high-frequency circuit. The mixer 61 and the limiter amplifier 62 are composed of a semiconductor device 69. The semiconductor device 69 has a power save terminal 89 (hereinafter referred to as a PS terminal 89) for reducing the operating current.
Is provided. In order to monitor the electric field strength of the signal input from the RF input terminal 85 of the mixer 61,
An SI output terminal 86 is provided. Signal output terminal 87
Outputs a signal whose frequency has been converted by the frequency conversion device. The power supply terminal 88 is provided for supplying power to the semiconductor device 69. In this state, the semiconductor device 69 is flip-chip mounted on the upper surface of the double-sided substrate on which the components of the high frequency circuit multiplier 99 are mounted. At this time, on the double-sided board on which the semiconductor device 69 is mounted, only the conductor for connecting each terminal of the semiconductor device 69 to the double-sided board is not arranged. By doing this,
Oscillation of the limiter amplifier 62 can be prevented.

(Embodiment 5) FIG. 6 is a top plan view of a frequency converter using a frequency multiplier for a high-frequency circuit according to a fifth embodiment of the present invention, and FIG. 7 is a bottom plan view. . This is a diagram specifically realizing the circuit configuration shown in FIG. The same components as those of the third embodiment are denoted by the same reference numerals, and detailed description is omitted. As shown in FIG. 6, the signal output terminal 87 and the RSSI output terminal 86 are arranged so that the terminals are adjacent to each other in the frequency converter. In this case, they are arranged so as to straddle the corners of the rectangle, but they may be constituted by one side of the rectangle. In addition, the terminals on both sides of the signal output terminal 87 and the RSSI output terminal 86 are grounded or the power supply terminal 88, and both terminals of the signal output terminal 87 and the RSSI output terminal 86 are arranged to have low impedance. As a result, the signal output terminal 87 and the RSSI output terminal 86 can be prevented from being coupled to other terminals at high frequencies, and as a result, oscillation of the limiter amplifier 62 in FIG. 5 can be stopped, and stable frequency conversion can be performed. The device is realized. In FIG. 6, the limiter amplifier 62 of FIG. 5 does not appear in the figure because it is configured in the semiconductor device 69.

As shown in FIG. 7, the signal inputted from the signal input terminal 85 is applied to the R of the semiconductor device 69 on the lower surface of the double-sided board.
Patterning up to the F input terminal. As a result, mixing of unnecessary signals can be prevented. Note that PS in FIG.
Although the terminals 89 are also patterned on the lower surface of the double-sided substrate as shown in FIG. 7, they may be patterned on the upper surface of the double-sided substrate.

Further, the signal input terminal 85, the input terminal 81 of the filter 68 in FIG. 5, and the output terminal 82 of the filter 68 are not arranged adjacent to each other, but are arranged so that at least one terminal interval is maintained. doing. This allows
The characteristic deterioration of the filter 68 connected to the outside can be prevented.

Further, the signal output terminal 87 and the RSSI output terminal 86 are connected to the signal input terminal 85 and the input terminal 8 of the filter 68.
1 and the output terminal 82 of the filter 68 are not adjacent to any terminal. This also has the effect of stopping the oscillation of the limiter amplifier 62 and realizes a stable frequency converter.

[0037]

As described above, according to the present invention, the emitter of the first transistor is grounded, the base of the first transistor is connected to the input terminal via the first capacitor, and the first resistor is connected. And the collector of the first transistor is connected to one end of a second resistor via a first parallel resonator and via a first band-pass filter. Connected to the base of a second transistor, one end of the second resistor is grounded via a second capacitor, and the other end of the second resistor is connected to a power supply terminal and via a third capacitor. Ground, and connect the base of the second transistor to a third
And a collector of the second transistor is connected to one end of the fourth resistor via a second parallel resonator, and one end of the fourth resistor is connected to the other end of the fourth resistor. Is connected to the ground via a fourth capacitor, the other end of the fourth resistor is connected to a power supply, the collector of the second transistor is connected to the output terminal via a second band-pass filter,
The first transistor and the second transistor are 6
Since it is composed of a single package with a terminal structure and divided into at least two or more ground terminals, it is possible to improve the multiplication efficiency of the multiplication device for high-frequency circuits, and to solve the problem that the harmonic spurious characteristics deteriorate. This has the advantageous effect that it can be performed.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a frequency multiplier for a high-frequency circuit according to a first embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a frequency multiplier for a high-frequency circuit according to a second embodiment of the present invention;

FIG. 3 is a top plan view showing a frequency multiplier for a high-frequency circuit according to a third embodiment of the present invention;

FIG. 4 is a bottom layout view of the same.

FIG. 5 is an electric circuit diagram showing a frequency conversion device according to a fourth embodiment of the present invention.

FIG. 6 is a top plan view showing a frequency converter according to a fifth embodiment of the present invention.

FIG. 7 is a layout drawing of the lower surface.

FIG. 8 is an electric circuit diagram showing a conventional frequency multiplier for a high-frequency circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Transistor array 11 1st capacitor 12 2nd capacitor 13 3rd capacitor 14 4th capacitor 21 1st resistor 22 2nd resistor 23 3rd resistor 24 4th resistor 31 1st parallel resonator Reference Signs List 32 second parallel resonator 33 first band-pass filter 34 second band-pass filter 41 first transistor 42 second transistor 61 mixer 62 limiter amplifier 68 filter 69 semiconductor device 81 filter input terminal 82 filter output Terminal 85 Signal input terminal 86 RSSI output terminal 87 Signal output terminal 88 Power supply terminal 89 PS terminal 91 Ground terminal 92 Ground terminal 93 Power supply terminal 94 Input terminal 95 Output terminal 96 terminal 97 Monitor output terminal 99 Multiplier for high frequency circuit

Claims (9)

[Claims] 1. An emitter of a first transistor is grounded, a base of the first transistor is connected to an input terminal via a first capacitor, and a collector of the first transistor is connected via a first resistor. And a collector of the first transistor is connected to one end of a second resistor via a first parallel resonator and connected to a base of a second transistor via a first band-pass filter. One end of the second resistor is grounded via a second capacitor, the other end of the second resistor is connected to a power supply terminal and grounded via a third capacitor, and the base of the second transistor is Is connected to one end of a fourth resistor via a third resistor, and the collector of the second transistor is connected to one end of the fourth resistor via a second parallel resonator. One of the resistance The other end is grounded via a fourth capacitor, the other end of the fourth resistor is connected to a power supply, the collector of the second transistor is connected to an output terminal via a second band-pass filter, A frequency multiplier for a high-frequency circuit, wherein the first transistor and the second transistor are formed in one package having a six-terminal structure and are divided into at least two or more ground terminals. 2. The high-frequency circuit multiplier according to claim 1, wherein the first band-pass filter and the second band-pass filter are each constituted by a single-pole capacitively-coupled band-pass filter. 3. The resonance frequency of the first parallel resonator and the resonance frequency of the third parallel resonator constituting the first band-pass filter are the same, and the resonance frequency of the second parallel resonator is the second resonance frequency.
2. The frequency multiplier according to claim 1, wherein the frequency is lower than the resonance frequency of the fourth parallel resonator constituting the band-pass filter. 4. Components other than the third resistor and the fourth resistor are mounted on one surface of a double-sided board, and the third resistor and the fourth
2. The high frequency circuit multiplier according to claim 1, wherein said resistor is constituted by a printed resistor on the other surface of said double-sided substrate. 5. The high-frequency circuit multiplier according to claim 1, wherein the multiplier of the multiplier constituted by the first transistor and the multiplier of the multiplier constituted by the second transistor are the same. 6. An output terminal of the frequency multiplier according to claim 1, wherein the output terminal is connected to a local input terminal of a mixer, an RF input terminal of the mixer is connected to a signal input terminal, and an IF output terminal of the mixer is a filter. The output terminal of the filter is connected to the input terminal of the limiter amplifier, the output terminal of the limiter amplifier is connected to the signal output terminal, the RSSI output of the limiter amplifier is connected to the RSSI output terminal, The mixer and the limiter amplifier are 1
A frequency conversion device comprising two semiconductor devices, wherein the frequency multiplier for the high-frequency circuit and the semiconductor device are formed on one double-sided substrate. 7. The frequency conversion device according to claim 6, wherein the signal output terminal and the RSSI output terminal are arranged adjacent to each other. 8. The frequency conversion device according to claim 6, wherein any two terminals of the signal input terminal, the input terminal of the filter, and the output terminal of the filter are arranged so as not to be adjacent to each other. 9. The frequency converter according to claim 6, wherein the signal input terminal, the input terminal of the filter, and the output terminal of the filter are arranged so as not to be adjacent to the signal output terminal, and are also arranged so as not to be adjacent to the RSSI output terminal.