JPH10284687A - Semiconductor integrated circuit and cell layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology, which can lay out even a relatively large logic block without dividing the block. SOLUTION: When a first logic block A, a second logic block C which is arranged at the neighborhood of the first logic block, and a plurality of I/O cells 21-3 which can give and take the signals between the first logic block and the second logic block and the outside are aligned, the plurality of I/O cells above described are deviated into a direction intersecting the aligning direction of the above described plurality of I/O cells, in correspondence with the layout area of the above described first block and the above described second block. Thus, the relatively large logic block can be arranged without dividing the block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to a technique effective when applied to a semiconductor integrated circuit by a gate array system and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (LSI), for example, a gate array type LSI is a semiconductor chip (hereinafter simply referred to as "chip").
(Also called NAND) or Noah (NO)
Basic cells (basic cells) corresponding to logic gates such as R) are arranged in a grid pattern, and have a configuration called a master slice. The master slice method is a method in which basic cells are formed on a chip in advance, and only a wiring between the basic cells is added to form a desired LSI. The power supply and the ground wiring are determined in advance so that all the basic cells satisfy the electrical characteristics. As described above, the master slice method can form a large variety of LSIs simply by generating only a mask pattern relating to wiring, and thus is suitable for quickly and inexpensively manufacturing a small quantity and large variety of LSIs.

The layout of a gate array type LSI is as follows.
When a logic circuit diagram and a chip shape described using a logical function unit (block) prepared in a library are given, artwork data on arrangement and wiring of each block in the library is generated. ,
Various layout systems have been proposed so as to be able to do so in a short time without error.

[0004] As an example of a document describing a gate array type LSI, there is an "LSI Handbook (p. 204-)" issued by Ohm Co., Ltd. on November 30, 1984.

[0005]

SUMMARY OF THE INVENTION Gate Array LS
In the layout of I, a plurality of I / Os (input / output inputs / outputs) corresponding to external pins are provided in order to enable a signal to be exchanged between a predetermined logic block formed by a combination of basic cells and the outside. G) A cell is provided. The plurality of I / O cells are laid out only on the edge of the semiconductor chip so as to surround the plurality of logic blocks, or the plurality of I / O cell columns are laid out in a stripe pattern at predetermined intervals. Sometimes. The latter layout is particularly called an internal stripe I / O structure. The present inventor has studied the gate array having the internal stripe I / O structure. As a result, in spite of the fact that the block is functionally one logical block, the block may be divided and laid out in some cases.
In such a case, it has been found that the wiring in the block becomes undesirably long, causing an undesired signal delay.

That is, in the internal stripe I / O structure, the formation position of the I / O cell row laid out in a stripe pattern is fixed in relation to the external pins and the internal wiring of the chip. Can not move with. Therefore, when laying out a block having a relatively large layout area, if such a block does not fit between the I / O cell columns arranged in a stripe pattern, the I / O cell column is sandwiched. Then, the logical block is divided and the layout has to be laid out. Then, the wiring between the divided logic blocks must be routed so as to straddle the I / O cell column, so that the wiring in that case is inevitably long. When the wiring becomes long, the amount of signal delay there increases, which affects the timing of the logical operation.

An object of the present invention is to provide a technique for preventing an internal wiring of a semiconductor integrated circuit having a stripe I / O structure from becoming undesirably long.

Another object of the present invention is to provide a technique which can lay out a relatively large logical block without dividing it.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

A first block (A) having a predetermined logical function, and a second block (A) arranged adjacent to the first logical block.
When a logic block (C) and a plurality of I / O cells (21-3) that enable exchange of signals between the first logic block and the second logic block and the outside are arranged, The plurality of I / O cells are arranged in accordance with the layout area of the first block and the second block.
/ O cells are arranged so as to be shifted in a direction (arrow Y direction) intersecting with the arrangement direction of the / O cells.

According to the above-described means, since the I / O cells are shifted in accordance with the layout area of the block, a relatively large logic block can be arranged without being divided. Therefore, it is possible to prevent the wiring of the logic block from becoming undesirably long, and to reduce the signal delay in the logic block.

A plurality of logic blocks (A, B, C) having a predetermined logic function, and a plurality of external pins (I / O) enabling exchange of signals between the logic block and the outside.
And a plurality of I / O cells (21-3) arranged corresponding to the external pins, a metal wiring for coupling the I / O cells and the external pins is provided in the logic block. Even if the I / O cell is moved in a direction that allows the layout position of the I / O cell to move in relation to the layout area of the I / O cell, a movement allowance portion that can be coupled to the input / output terminal of the I / O cell is formed. The I / O cell and the external pin are connected via the extra travel portion.

According to the above-described means, even if the I / O cell is moved in a direction that allows the layout position of the I / O cell to be moved in relation to the layout area of the logic block, the I / O cell is not affected by the metal wiring. A movement allowance portion that can be coupled to the input / output terminal of the / O cell is formed.
The O cell and the external pin are connected. This avoids the split arrangement of the logical block and prevents the wiring of the logical block from becoming undesirably long.

A plurality of logic blocks having a predetermined logic function; an external pin enabling signals to be exchanged between the logic block and the outside; and a plurality of I / O cells arranged corresponding to the external pin In the layout method for a semiconductor integrated circuit, the layout position of the I / O cell is shifted in relation to the layout area of the logic block to a metal wiring for coupling the I / O cell to an external pin. Is formed in a direction in which the I / O cell can be coupled to the input / output terminal of the I / O cell, and the I / O cell of each I / O cell is formed along the movement margin in relation to the layout area of the logic block. This is for determining the layout position.

According to the above-described means, the layout position of each I / O cell is determined along the margin for movement,
Even a relatively large logical block can be laid out without being divided.

At the center of the I / O cell in the moving direction,
It is possible to lay out input / output terminals that can be coupled to metal wiring for coupling to external pins.

[0018]

FIG. 2 shows a semiconductor integrated circuit to which a cell layout method according to the present invention is applied.

Although not particularly limited, the semiconductor integrated circuit 2 shown in FIG. 2 is a gate array type LSI having a stripe I / O structure, and is formed of one semiconductor such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. Formed on the substrate.

The layout of the gate array type LSI is as follows.
When a logic circuit diagram and a chip shape described using a logical function unit (block) prepared in a library are given, artwork data on arrangement and wiring of each block in the library is generated. ,
A workstation is used so that it can be done in a short time without error.

As shown by 21-1 to 21-n, a plurality of I / O cells each having a plurality of I / O cells arranged therein.
It has a cell column, and general logic is arranged except for a region where the I / O cell column is formed. In addition, a plurality of external pins 22 are provided corresponding to the general logic arrangement area so as to enable signal exchange with the outside. The external output of the output signal from the logic block formed in the general logic formation region or the signal fetch from the outside to the logic block is performed via the corresponding I / O cell and external pin.

Here, the plurality of I / O cell columns 21-1
Each of the I / O cells is an array of I / O cells as shown in FIG. 3, for example, as shown in FIG. It can be arranged slightly shifted in the direction intersecting the direction. That is, when the arrangement direction of the I / O cells is set to the arrow X direction,
Individual I / O cells can be displaced in the direction of arrow Y, which is the direction intersecting with the I / O cells. Arrow Y like that
The reason why the individual I / O cells are shifted in the direction is as follows.

According to the prior art, the formation position of the I / O cell row laid out in a stripe pattern is fixed in relation to external pins and the internal wiring of the chip. Can not. Therefore, when laying out a block having a relatively large layout area, if such a block does not fit between the I / O cell columns arranged in a stripe pattern, the I / O cell column is sandwiched. Then, the logical block is divided and the layout must be laid out. For example, as shown in FIG. 4, a logic block having a relatively large layout area
Considering the case where A and logic blocks B and C having a smaller layout area are laid out, the logic blocks B and C are located in the general logic placement area shown in FIG. Although the logical block A can be accommodated but requires a relatively large layout area, it cannot be accommodated in the general logical arrangement area shown in FIG.
The logical block A is divided and laid out so as to sandwich 1-3. That is, a block indicated by 43 and 44
Is a logical block A which is originally a logical block A.
In spite of the number of logical blocks, the layout area of the logical block is too large compared to the general logical arrangement area, so that the layout has to be divided and laid out as indicated by 43 and 44.

In this case, the divided blocks 43 and 44
The wiring 41 between them must be routed so as to straddle the I / O cell column. In this case, the wiring is inevitably spanned by the I / O cell column as compared with the case where the logical block A is not divided. It will be long. Therefore, in exchanging signals between the blocks 43 and 44, undesired signal delay is inevitable, and high-speed operation of the circuit is hindered.

Therefore, if the logical block does not fit in the general logical allocation area, as shown in FIG.
By moving some cells of the I / O cell column 23-1 in the direction indicated by the arrow and increasing the general logical arrangement area by that amount, the divided layout of the logical block A can be avoided. That is, all the I / O cell columns 21
The layout of -1 to 21-n is designed so as to be movable in the direction (the direction of the arrow Y in FIG. 3) intersecting with the direction of arrangement of the I / O cells (the direction of the arrow X in FIG. 3). Considering the size of the logical block to be
/ O cells can be moved.

For example, as shown in FIG. 5, by moving a part of the I / O cell column 23-1 in the direction indicated by the arrow to enlarge the general logical arrangement area, the general logical arrangement area is enlarged. The logical block A can be sufficiently accommodated. Note that the logical block C has a size that can be accommodated in the general logical arrangement area, so that there is no need to move the I / O there.

According to such a layout, the wiring 51 between the blocks 43 and 44 can be shorter than that shown in FIG. If the wiring is short, the amount of signal delay there is small, so that high-speed transmission of logic signals is possible, and high-speed operation of the circuit is possible.

FIG. 6 shows the I / O cell rows 23-1 to 23-23.
A configuration example of one of a plurality of I / O cells forming −n is specifically shown.

As shown in FIG. 6, the I / O cell 40
Are the electrostatic protection element 61, the input / output terminal 62, the driver 6
3, including an input circuit 64 and an output circuit 65.

When the gate array type LSI is formed by MOS transistors, the electrostatic protection element 61 is provided to prevent the gate oxide film of the MOS transistor from being destroyed by static electricity. The input / output terminal 62 is a terminal coupled to an external pin via a signal wiring described later, and the driver 63 drives an external load via the input / output terminal 62. The input circuit 64 is provided to take in a signal input from the outside via the input / output terminal 62 into a logic block inside the LSI. Also,
The output circuit 65 is a circuit for externally outputting a signal transmitted from the logic block via the driver 63.

Next, the movement of the I / O cell will be specifically described.

FIG. 1 shows the I / O in the semiconductor integrated circuit 2.
The layout in the vicinity of the cell column is shown.

VDD is an external pin for power supply on the high potential side, VSS is an external pin for power supply on the low potential side, and I / O is an external pin for data input / output.

The external pin VDD and the external pin VSS are L
High potential side power supply wiring 2 for transmitting power to the inside of SI
0 and the low-potential-side power supply wiring 30.
The high potential side power supply wiring 20 and the low potential side power supply wiring 30
Are the uppermost metal wiring of the LSI.

A signal wiring 10 for transmitting signals exchanged between the inside and outside of the LSI is coupled to the external pin I / O. This signal wiring 10 is also the uppermost metal wiring of the LSI. The plurality of I / O cells 40 forming the I / O cell column 21-3 are connected to the signal wiring 10, the high-potential power supply wiring 20, or the low-potential power supply wiring 30 by contacts. One of the high-potential-side power supply wiring 20 and the low-potential-side power supply wiring 30 is directly supplied to the I / O cell 40 via the uppermost power supply wiring, while the other is further supplied to the second-layer metal wiring. Supplied using wiring (not shown).

The standard layout position of the I / O cell column 21-3 is a position where the position indicated by the line 13 and the center of the I / O cell (input / output terminal 62) coincide. Even if the individual I / O cells 40 are moved from the standard layout position in the arrow Y direction, if the movement is within a predetermined range, the I / O cells 40, the signal wiring 10, and the high potential side power supply The uppermost metal wiring is laid out so as to be capable of coupling with the wiring 20 or the low potential side power supply wiring 30 by contact. In other words, the movement range indicated by the arrow 12 indicates a range in which movement is possible in the layout of the I / O cell 40. If the movement range is within the movement range 12, the I / O cell 4
Even if 0 is displaced in the direction of arrow Y, the metal wiring is formed with a margin so that the input / output terminal 62 of the I / O cell 40 can be connected to the uppermost metal wiring by contact. In other words, when the layout position of the I / O cell 40 is fixed, it is sufficient if the end of the uppermost layer metal wiring exists near the line 13, and it is not necessary to form it longer. However, in this example, the I / O cell 40
Of the I / O cell 40 in order to allow the
In consideration of the coupling with the input / output terminal 62, the uppermost metal wiring is formed extending to a position beyond the line 13 with a margin. As described above, as long as the I / O cell 40 is moved within the movement range indicated by the arrow 12, the input / output terminal 62 of the I / O cell 40 can be connected to the uppermost metal wiring by contact. The uppermost metal wiring is formed with a margin, and such a margin is defined as a “coupling margin”.

According to the above-described example, the following effects can be obtained.

A part of the I / O cell column 23-1 is moved in the direction indicated by the arrow to enlarge the general logical arrangement area so that the logical block A can be sufficiently accommodated in the general logical arrangement area. Become. According to such a layout, the wiring 51 between the blocks 43 and 44 is shortened, and the amount of signal delay there is reduced, so that high-speed transmission of a logic signal becomes possible and high-speed operation of the circuit becomes possible.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited thereto, and various modifications can be made without departing from the gist of the invention. Needless to say.

In the above description, the case where the invention made by the present inventor is mainly applied to a gate array type LSI which is a utilization field as a background has been described.
The present invention is not limited to this, and can be applied to various semiconductor integrated circuits.

The present invention can be applied on condition that signals are exchanged with the outside via at least an I / O cell.

[0042]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by disposing the I / O cells staggered according to the layout area of the block, a relatively large logic block is arranged without being divided, whereby the wiring of the logic block becomes undesirably long. Is avoided.

Further, even if the I / O cell is moved in a direction that allows the layout position of the I / O cell to move in relation to the layout area of the logic block, the metal wiring is connected to the input / output terminal of the I / O cell. Since the I / O cell and the external pin are coupled via the movable margin portion that can be coupled, the divided arrangement of the logical block is avoided, and the wiring of the logical block becomes undesirably long. Is avoided.

Further, in the cell layout, the layout position of each I / O cell is determined along the margin of movement, so that even a relatively large logical block can be laid out without being divided. Will be able to

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a layout of a main part in a semiconductor integrated circuit according to the present invention.

FIG. 2 is an overall explanatory diagram of the semiconductor integrated circuit.

FIG. 3 is an explanatory diagram illustrating movement of I / O cells in the semiconductor integrated circuit.

FIG. 4 is an explanatory diagram of a layout when an I / O cell is not moved.

FIG. 5 is an explanatory diagram of a layout when the I / O cell is moved.

FIG. 6 is a block diagram illustrating a configuration example of the I / O cell.

[Explanation of symbols]

 2 Gate Array LSI 10 Uppermost layer signal line 20 Uppermost layer power supply line 21-1 to 21-n I / O cell column 22 External pin 30 Uppermost layer power supply line 40 I / O cell 61 Static protection element 62 Input / output terminal 63 Driver 64 Input circuit 65 Output circuit

Claims (4)

[Claims] A first block having a predetermined logic function; a second logic block disposed adjacent to the first logic block; and a signal between the first logic block and the second logic block and the outside. A plurality of I / O cells arranged in a plurality of I / O cells, wherein the plurality of I / O cells are arranged in accordance with a layout boundary between the first block and the second block. I / O
A semiconductor integrated circuit, which is arranged so as to be shifted in a direction intersecting a cell arrangement direction. 2. A plurality of logic blocks having a predetermined logic function; a plurality of external pins enabling signals to be exchanged between the logic block and the outside; and a plurality of external pins arranged corresponding to the external pins. In a semiconductor integrated circuit in which I / O cells are arranged, metal wiring for coupling the I / O cells and external pins is provided regardless of the layout position of each I / O cell. A semiconductor integrated circuit having a wiring margin portion connectable to the input / output terminals of the I / O cell and an I / O cell coupled to an external pin via the coupling margin portion. 3. A plurality of logic blocks having a predetermined logic function, an external pin enabling exchange of a signal between the logic block and the outside, and a plurality of I / Os arranged corresponding to the external pin. In a cell layout method for a semiconductor integrated circuit in which O cells are arranged, a metal wiring for coupling the I / O cells and external pins is provided with I / O cells irrespective of the layout position of each I / O cell. A wiring margin that can be coupled to the input / output terminal of the O cell is formed, and the layout position of each I / O cell is determined along the wiring margin in relation to the layout area of the logic block. Cell layout method. 4. The cell layout method according to claim 3, wherein an input / output terminal that can be coupled to a metal wiring for coupling to an external pin is laid out at a central portion of the I / O cell in the moving direction.