JPH10283800A - Memory multiple-selection test circuit of semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a faulty part and to perform, for example a fault screening test and a life acceleration test in a short time by multiplexing a selection circuit being connected to a vertical wiring and a selection circuit being connected to a horizontal wiring and applying a voltage and data simultaneously. SOLUTION: When test mode selection signals C1, C2, and C3 have been set to H level, the output of a test circuit is entirely set to H level and word lines WL1-WL8 are selected. When a bit line selection circuit BSEL is entirely set to H level in this state, bit lines BL1-BL8 are selected and data can be written to all memory cells MS. By setting writing data dataA and dataB to 1 or 0, all memory dells MS can be set to either 0 or 1, thus performing a life acceleration test quickly without depending on the size of a memory space.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a dynamic RA.
M (random access memory), static RAM,
The present invention relates to a test method for a flash memory or the like, and relates to a technique effective for use in a memory having a large capacity of about 16 M bits or more.

[0002]

2. Description of the Related Art Conventionally, with the advance of semiconductor technology, 16
A dynamic RAM (DRAM) having a large storage capacity such as M, 64M, 256M bits has been developed.
As the storage capacity of the DRAM increases, the test time increases.

[0003] It is because access to a memory cell is performed in the same manner as in an actual use state, and selection of a memory cell is one-to-one with respect to selection of one address. It is necessary to select an address, and the test time increases in proportion to the increase in memory capacity. FIG.
Shows an example of the prior art. BL1, BL2, WL
In FIG. 5, in which X1 and WL2 are turned on / off one by one, for example, when X0 = H and Y0 = H are input, BL
The lines 1 and WL7 are selected, and the MS (memory cell) between them is selected. At this time, other cells are not selected.

[0004]

Conventionally, in order to detect interference between memory cells and a memory cell leak failure, a selection circuit for BL (bit line) and WL (word line) is switched every one or two addresses to detect a failure location. Is detected.

Therefore, in proportion to the increase of the memory space,
There is a problem that the test time increases. Therefore, according to the present invention, the test mode is operated, and simultaneously, BL, WL
It is an object of the present invention to provide a circuit and a method capable of detecting a defective portion in a short time by selecting a method, and performing a defect selection test, a life acceleration test, and the like in a short time.

[0006]

The present invention uses the following means in order to solve the above problems.

In a semiconductor memory device, the mode of a decoder (selection circuit) is switched between WL and BL to be selected according to an address (specifying a specific storage location), and at the same time, for example, the whole or one quarter or one half thereof To be able to select many.

For this purpose, in a semiconductor memory device, a selection circuit connected to a vertical wiring (WL: word line) and a selection circuit connected to a horizontal wiring (BL: bit line) are multiple-selected, and a voltage or data is simultaneously selected. Apply.

[0009]

By using the above means, the whole memory cell can be selected at once or a plurality of memory cells at the same time.
It can be implemented in a short time. For example, if an odd-numbered selection circuit and an even-numbered selection circuit are separated, and stress is applied to each of them, the voltage can be applied to all lines or cells in two cycles. In addition, defects in all memories can be found in a small number of cycles.

[0010]

FIG. 1 is a block diagram showing an embodiment according to the present invention. FIG. 2 to FIG. 3 show an operation explanation example of FIG.

In FIGS. 1 and 2, BSEL and WS
By turning on / off multiple EL circuits simultaneously, B
, BLn and WL1, WL2,
.., A large number of WLn are simultaneously turned on / off. The portion forming the memory device is composed of a vertical selection wiring WL (word line) and a BSEL (selection circuit) connected thereto, and a horizontal direction is provided with a BL (bit line) wiring and a data reading circuit SA (sense amplifier) connected thereto. And a SW (selection circuit) and a data writing circuit connected thereto.

[0012] Between WL and BL, M for storing data
S (memory cell) is formed, and by the selection circuit,
When one WL and BL are selected, data can be written and read to and from the memory cells between them.

According to the present invention, in order to operate the test circuits shown in FIGS. 1 and 2, C1, C2 and C3 are set to H level (V
In this case, all the WSEL lines are at the H level, and the vertical lines WL1 to WL8 are selected.

Next, the same test circuit is operated, and the BSE
When all the L lines are set to the H level, the horizontal lines BL1 to BL8 are selected, and data can be written to all the memory cells at the intersection of the WL and the BL line. For data writing, by setting the write data of dataA and dataB to 1 or 0, it is possible to set all memory cells to 0 or 1 or alternately to 1010 or the like.

When the test circuit is continuously operated as shown in FIG. 3 (C1 = H, C2 = L, C3 = H) and WSEL is selected by the signal of X1, it becomes possible to write data of the contents shown in FIG. Become.

This shows an example of using a test circuit, and FIG.
In addition to the contents shown in the above, a method for finding a leak failure between memory cells will be described. Repeatedly, when the input signal of X1 is at the H level, WL1, WL2, WL5, and WL6 are selected. When the input signal of Y0 is applied with the input signal of H / Y0, L1, BL2, BL5, and BL6 are selected. Is done. Therefore, the data set in the memory cell where the line intersects can be written.
Writing is performed on all memory cells by the combination of levels.

As an example of a test method, different data (1/0) is written to adjacent memory cells, and a defect in which data disappears due to interference such as leakage can be efficiently detected. As shown in FIG. 4, when a life test is performed using the test mode, voltage stress can be applied to the entire memory cell and between each line by repeating the mode. Although the test is performed while repeatedly switching the space for each address (selection wiring), the present invention can be performed in two to four cycles without depending on the size of the memory space. Can be done with

[0018]

As described above, according to the present invention, a defect of a memory device can be detected in a short time.

Further, even in the life accelerating test, since the initial failure can be found in a short time, the same effect can be obtained regardless of the size of the memory space capacity.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is an operation explanatory block diagram of FIG. 1;

FIG. 3 is an operation explanatory block diagram of FIG. 1;

FIG. 4 is a block diagram for explaining the operation of FIG. 1;

FIG. 5 is a diagram showing a conventional method.

[Explanation of symbols]

 WL word line BL bit line SA sense amplifier BSEL bit line selection circuit WSEL word line selection circuit dataA, dataB write data MS memory cell X0, X1, X2 address selection signal Y0, / Y0, Y1, / Y1 address selection signal C1, C2 , C3 test mode switching signal H high level signal L low level signal

Claims (1)

[Claims] 1. A semiconductor memory device, comprising: a control circuit for selecting a memory cell; and a sub-line for simultaneously selecting a word line and a bit line of a selected line, and applying a voltage. Memory multiple selection test circuit.