JPH10283794A - Sample and hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To switch sample/hold without using an analog switch and to retain output without being affected by the change in an input signal on holding securely by cutting off the output stage of an operational amplifier by a holding command and by fixing the potential of a capacitor for compensating phase being provided in the operational amplifier. SOLUTION: An operational amplifier OP 3 outputs a signal Vo with the same voltage as an input voltage to a holding capacitor when the switching signal S/H of sample/hold is a high-level sampling. In the case of a holding where the switching signal S/H is at a log level, transistors Tr71 and 72 of a push/pull output circuit 70 are cut off, an output is open-circuited, and the impedance of the side of a differential amplifier 50 of a capacitor C61 for compensating phase is increased by a transistor Tr3, thus preventing the output signal Vo from being changed even if an input voltage is rapidly changed on holding and surely retaining the potential of the holding capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit provided with an operational amplifier (operational amplifier) in an input stage.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 8, for example, an operational amplifier OP10, an analog switch SW1 connected to an output terminal of the operational amplifier OP10, and one end connected to an output terminal of the operational amplifier OP10 via the analog switch SW1. Is connected to the inverting input terminal (-) of the operational amplifier OP10, and the other end is grounded.
And a buffer circuit including an operational amplifier OP11 for outputting the voltage of the hold capacitor C10 to the outside.

In this type of sample and hold circuit, when the analog switch SW1 is turned on, the operation of the operational amplifier OP10 causes the hold capacitor C10 to input the input signal to the non-inverting input terminal (+) of the operational amplifier OP10. When the analog switch SW1 is turned off and charged to the same voltage level as Vin, the operational amplifier OP
The charging of the hold capacitor C10 by 10 is stopped, and the voltage of the hold capacitor C10 is held.

Therefore, the output signal Vout from the operational amplifier OP11 constituting the buffer circuit has the same voltage as the input signal Vin when the analog switch SW1 is on, and when the analog switch SW1 is turned off, the output signal Vout of the analog switch SW1 is turned off. It is kept at the voltage level at the time of ON.

[0005]

In the above-mentioned conventional sample-hold circuit, the sample and hold of the input signal Vin are switched using an analog switch SW1 connected to the output terminal of an operational amplifier OP10. Therefore, in order to incorporate the sample-and-hold circuit into a one-chip IC, it is necessary to use a BiCMO
There is a problem that the S step is required, which leads to an increase in the cost of the IC. That is, in the conventional sample and hold circuit, the operational amplifiers OP10 and OP11 can be easily configured by using bipolar transistors. However, since the analog switch SW1 is usually configured by a MOS-type FET, these circuits are integrated in an IC. In this case, a BiCMOS process is required for its manufacture, which leads to an increase in the cost of the IC.

On the other hand, in order to solve such a problem, the inventor of the present application has proposed, at the time of hold, an output NP in a push-pull output circuit constituting an output stage of an operational amplifier OP10.
By cutting off the N-transistor and the PNP transistor, switching between sampling and holding of the input signal Vin within the operational amplifier OP10 without using the analog switch SW1 was considered.

As a method of cutting off the output transistors (NPN transistor and PNP transistor) of the push-pull output circuit to open the output, for example, a method disclosed in Japanese Patent Publication No. 7-52816 is described. As described above, the base of each transistor is connected to the collector of the other transistor via a resistor, and the operation of the constant current circuit that supplies a bias current to each transistor is stopped, thereby turning off each transistor. In addition, there is known a method in which the base of each transistor is set to a low potential side and a high potential side potential of a DC power supply to which the other collector is connected to maintain an off state.

In this way, the sample-and-hold circuit can be realized without using the analog switch SW1 as in the prior art, so that the sample-and-hold circuit can be easily made into an IC. However, when the output transistor in the operational amplifier OP10 is cut off as described above, there is no problem when the change of the input signal Vin at the time of holding is slow. This causes a problem that the phase compensation capacitor causes AC coupling, the signal is transmitted to the push-pull output circuit, and the voltage of the hold capacitor C10 fluctuates.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem. In a sample / hold circuit having an operational amplifier in an input stage and configured to charge a hold capacitor by the operation of the operational amplifier, the sample / hold switching is performed. It is an object of the present invention to perform the operation without using an analog switch and to reliably hold an output without being affected by a change in an input signal during a hold.

[0010]

According to the first aspect of the present invention, there is provided a holding capacitor having one end grounded to a reference potential, and a holding capacitor having an output terminal and an inverting input terminal. Is connected to the other end of
An operational amplifier that charges the hold capacitor to the voltage corresponding to the input signal to the non-inverting input terminal, a buffer circuit that outputs the charge voltage of the hold capacitor, and an external open circuit that opens the output of the operational amplifier when it receives a hold command from outside A sample and hold circuit comprising an output open circuit for fixing an output from the buffer circuit,
Cut-off means for cutting off the output NPN transistor and PNP transistor in the push-pull output circuit constituting the output stage of the operational amplifier by the hold command in accordance with the hold command, and the phase provided in the operational amplifier in accordance with the hold command. And a potential fixing means for fixing the potential of the compensation capacitor.

In the sample and hold circuit according to the present invention, when a hold command is input from the outside, the cutoff means causes each of the output transistors in the push-pull output circuit forming the output stage of the operational amplifier to operate. Is cut off, and the potential fixing means fixes the potential of the phase compensation capacitor.

For this reason, even if the input signal input to the non-inverting input terminal of the operational amplifier changes sharply during the hold, the signal is transmitted to each output transistor by the AC coupling of the phase compensation capacitor. This is not the case, and the output of the operational amplifier is always kept open.

Therefore, according to the present invention, as in the prior art,
It is not necessary to provide an analog switch for opening the output of the operational amplifier between the operational amplifier and the hold capacitor, and the voltage of the hold capacitor can be reliably prevented from fluctuating during the hold. Therefore, according to the present invention, a sample-and-hold circuit that can obtain stable hold characteristics can be configured without using a MOS-type FET, and it is possible to easily implement an IC.

In this case, the potential fixing means may be as follows.
The input section of the input signal to the operational amplifier may be fixed at a predetermined potential as described in the item (1), and the differential amplifier and the phase compensation forming the input stage of the operational amplifier as described in the item (3). The connection with the capacitor may be directly fixed at a predetermined potential, or the constant current provided in the differential amplifier constituting the input stage of the operational amplifier as described in claim 4. The source may be configured to stop operation.

In particular, it is more preferable that the potential of the phase compensating capacitor fluctuates after the hold command is released, as described in claim 2 or claim 4. That is, as described in claim 3,
If the differential amplifier side of the phase compensation capacitor is directly fixed at a predetermined potential, after the hold command is released, the potential of the phase compensation capacitor on the differential amplifier side suddenly changes to a potential corresponding to the input signal. A spike noise may be generated on the output side of the phase compensation capacitor (that is, the base of the transistor in the push-pull output circuit), and the spike noise may be output to the outside. However, if the potential fixing means is configured as described in claim 2 or claim 4, the differential amplifier side of the phase compensation capacitor can be in a so-called floating state.
After the hold command is released, the potential on the differential amplifier side of the phase compensation capacitor does not suddenly change, and the occurrence of the spike noise as described above can be prevented.

Further, the cutoff means only needs to be able to cut off each transistor of the push-pull output circuit when a hold command is input, and the method thereof is conventionally known, such as the method disclosed in the above-mentioned publication. Although various methods can be adopted, in particular, as described in claim 5, the base and the emitter of each output transistor constituting the push-pull output circuit are connected by a resistor. Is preferred.

That is, if the base and emitter of each output transistor are connected by a resistor as described above,
When each transistor is in the off state, the potential between the base and the emitter is set to the same potential, thereby preventing each transistor from being broken down by the input voltage from the holding capacitor connected to the output terminal of the operational amplifier. Therefore, even when the voltage of the hold capacitor connected to the output terminal (that is, the hold voltage) increases, each transistor can be reliably held in the off state during the hold.

[0018]

Embodiments of the present invention will be described below. First, FIG. 1 is a configuration diagram illustrating a configuration of an entire air-fuel ratio detection device according to an embodiment including a sample and hold circuit to which the present invention is applied.

The air-fuel ratio detecting device of this embodiment is for detecting an air-fuel ratio (A / F) of a fuel mixture supplied to an internal combustion engine from an oxygen concentration in exhaust gas of the internal combustion engine. A / F sensor 2 provided in an exhaust pipe of the A / F sensor 2, a constant voltage output circuit 4 for applying a constant voltage AFC (for example, 3 V) to one end of the A / F sensor 2, and an A / F sensor at the other end of the A / F sensor 2. A drive voltage output circuit 6 for applying a drive voltage AFV for detection and internal resistance detection.

Here, the A / F sensor 2 is formed by forming a solid electrolyte such as zirconia into a cylindrical shape having one end closed, and forming a porous electrode on the inner and outer surfaces of the solid electrolyte. The sensor body is placed in a diffusion chamber where the inflow of exhaust gas is restricted, and the outer electrode is exposed to the exhaust gas in the diffusion chamber, and is incorporated in a predetermined housing so that air is introduced into the inner electrode. belongs to.

In the A / F sensor 2, if a voltage is applied between the electrodes so that the voltage of the inner electrode is higher than that of the outer electrode, oxygen in the diffusion chamber is pumped into the atmosphere. The movement of oxygen in the solid electrolyte causes a current to flow from the inner electrode to the outer electrode. And this current is
As shown in the figure, there is a region that does not change with the change of the applied voltage between the electrodes, and the current (limit current) flowing in this region depends on the oxygen concentration in the exhaust gas (and thus A / F). Change.

Therefore, in the present embodiment, the constant voltage output circuit 4
Voltage AFC to one end (inner electrode) of A / F sensor 2 from
By applying a drive voltage AFV (for example, 2.7 V) lower than the constant voltage AFC to the other end (outer electrode) of the A / F sensor 2 from the drive voltage output circuit 6,
An A / F detection voltage Vp (= AFC-AFV; for example, +30
0 mV), and the A / F is detected by measuring the limit current Ip flowing to the A / F sensor 2 at that time (see FIG. 2).

The A / F sensor 2 can be activated at a predetermined temperature or higher to detect the A / F, and the detection result changes depending on the temperature. A heater (not shown) for heating the main body and controlling the temperature to a constant temperature (for example, 700 ° C.) is separately provided. Then, in order to maintain the sensor temperature at a predetermined temperature, it is necessary to detect the sensor temperature and control the amount of current supplied to the heater.

Therefore, in this embodiment, the driving voltage AFV is temporarily changed to the constant voltage A while the constant voltage AFC is applied from the constant voltage output circuit 4 to one end (inner electrode) of the A / F sensor 2.
Switching to a higher voltage than FC (eg 3.3V)
By controlling the voltage between both ends of the A / F sensor 2 to an internal resistance detection voltage Vn (for example, -300 mV) in a direction opposite to that at the time of A / F detection, and measuring a current In flowing through the A / F sensor 2 at that time The internal resistance Rn (= Vn / In) of the A / F sensor 2 corresponding to the sensor temperature is calculated from the current In and the internal resistance detection voltage Vn (see FIG. 2).

When a voltage in the opposite direction to that during the A / F detection is applied between the electrodes of the A / F sensor 2 to detect the internal resistance Rn, the current flows temporarily in the opposite direction. Thus, oxygen is adsorbed on the inner electrode. Therefore, even after the internal resistance Rn is detected, even if the direction of voltage application is returned for A / F detection, A / F is maintained until oxygen adsorbed on the inner electrode is exhausted.
F cannot be detected accurately.

Therefore, in this embodiment, after the detection of the internal resistance Rn, the driving voltage AFV is temporarily switched to a lower voltage (for example, 2.4 V) than that at the time of A / F detection, and the A / F sensor 2 By applying a return voltage (for example, +600 mV) between the electrodes with the same polarity as that at the time of A / F detection and higher than that at the time of A / F detection, oxygen adsorbed on the inner electrode is quickly discharged, and the A / F Can be promptly returned to the detection operation.

The air-fuel ratio detecting device of this embodiment includes:
In order to realize the A / F detection operation, the internal resistance detection operation, and the return operation, as shown in FIG.
A microcomputer 10 for switching the FV and controlling the heater is provided, and the voltage output circuits 4 and 6 are configured as follows.

First, the drive voltage output circuit 6 receives a drive command voltage command value DAFV output from the microcomputer 10 via the D / A converter 8 as an analog voltage signal. In the drive voltage output circuit 6, the voltage signal from the D / A converter 8 is smoothed by an integration circuit including a resistor R4 and a capacitor C1, and this is used as a drive voltage AFV to provide a buffer circuit including an operational amplifier OP2. Through the other end (outer electrode) of the A / F sensor 2 (see FIG. 3).

Note that the microcomputer 10 usually has a drive voltage AF
A command value DAFV for controlling V to a voltage value for A / F detection is output, and the command value DAFV is set to a drive voltage once every predetermined period (for example, 128 msec.) (For example, 4.5 msec.). The AFV is sequentially switched to a voltage value for detecting the internal resistance and a voltage value for returning.

Further, the constant voltage output circuit 4 supplies the power supply voltage Vb
(For example, 5V) to generate a reference voltage, the voltage dividing resistors R1 and R2, and the non-inverting input terminal (+) are connected to the resistor R1 and R2.
The inverting input terminal (-) is directly connected to one end (inside electrode) of the A / F sensor 2, and the output terminal is connected to one end (inside electrode) of the A / F sensor 2 by R2. And an operational amplifier OP1 connected via a resistor R3.

Accordingly, from the output terminal of the operational amplifier OP1, one end (inner electrode) of the A / F sensor 2 is connected to the resistors R1 and R2.
A voltage for controlling the same voltage as the reference voltage generated in 2 is output, and one end of the A / F sensor 2 is controlled to a constant voltage AFC equal to the reference voltage. Also, at this time, the same current as the current flowing through the A / F sensor 2 flows through the resistor R3, and the output terminal voltage of the operational amplifier OP1 corresponds to the current flowing through the A / F sensor 2. This voltage is used as the detection voltage Vs of the A / F and the internal resistance (see FIG. 3).

Then, the microcomputer 10 converts the detected voltage Vs obtained when the driving voltage AFV is controlled to the voltage for detecting the internal resistance into the A / D converter 1 for controlling the heater.
From the detection voltage Vs, the resistance value of the resistor R3, and the constant voltage AFC applied to the A / F sensor 2,
Current In ｛flowing to A / F sensor 2 = (AFC−Vs)
/ R3}, and based on the current In and the internal resistance detection voltage Vn, the internal resistance Rn (= V
(n / In) is calculated, and the current supplied to the heater is controlled so that the internal resistance Rn becomes a predetermined value (in other words, the sensor temperature becomes a predetermined temperature).

On the other hand, the detection voltage Vs obtained when the drive voltage AFV is controlled to the voltage for detecting the A / F is A / F
Since the detected voltage Vs corresponds to the limit current (and thus the A / F) flowing through the F sensor 2, it is necessary to output this detection voltage Vs to a control device that controls the amount of fuel supplied to the internal combustion engine. However, if this detection voltage Vs is output to the control device of the internal combustion engine as it is, the detection voltage Vs does not correspond to the A / F when the internal resistance of the A / F sensor 2 is detected or when the A / F sensor 2 returns thereafter. A / F cannot be controlled accurately.

Therefore, the air-fuel ratio detecting device of this embodiment includes:
A sample-and-hold circuit 14 is provided as a circuit that outputs the detection voltage Vs to the control device of the internal combustion engine. When the A / F is detected, the detection voltage Vs is directly used as the detection signal AF of the A / F.
O is output to the control device, and at the time of internal resistance detection and subsequent recovery, a voltage value holding the detection voltage Vs at the time of A / F detection is output to the control device as a detection signal AFO.

In order to implement such a sample / hold operation, a sample / hold switching signal S / H is input from the microcomputer 10 to the sample / hold circuit 14, and the sample / hold circuit 14 receives the sample / hold switching signal S / H.
When H is at the low level, the detection voltage Vs that has been output until then is held (see FIG. 3).

Next, the sample and hold circuit 1 of the present embodiment
4 are two operational amplifiers OP3 and O2 as shown in FIG.
P4 and a hold capacitor C2. The operational amplifier OP3 incorporates the output open circuit of the present invention, and has an output terminal connected to one end of the hold capacitor C2 and an inverting input terminal (-).
And the non-inverting input terminal (+) is connected to the operational amplifier OP
1 and receives the detection voltage Vs.
The other end of the holding capacitor C2 is grounded to the ground of the air-fuel ratio detecting device.

On the other hand, the operational amplifier OP4 is a buffer circuit for outputting the voltage (charging voltage) across the hold capacitor C2 to the control device of the internal combustion engine as an A / F detection signal AFO. (+) Is connected to the output terminal of the operational amplifier OP3, and the inverting input terminal (-)
Is connected to the output terminal.

The sample / hold switching signal S / output from the microcomputer 10 is supplied to the operational amplifier OP3.
When H is input and the detection signal Vs at which the switching signal S / H becomes High level is sampled, the general operational amplifier OP3
Operates as a hold capacitor C from the output terminal.
2 and a signal Vo having the same voltage as the detection voltage Vs is output to the operational amplifier OP4. When the detection voltage Vs at which the switching signal S / H is at the low level is held, the output transistor of the push-pull output circuit constituting the output stage is cut off. Turn off,
Open the output.

As a result, at the time of hold, the operational amplifier O
The voltage charged in the hold capacitor C2 at the time of sampling is output from P4, and the detection signal AFO output to the control device is held at the voltage value at the time of sampling. Hereinafter, the operational amplifier OP3 which is a main part of the present invention will be described.
Will be described. In the following description, FIGS. 4 to 6 show the configuration of the operational amplifier OP3 of the first to third embodiments corresponding to claims 2 to 4, respectively. The configuration is all the same as that of the sample and hold circuit 14 shown in FIG.

As shown in FIG. 4, the operational amplifier OP3 of the first embodiment includes a power supply terminal to which the power supply voltage Vb on the high potential side of the DC power supply is applied, and a low potential side (ground; GN) of the DC power supply.
D), and operates by receiving power supply through these terminals. The operational amplifier OP3 includes a differential amplifier 50 in an input stage, a common emitter amplifier 60 for amplifying an output from the differential amplifier 50 in a next stage, and a push-pull output circuit 70 in an output stage. Further, the operational amplifier OP3 has an input terminal to which the switching signal S / H from the microcomputer 10 is input, and a low-level switching signal S / H to be a hold command to this input terminal.
Is input, an output open circuit 80 for opening the output of the push-pull output circuit 70 to an open state is provided.

First, the differential amplifier 50 has an emitter connected to a power supply line (power supply voltage Vb) via a resistor R50, and a base connected to an external control signal V for controlling a current.
and a PNP transistor Tr50 that is connected to a control terminal that receives C and outputs a constant current corresponding to the control signal Vc from the five collectors. The PNP transistor T
r50 is a constant current source of the differential amplifier 50.

The differential amplifier 50 has the following eight transistors.・ Base is inverted input terminal (-input) via resistor R51
And the emitter is a PNP transistor T
A PNP transistor Tr51 connected to the first collector of r50 and having the collector grounded.

A PNP transistor Tr52 whose base is connected to the emitter of the PNP transistor Tr51 and whose emitter is connected to the second collector of the PNP transistor Tr50. A PNP transistor Tr5 whose base is connected to a non-inverting input terminal (+ input) via a resistor R52, whose emitter is connected to the third collector of the PNP transistor Tr50, and whose collector is grounded;
3.

The base is connected to the emitter of the PNP transistor Tr53, and the emitter is connected to the PNP transistor T53 together with the emitter of the PNP transistor Tr52.
a PNP transistor Tr54 connected to the second collector of r50. A PNP transistor Tr55 whose emitter is connected to the fourth collector of the PNP transistor Tr50, whose base is connected to the collector of the PNP transistor Tr52, and whose collector is grounded;

The emitter is a PNP transistor Tr50
PNP transistor Tr56 whose base is connected to the collector of PNP transistor Tr54, and whose collector is grounded. An NPN transistor Tr57 whose collector is connected to the collector of the PNP transistor Tr52 (and thus the base of the PNP transistor Tr55), whose emitter is connected to the ground line, and whose base is connected to its own collector.

The collector is a PNP transistor Tr54
Of the NPN transistor Tr57, the emitter is connected to the ground line, the base is connected to the base of the NPN transistor Tr57, and the NPN transistor Tr57 forms a current mirror circuit with the NPN transistor Tr57. Tr
58.

On the other hand, the common emitter amplifier 60 has an emitter connected to the power supply line and a base connected to the PN.
PNP transistor Tr61 connected to the base of P transistor Tr50 and outputting a constant current from the collector
And a base connected to the emitter of the PNP transistor Tr56, a collector connected to the collector of the PNP transistor Tr61, and an emitter connected to the resistor R61.
, An NPN transistor Tr63 connected to the ground line via the NPN transistor Tr63, a base connected to the emitter of the NPN transistor Tr63, an emitter connected to the ground line, and a collector connected to the phase compensating capacitor C61.
And an NPN transistor Tr64 connected to the base of the PNP transistor Tr56 via a PNP transistor Tr56, and a pair of diodes D61 and D62 connected in series between the collector of the NPN transistor Tr63 and the ground line with the ground side as a cathode. ing.

That is, in the operational amplifier shown in FIG. 4, signals from the inverting input terminal (-input) and the non-inverting input terminal (+ input) are transmitted via Darlington-connected PNP transistors Tr51, Tr52 and Tr53, Tr54, respectively. NPN transistor Tr6, which is a well-known type having a built-in capacitor C61 for phase compensation and serving as a signal output section of common emitter amplifier 60
A voltage corresponding to the potential difference between the input signal to the inverting input terminal and the non-inverting input terminal is generated at the collector of No. 4.

Next, the push-pull output circuit 70 is a transistor for outputting a signal (Vo), a first NPN transistor Tr71 having a collector connected to the power supply line and an emitter connected to the output terminal, and a collector connected to the ground. A PNP transistor Tr72 connected to the line and having an emitter connected to the output terminal. And NP
Between the base and the emitter of the N transistor Tr71 and P
Between the base and the emitter of the NP transistor Tr72,
The resistors R71 and R72 are respectively connected.

Further, between the base of the NPN transistor Tr71 and the base of the PNP transistor Tr72,
A pair of diodes D71 and D72 connected in series to each other
Is provided. These diodes D71, D72
Means that each transistor Tr71, T
The voltage between bases of r72 is set to the respective transistors Tr71 and T71.
r72 is for maintaining the forward voltage (about 1.4 V) of two operable diodes, and the anode is N
They are connected to each other in the forward direction such that they are on the base side of the PN transistor Tr71 and the cathode is on the base side of the PNP transistor Tr72.

The base of the PNP transistor Tr72 is connected to the collector of an NPN transistor Tr64, which is the output transistor of the common emitter amplifier 40. The output from the common emitter amplifier 40 is PNP
The signal is input to the base of the transistor Tr72.

Next, an NPN transistor Tr7 is provided between the base of the NPN transistor Tr71 and the power supply line.
1 and a PNP transistor Tr73 whose emitter is connected to the power supply line and whose collector is connected to the base of the NPN transistor Tr71 in order to supply a bias current for driving the PNP transistor Tr72. The base of the PNP transistor Tr73 is connected to the base of the PNP transistor Tr73.

The PNP transistor Tr74 forms a current mirror circuit together with the PNP transistor Tr73. The emitter of the PNP transistor Tr74 is connected to the power supply line, and the collector is connected to its own base. Also, PNP transistors Tr73 and Tr7
4 is connected to a power supply line via a resistor R73.

The collector of the PNP transistor Tr74 is connected to the collector of the NPN transistor Tr75 whose emitter is connected to the ground line.
The base of the N transistor Tr75 is connected to the base of the NPN transistor Tr76. Also, this NP
The emitter of the N-transistor Tr76 is connected to the ground line, the collector is connected to its own base, and the emitter is connected to the collector of a PNP transistor Tr78 whose power supply line is connected. And P
The base of the NP transistor Tr78 is a differential amplifier 50
And the bases of the PNP transistor Tr50 in the inside and the PNP transistor Tr61 in the common emitter amplifier 60, and are connected to a control terminal for receiving a control signal Vc for current control from outside.

As a result, the PNP transistor Tr78
Functions as a constant current source that supplies a constant current from the power supply line to the NPN transistor Tr76 side, and a constant current flows through the NPN transistor Tr76. Further, since the NPN transistor Tr76 and the NPN transistor Tr75 form a current mirror circuit, the same constant current flows through the NPN transistor Tr75 as that of the NPN transistor Tr76.
The same constant current also flows through the PNP transistor Tr73.

Next, the output open circuit 80 includes an inverter INV for inverting the High / Low level of the switching signal S / H from the microcomputer 10 and three NPN transistors Tr.
1 to Tr3, and three resistors R81 to R83 connected to the bases of the transistors Tr1 to Tr3 and the output of the inverter INV.

The collector of the NPN transistor Tr1 is connected to the collector of the NPN transistor Tr76 in the push-pull output circuit 70, and the emitter is connected to the emitter of the NPN transistor Tr76. The collector of the NPN transistor Tr2 is connected to the NPN transistor Tr64 in the common emitter amplifier 60.
And the emitter is also grounded to the ground line. The collector of the NPN transistor Tr3 is connected to the PNP transistor T in the differential amplifier 50.
The base is connected to the base of r53 (in other words, the input line of the detection voltage Vs), and the emitter is similarly grounded to the ground line.

In the operational amplifier OP3 of this embodiment thus configured, when the high-level switching signal S / H is input from the microcomputer 10 (that is, at the time of sampling), the NPN transistor Tr1 is turned off. And the NPN transistors Tr75, Tr76, and PN
Each of the P transistors Tr74 and Tr73 functions as a current mirror circuit, and supplies a base current to the output NPN transistor Tr71. Further, since the NPN transistor Tr2 is also turned off, the NPN transistor Tr64 operates normally, the base current of the Tr72 flows, and the NPN transistor Tr3 is also turned off, so that the input signal ( That is, the detection voltage Vs) is transmitted to the differential pair of PNP transistors. Therefore, the operational amplifier OP3 operates normally, and a signal Vo having the same potential as the detection voltage Vs is output from its output terminal.

On the other hand, the switching signal S / H from the microcomputer 10
Becomes low level (that is, during hold), NP
When the N-transistor Tr1 is turned on, the constant current supplied from the PNP transistor Tr78 flows to the ground line side, and the NPN transistors Tr75 and Tr76
, And the current flowing through the current mirror circuit including the PNP transistors Tr74 and Tr73, in other words, the base current of the output PNP transistor Tr71. Also, NP
When the N-transistor Tr2 is turned on, the base of the PNP transistor Tr64 is grounded to the ground line,
Since the NPN transistor Tr64 is turned off, the base of the output NPN transistor Tr71 becomes high impedance. Therefore, the output transistor Tr7
1, 72 are both turned off, and the operational amplifier OP3
Is in a high impedance open state.
In the present embodiment, the NPN transistors Tr1 and Tr2 that turn off the output transistors Tr71 and Tr72 and open the output in this way correspond to cut-off means of the present invention.

When the switching signal S / H is held at the low level, the NPN transistor Tr3 is also turned on, so that the base of the PNP transistor Tr53 connected to the non-inverting input terminal is grounded to the ground line,
Fixed to w level. And a PNP transistor T
r54 enters the saturation operation region, and the NPN transistor Tr
Reference numeral 58 indicates a non-operating state, and the collector of the PNP transistor Tr54 has a high impedance because the base of the PNP transistor Tr56 is connected to the collector. Then, since the emitter current of the PNP transistor 54 flows to the ground, the potential of the phase compensation capacitor C61 on the differential amplifier 50 side becomes high impedance, and the charge of the phase compensation capacitor C61 is held. Therefore, the potential of the phase compensation capacitor C61 is fixed, and the potential of the output signal Vo, in other words, the potential of the hold capacitor C2 is stabilized. In this embodiment, the NPN transistor Tr3 for fixing the potential of the phase compensation capacitor C61 in this manner corresponds to the potential fixing means of the present invention.

As described above, in the operational amplifier OP3 of the first embodiment, as shown in FIG. 7, not only the output transistors Tr71 and 72 are cut off to hold the output open at the time of holding, but also as shown in FIG. Since the input line of the detection voltage Vs is grounded by the NPN transistor Tr3 and the potential A of the phase compensation capacitor C61 on the side of the differential amplifier 50 is fixed, detection is performed by a change in the drive voltage AFV of the A / F sensor 2 during holding. Even if the voltage Vs changes abruptly, due to the AC coupling of the phase compensating capacitor C61, the change of the detection voltage Vs causes the change of the detection voltage Vs to the push-pull output circuit 70 side (potential B See)
The output signal Vo (in other words, the potential of the hold capacitor C2) does not change, and the potential of the hold capacitor C2 can be reliably held.

Therefore, according to the sample and hold circuit 14 of the present embodiment, an analog switch for opening the output of the operational amplifier is provided between the operational amplifier of the input stage and the hold capacitor C2 as in the prior art. It is not necessary, and the output voltage (detection signal A
FO) can be reliably prevented from fluctuating. Therefore, according to the present embodiment, a sample-hold circuit that can obtain a stable hold characteristic can be configured without using a MOS-type FET, and the entire air-fuel ratio detection device excluding the sample-hold circuit 14 and the A / F sensor 2 Can easily be made into an IC.

In this embodiment, since the resistors R71 and R72 are provided between the base and the emitter of each of the transistors Tr71 and Tr72 for output in the operational amplifier OP3, when each of the transistors Tr71 and Tr72 is off, Even when the potential between the base and the emitter is set to the same potential and the high voltage is held in the phase compensation capacitor C61 connected to the output terminal of the operational amplifier OP3, it is possible to prevent the transistors Tr71 and Tr72 from breaking down. .

Further, in this embodiment, the PN constituting the current mirror circuit in the push-pull output circuit 70
The bases of the P transistors Tr74 and Tr73 are connected to a resistor R
Since it is connected to the power supply line via the switch 73, even if a leak current flows to the base during the hold, the PNP transistor Tr73 does not operate and the bias current does not flow to the NPN transistor Tr71 side. . That is, in the present embodiment, a more stable open state can be held during holding by the resistor R73 provided in the current mirror circuit.

Next, the operational amplifier OP3 of the second embodiment shown in FIG. 5 is different from the operational amplifier OP3 of the first embodiment shown in FIG.
Is changed as follows, and the other configuration is exactly the same as the operational amplifier OP3 of the first embodiment. That is, the operational amplifier OP3 according to the second embodiment includes the resistors R82 and R83 and the NPN in the output open circuit 80 according to the first embodiment.
The transistors Tr2 and Tr3 are deleted, and the collector is replaced by the PNP transistor Tr56 in the differential amplifier 50.
And an NPN transistor Tr4 whose emitter is grounded to a ground line, and whose base is connected to the output of the inverter INV via a resistor R84.

In the operational amplifier OP3 of the present embodiment thus configured, the NPN transistors Tr1. Tr4 is turned on, the current from the PNP transistor Tr73 is cut off on the push-pull output circuit 70 side, and the differential amplifier 50 side of the phase compensation capacitor C61 is grounded to the ground line via the NPN transistor Tr4. Therefore, as shown in FIG. 7, the output signal Vo can be held without being affected by the detection voltage Vs. Therefore, even if the operational amplifier OP3 is configured as in the second embodiment shown in FIG. 5, the same effect as in the above embodiment can be obtained.

However, the switching signal S / H is changed from the low level to the high level.
Immediately after the change to the gh level (that is, immediately after the NPN transistor Tr4 is turned off), the potential A of the phase compensation capacitor C61 on the differential amplifier 50 side changes to a voltage corresponding to the detection voltage Vs. As a result, the potential B of the phase compensating capacitor C61 on the push-pull output circuit 70 side temporarily rises rapidly, and spike noise is output from the output terminal (see FIG. 7). Therefore, it is desirable to use the sample and hold circuit using the operational amplifier OP3 of the second embodiment in a system that does not require an output when a change from hold to sample occurs.

Next, the operational amplifier OP3 of the third embodiment shown in FIG. 6 is different from the operational amplifier OP of the first embodiment shown in FIG.
P3 is changed as follows, and other configurations are the first.
The configuration is exactly the same as the operational amplifier OP3 of the embodiment. That is, the operational amplifier OP3 of the second embodiment eliminates the resistor R83 and the NPN transistor Tr3 in the output open circuit 80 of the first embodiment, and provides the base of the PNP transistor Tr50 serving as a constant current source in the differential amplifier 50, In the push-pull output circuit 70, the bases of the PNP transistors Tr73 and Tr74 constituting the current mirror circuit are connected, and the bases of the common emitter amplifier 60 and the PNP transistors Tr61 and Tr78 constituting the constant current source in the push-pull output circuit 70. Is separated from the base of the PNP transistor Tr50, and the control signal Vc for current control input to the control terminal is input to the base of each of the PNP transistors Tr61 and Tr78. In the operational amplifier OP3 of the third embodiment configured as described above, if the switching signal S / H is at the high level and the transistor Tr1 is in the off state, the PN
Since the same current as the current flowing through the P transistors Tr73 and Tr74 is output from each collector of the PNP transistor Tr50, the PNP transistor Tr50 functions as a constant current source in the differential amplifier 50 as in the first embodiment. . However, when the switching signal S / H becomes Low level and the transistor Tr1 is turned on, the current flowing through the PNP transistors Tr73 and Tr74 is cut off, so that the current from each collector of the PNP transistor Tr50 is also cut off. As a result, the operation of the differential amplifier 50 is stopped, and the potential of the phase compensation capacitor C61 is fixed. Therefore, the operational amplifier OP3 of the third embodiment can obtain exactly the same effect as the operational amplifier OP3 of the first embodiment.

In the operational amplifier OP3 of the second embodiment and the third embodiment, the operation of each part other than the above description is the same as that of the first embodiment.
The description is omitted because it is the same as the embodiment. Then, in the second embodiment, the NPN transistor Tr1 functions as cut-off means, and the NPN transistor Tr4 functions as potential fixing means. In the third embodiment, the NPN
The transistors Tr1 and Tr2 function as cut-off means, and stop operation when the NPN transistor Tr1 and the NPN transistor Tr1 are turned on.
Tr76 and PNP transistors Tr74 and 73 function as potential fixing means.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments.
Various embodiments can be adopted. For example, in the above embodiment, as the operational amplifier OP3 constituting the input stage of the sample-hold circuit, signals from the inverting input terminal and the non-inverting input terminal are input via PNP transistors Tr51, Tr52 and Tr53, Tr54 respectively connected in Darlington. The above description has been made with reference to an example of an operational amplifier having a differential amplifier configured to perform the above-described operation and further including a capacitor C61 for phase compensation. However, the present invention can be applied to any type of operational amplifier. For example, the present invention can be applied to an operational amplifier having an externally provided capacitor for phase compensation.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of an entire air-fuel ratio detection device according to an embodiment.

FIG. 2 is an explanatory diagram illustrating operations of A / F detection and internal resistance detection in the air-fuel ratio detection device according to the embodiment.

FIG. 3 is a time chart for explaining signal waveforms of each part of the air-fuel ratio detection device of the embodiment.

FIG. 4 is an electric circuit diagram illustrating a configuration of a first embodiment of an operational amplifier OP3 included in the sample-hold circuit illustrated in FIG.

FIG. 5 is an electric circuit diagram showing a configuration of an operational amplifier OP3 according to a second embodiment.

FIG. 6 is an electric circuit diagram showing a configuration of an operational amplifier OP3 according to a third embodiment.

FIG. 7 is an operational amplifier OP of the first embodiment and the second embodiment.
FIG. 3 is an explanatory diagram for explaining voltages A and B and an output signal Vo at both ends of a phase compensation capacitor No. 3;

FIG. 8 is an explanatory diagram illustrating a configuration of a conventional sample and hold circuit using an operational amplifier.

[Explanation of symbols]

14 sample-hold circuit OP3 operational amplifier C2 hold capacitor OP4 operational amplifier (buffer circuit) 50 differential amplifier 60 common emitter amplifier 70 push-pull output circuit 80 output open circuit C61 phase compensation capacitor

Claims (5)

[Claims] An output terminal and an inverting input terminal are connected to the other end of the hold capacitor, and the hold capacitor is connected to a non-inverting input terminal. An operational amplifier that charges to a voltage corresponding to the above, a buffer circuit that outputs a charge voltage of the hold capacitor, and when an external hold command is received, the output of the operational amplifier is opened and the output from the buffer circuit is fixed. A sample-and-hold circuit comprising: an output open circuit that outputs an NPN transistor and a PNP transistor for output in a push-pull output circuit that constitutes an output stage of the operational amplifier according to the hold command. Cut-off means for cutting off; and Ri, the sample-hold circuit, characterized by comprising consist of, a potential fixing means for fixing the potential of the phase compensation capacitor provided in the operational amplifier. 2. The sample and hold circuit according to claim 1, wherein said potential fixing means fixes an input portion of said input signal to said operational amplifier to a predetermined potential. 3. The sample according to claim 1, wherein the potential fixing means fixes a connection between a differential amplifier constituting an input stage of the operational amplifier and the phase compensation capacitor at a predetermined potential. Hold circuit. 4. The sample and hold circuit according to claim 1, wherein said potential fixing means stops operation of a constant current source provided in a differential amplifier constituting an input stage of said operational amplifier. 5. The push-pull output circuit according to claim 1, wherein
5. The sample and hold circuit according to claim 1, further comprising a resistor connected between the base and the emitter of the N transistor and the PNP transistor.