JPH10283785A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize an operation, and speed up the access time of, for example, a synchronous SRAM containing a burst counter by performing the shift operation of a shift register selectively depending on whether a burst mode is linear or interleave sequence. SOLUTION: When a synchronous SRAM is set to a normal operation mode, only the initial setting of flip flops FF1-FF4 is performed by an internal clock signal BBC in a burst counter BC and a shift register is not shifted by an internal clock signal CBC. Therefore, predecode signals /a0/a1, a0/a1, /a0a1, a0a1 corresponding to a column being specified by address signals A0-A1 are set to a high level during one cycle. A signal path until the predecode signals are formed is the same regardless of an operation mode and a transfer delay time difference between the operation modes is small, thus preventing a hazard against the predecode signal from being generated and speeding up an access time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a synchronous SR having a burst mode.
The present invention relates to an AM (Static Random Access Memory) and a technique which is particularly effective when used for shortening the access time.

[0002]

2. Description of the Related Art There is a semiconductor device such as a synchronous SRAM having a so-called burst mode which operates synchronously according to a predetermined clock signal and has access to a predetermined number of continuous column addresses. In addition, there is a cache memory including a data memory composed of such a synchronous SRAM as a constituent element, and there is a digital system such as a personal computer including such a cache memory.

[0003]

Prior to the present invention, the present inventors have developed a synchronous SRAM having a burst mode, and encountered the following problems in the process. That is, as shown in FIG. 6, the synchronous SRAM has address signals A0 to A0 of lower 2 bits.
An address register AR0 to AR1 receiving A1 and a burst counter BC are provided. Among these, the address registers AR0 to AR1 fetch and hold the address signals A0 to A1, respectively, according to the internal clock signal BBC. After the burst counter BC is reset according to the internal clock signal BBC, the internal clock signal CBC is reset.
A step operation is performed according to BC.

Complementary output signals A0 * to A1 * of address registers AR0 to AR1 and burst counter BC
(Here, for example, the non-inverted output signal A0 and the inverted output signal A0B are collectively represented by an asterisk (*) like a complementary output signal A0 *. In the following circuit diagrams and block diagrams, this is valid. A so-called inverted signal or the like which is selectively set to a low level sometimes has a horizontal line at the top of its name, but in the following description of this specification, a / is added immediately before the name or a B is added immediately after the name. And Q0 * to Q1 * are exclusive-OR circuits EO1 to EO.
After being combined by O4, complementary internal address signals a0 * to a1 * are obtained.

The complementary internal address signals a0 * to a1 * are
After being combined by logic gates Gm to Gl of predecoder PD, predecode signals / a0 / a1, a
0 / a1, / a0a1 and a0a1 (where the predecode signals / a0 / a1, a0 / a1, / a0a1 and a0a1 are inverted internal address signals / a0 and / or
a1, a non-inverted internal address signal a0, an inverted internal address signal / a1, an inverted internal address signal / a0, a non-inverted internal address signal a1, and a logical product signal of the non-inverted internal address signals a0 and a1, respectively. Hereinafter the same)
Becomes

When the synchronous SRAM is set to the normal operation mode for single access, address signals A0 to A1 input from a cache memory control circuit (not shown) of the cache memory are applied to address registers AR0 to AR0.
AR1 passes through exclusive OR circuits EO1 to EO4 and a relatively shallow logic circuit via predecoder PD to become predecode signals / a0 / a1, a0 / a1, / a0a1 and a0a1, but synchronous SRAM operates in burst mode. , Complementary output signals Q0 * to Q1 of burst counter BC having a relatively deep logic configuration
* Indicates a predecode signal / a0 / a1, a0 / via exclusive OR circuits EO1 to EO4 and predecoder PD.
a1, / a0a1 and a0a1.

That is, from the column address signals A0 to A1, the predecode signals / a0 / a1, a0 / a1, / a0
The signal path until a1 and a0a1 are formed is:
The transmission delay time varies depending on the operation mode of the synchronous SRAM, and the transmission delay time differs. For this reason, it becomes difficult to control the timing of the synchronous SRAM, and the access time is delayed. In addition, general synchronous S
As is well known, the burst mode of the RAM includes a linear sequence in which a 2-bit flip-flop constituting a burst counter BC advances in a forward order according to a logical condition of a binary counter, and an interleave sequence in which the steps advance in a reverse order. However, if a logic circuit necessary for switching these sequences is added, the difference in the transmission delay time between the two signal paths is further increased, and the access time of the synchronous SRAM is further reduced. In addition, predecode signals / a0 / a1, a0 / a1, / a0a1
And a predecoder PD for selectively forming a0a1
Is behind the burst counter BC, the hazard associated with decoding is reduced by the predecode signals / a0 / a1, a0.
/ A1, / a0a1 as well as a0a1, thereby producing a synchronous SRAM including a burst counter BC.
Operation becomes unstable.

It is an object of the present invention to compress a difference in transmission delay time of a column address signal between a normal operation mode and a burst mode of a burst counter, and to speed up an access time of a synchronous SRAM including a burst counter.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a synchronous SRAM or the like having a burst mode and having, for example, a burst counter for autonomously specifying a lower-order n-bit column address, the burst counter is set to 2 n bits based on the n-bit column address. And a shift register comprising 2 n flip-flops selectively set or reset in accordance with the corresponding predecode signal. , The shift operation of the shift register is selectively performed in the normal or reverse order depending on whether the burst mode is a linear or interleaved sequence.

According to the above-described means, the delay time of the column address signal with respect to the clock signal is reduced, and the occurrence of a hazard in the predecode signal is prevented while the burst counter such as the synchronous SRAM operates in the normal operation mode. The difference in transmission delay time of the column address signal in the burst mode can be reduced. As a result, while the operation is stabilized, the timing control of the burst counter can be facilitated and the access time of a synchronous SRAM or the like including the burst counter can be shortened. The operation of a memory or the like can be accelerated, and the machine cycle of a personal computer or the like including a cache memory can be accelerated.

[0012]

FIG. 1 shows a synchronous SRAM (SSRAM1 and SSRAM) to which the present invention is applied.
A block diagram of one embodiment of the cache memory CACH including 2) is shown. First, an outline of the configuration and operation of a cache memory CACH as an application example of the synchronous SRAM of this embodiment will be described with reference to FIG. The cache memory CACH is not particularly limited, but is included in a predetermined personal computer. FIG.
Includes a central processing unit CPU of a personal computer,
The clock generation circuit CG and a part of the system bus are shown together.

In FIG. 1, a cache memory CACH of this embodiment has one tag memory TAGM and two synchronous SRAMs (SSRAM1 and SSRAM).
2) and one cache memory control circuit CCTL. Of these, tag memory T
The AGM is coupled to the central processing unit CPU via upper predetermined bits of the address bus ABUS, and an output signal thereof, that is, a hit signal HT is supplied to the cache memory control circuit CCTL. This cache memory control circuit CCTL is further supplied with a predetermined clock signal CLK from a clock generation circuit CG. Further, a predetermined-bit control signal CTL from the central processing unit CPU and 4-bit byte write enable signals BW0B to BW3B
And an address status processing signal ADSPB.

On the other hand, the synchronous SRAMs (SSRAM1 and SSRAM2) constituting the data memory are coupled to the lower 15 bits A0 to A14 of the address bus ABUS, and one synchronous SRAM (SSR
AM1) is a lower 32 bit data bus DBUS.
L (D0-D31) and the other synchronous S
The RAM (SSRAM2) is further coupled to an upper 32-bit data bus DBUS (D32 to D63). A clock signal CLK is commonly supplied from a clock generation circuit CG to the synchronous SRAMs (SSRAM1 and SSRAM2), and a byte write enable signal BW0B to BW3B and an address status processing signal ADSPB are commonly supplied from a central processing unit CPU.

In the synchronous SRAMs (SSRAM1 and SSRAM2), an address advance signal ADVB, an address status control signal ADSCB, a global write enable signal GWB, and a byte write enable signal BW are further supplied from the cache memory control circuit CCTL.
EB, a chip enable signal CE1B, and an output enable signal OEB are supplied. Synchronous SRAM
The chip enable signal input terminals CE2 of (SSRAM1 and SSRAM2) are commonly coupled to the power supply voltage VCC, and the chip enable signal input terminal CE2B is commonly coupled to the ground potential VSS. The mode control signal input terminal IMOD is commonly coupled to the ground potential VSS when the burst mode of the synchronous SRAM (SSRAM1 and SSRAM2) is set to the linear sequence, as shown by the dotted line in the figure, to form the interleave sequence. Are coupled in common to the power supply voltage VCC.

Tag memory T of cache memory CACH
The AGM includes a tag written at each address,
A tag output from the central processing unit CPU via a predetermined upper bit of the address bus ABUS is compared and collated, and when all the bits match, the output signal, that is, the hit signal HT is selectively set to a high level.

The cache memory control circuit CCTL receives the hit signal HT supplied from the tag memory TAGM, the control signal CTL supplied from the central processing unit CPU, the byte write enable signals BW0B to BW3B, and the address status processing signal ADSPB. And address advance signal ADVB, address status control signal ADSCB, global write enable signal GW
B, byte write enable signal BWEB, chip enable signal CE1B, and output enable signal OEB
Are selectively formed at a predetermined timing, and the synchronous S
It supplies to RAM (SSRAM1 and SSRAM2).

The synchronous SRAMs (SSRAM1 and SSRAM2) operate synchronously according to a clock signal CLK supplied from a clock generation circuit CG, and an address advance signal ADVB and an address status control signal ADS supplied from a cache memory control circuit CCTL.
According to CB, global write enable signal GWB, byte write enable signal BWEB, chip enable signal CE1B and output enable signal OEB,
32-bit data D for an address specified by the lower 15 bits A0 to A14 of the address bus ABUS
The write or read operation of 0 to D31 or D32 to D63 is executed.

FIG. 2 shows the cache memory CAC of FIG.
1 is a block diagram of an embodiment of a synchronous SRAM (SSRAM1) included in H. Based on the figure,
Synchronous SRAM (SSRA) to which the present invention is applied
An outline of the configuration and operation of the M1 and the SSRAM 2) will be described. The circuit elements constituting each block in FIG. 2 are a known MOSFET (Metal Oxide Semiconductor Field Effect Transistor; in this specification, a MOSFET is a generic term for an insulated gate field effect transistor) integrated circuit. It is formed on one semiconductor substrate such as single crystal silicon by a manufacturing technique. In the following description, a synchronous SRAM (SSRAM1) is taken as an example to
M (SSRAM1 and SSRAM2) will be described.

In FIG. 2, a synchronous SRAM (SSRAM1) of this embodiment has a memory array MARY arranged so as to occupy most of the surface of a semiconductor substrate as its basic component. Although not particularly limited, the memory array MARY has a storage capacity of 16,384 words, that is, 16K (kilo) words × 32 bits, that is, a so-called 512 Kbit, and the address of the 16K words is alternatively selected by an address decoder AD. It is specified. The address decoder AD has 4 bits, that is, substantially 2 bits, of a predecode signal / a0 / a1, a0 from the burst counter BC.
/ A1, / a0a1 and a0a1 are supplied, and 13-bit complementary internal address signals a2 * to a14 * are supplied from the address register AR.

The burst counter BC has an address signal A of lower two bits via address input terminals A0 to A1.
0 to A1 are supplied, and a high-level or low-level mode control signal IMOD is supplied via a mode control signal input terminal IMOD. Also, the logic gate G1
From its output signal, that is, the internal clock signal CBC (second
, And its output signal, that is, an internal clock signal BBC (first internal clock signal) is supplied from the logic gate G3. The inverted signal of the address advance signal ADVB is supplied to one input terminal of the logic gate G1, and the clock signal CLK is supplied to the other input terminal from the clock generation circuit CG via the clock input terminal CLK. Also, the logic gate G3
The output signal of the logic gate G2 is supplied to one input terminal, and the clock signal CLK is supplied to the other input terminal.

An address status control signal ADSCB is supplied to one input terminal of the logic gate G2, and an output signal g9 of the logic gate G9 is supplied to the other input terminal. One input terminal of the logic gate G9 is supplied with an inverted signal of the chip enable signal CE1B, and the other input terminal is supplied with an inverted signal of the address status processing signal ADSPB.

As a result, the output signal g of the logic gate G9
9 is selectively set to a high level when both the chip enable signal CE1B and the address status processing signal ADSPB are set to a valid level, that is, a low level, and the output signal of the logic gate G2 is the output signal g9 of the logic gate G9 or the address status. When any one of the control signals ADSCB is set to the low level, the control signal is selectively set to the high level. The output signal of the logic gate G3, that is, the internal clock signal BBC is selectively set to the high level when the output signal of the logic gate G2 is set to the high level and the clock signal CLK is set to the high level.
, Ie, the internal clock signal CBC, is selectively set to a high level when the address advance signal ADVB is set to a low level and the clock signal CLK is set to a high level.

The burst counter BC has an address signal A
It includes a predecoder PD receiving 0 to A1 and a shift register including four flip-flops FF1 to FF4. Flip-flop F constituting this shift register
When the internal clock signal BBC is at a high level, F1 to FF4 output substantial output signals of the predecoder PD, that is, predecode signals / A0 / A1, A0 / A1, and / A.
In accordance with 0A1 and A0A1, each is selectively set or reset, and receives a high level of internal clock signal CBC to perform a shift operation. The non-inverted output signals of the flip-flops FF1 to FF4 are the predecode signals / a0 / a1, a0 / a1, / a0a1 and a0
It is supplied to the address decoder AD as a1.

In this embodiment, the burst counter B
The shift operation of the shift register composed of the C flip-flops FF1 to FF4 is performed in the normal order corresponding to the linear sequence when the mode control signal IMOD is at the low level, and is performed when the mode control signal IMOD is at the high level. , Are performed in reverse order to correspond to the interleave sequence. A more specific configuration and operation of the burst counter BC and its characteristics will be described later in detail.

The address register AR has a logic gate G3
In response to the rising edge of the internal clock signal BBC, the upper 13 bits of the address signals A2 to A14 are fetched and held, and complementary internal address signals a2 * to a14 * are formed based on these address signals. It is supplied to the address decoder AD. The address decoder AD is substantially 2 supplied from the burst counter BC.
Bit predecode signals / a0 / a1, a0 / a1,
/ A0a1 and a0a1 and address register AR
13-bit complementary internal address signal a2 supplied from
Decoding in combination with * to a14 *, the address of 16K words of the memory array MARY is selected alternatively, and the corresponding 32 memory cells are set to the selected state.

The 32 memory cells in the selected state of the memory array MARY include a synchronous SRAM (SS
When the RAM 1) is in the write mode, a predetermined write signal is selectively supplied from the write drivers WD0 to WD3 in units of 8 bits, that is, 1 byte. Also, when the synchronous SRAM (SSRAM1) is set to the read mode, 3
The 2-bit read signal is amplified by a corresponding unit circuit of the sense amplifier SA, and then read data rd0.
To rd31 to the data output buffer OB.

The write drivers WD0 to WD3 receive write data wd0 to wd3 from the data input buffer IB.
Each of the corresponding 8 bits of 1 is provided,
Output signals gi to gl of corresponding logic gates GI to GL are supplied, respectively. A clock signal CLK is supplied to the data input buffer IB, and 32-bit write data is supplied via data input / output terminals D0 to D31. Output signals gi to gl from the logic gates GI to GL are further supplied. Supplied. The output signals of the corresponding byte write enable signal registers WR0 to WR3 are supplied to one input terminal of each of the logic gates GI to GL, and the output signal er of the chip enable signal register ER is supplied to the other input terminal. Are commonly supplied. Byte write enable signal registers WR0
The clock signal CLK is commonly supplied to WR3, and the output signals of the corresponding logic gates GE to GH are also supplied to WR3. One input terminal of these logic gates GE to GH is connected to the output signal g9 of the logic gate G9.
Are supplied in common, and the output signals of the corresponding logic gates GA to GD are respectively supplied to the other input terminals.

An inverted signal of the global write enable signal GWB is commonly supplied to one input terminal of the logic gates GA to GD, and output signals of the corresponding logic gates G4 to G7 are respectively supplied to the other input terminals. Supplied. An inverted signal of the byte write enable signal BWEB is commonly supplied to one input terminal of these logic gates G4 to G7, and an inverted signal of the corresponding byte write enable signal BW0B to BW3B is supplied to the other input terminal. Supplied respectively.

From these, the logic gates G4 to G7
Are output when the byte write enable signal BWEB is at a low level and the corresponding byte write enable signals BW0B to BW3B are at a low level.
Each is selectively set to a high level. The output signals of the logic gates GA to GD are selectively set to the high level when the global write enable signal GWB is set to the low level or the output signals of the corresponding logic gates GA to GD are set to the high level. You. further,
The output signals of the logic gates GE to GH are obtained by setting the output signal g9 of the logic gate G9 to the high level and the output signals of the corresponding logic gates GA to GH to the high level.
Each is selectively set to a high level.

The high level of the output signal of each of the logic gates GE to GH is changed to a corresponding one of the byte write enable signal registers WR0 to WR in response to the rise of the clock signal CLK.
3 and stored. The high level of the non-inverted output signals of the byte write enable signal registers WR0 to WR3 is set on condition that the non-inverted output signal er of the chip enable signal register ER is set to the high level.
The signals are selectively transmitted to corresponding write drivers WD0 to WD3 via corresponding logic gates GI to GL, and serve as write control signals for each write driver.

As a result, the lower three data buses DBUS
Write data input via two bits is taken into the data input buffer IB in response to the rising edge of the clock signal CLK, and then written into the corresponding write driver WD0.
To WD3 are transmitted in 8-bit units. Then, on the condition that the byte write enable signal BWEB and the corresponding byte write enable signals BW0B to BW3B are set to low level, the data is written to the selected 32 memory cells of the memory array MARY in units of 8 bits, that is, bytes. The global write enable signal G
When WB is at a low level, the memory array MARY
Are performed simultaneously regardless of the byte write enable signal BWEB and the byte write enable signals BW0B to BW3B.

The data output buffer OB is further supplied with a clock signal CLK and a logic gate GO.
Is supplied. The output signal of the logic gate GN is supplied to one input terminal of the logic gate GO,
The output signal of the logic gate GM is supplied to the other input terminal. The first to fourth input terminals of the logic gate GN have byte write enable signal registers WR0 to WR0.
An output signal of WR3 is supplied. Further, the output signal er of the chip enable signal register ER and the output signal of the chip enable signal delay register ED are supplied to the first and second input terminals of the logic gate GM, respectively. An output enable signal OEB is supplied.

The output signal of the logic gate GN is selectively set to a high level by setting any of the output signals of the byte write enable signal registers WR0 to WR3 to a high level. The output signal of the logic gate GM is such that the output signal er of the chip enable signal register ER and the output signal of the chip enable signal delay register ED are both at a high level and the output enable signal OEB
Is selectively set to a high level by setting to a low level, and the output signal of the logic gate GO is selected by setting the output signal of the logic gate GN to a low level and the output signal of the logic gate GM to a high level. To a high level.

As a result, the sense amplifier S output from the selected 32 memory cells of the memory array MARY is output.
The read data rd0 to rd31 amplified by the corresponding unit circuit of A are taken into the data output buffer OB in response to the rising edge of the clock signal CLK.
In response to the high level of the output signal of the logic gate GO, it is output from the data input / output terminals D0 to D31 to an external access device.

FIG. 3 shows the synchronous SRAM of FIG.
A circuit diagram of one embodiment of the burst counter BC included in (SSRAM1) is shown. FIG. 4 shows FIG.
FIG. 5 shows a signal waveform diagram of one embodiment of the burst counter BC during the linear sequence, and FIG. 5 shows a signal waveform diagram of the embodiment during the interleave sequence. Based on these figures, the burst counter BC of this embodiment is
The specific configuration and operation of the device and its features will be described. In FIG. 3, the MOSFET with an arrow at its channel (back gate) portion is a P-channel type, and an N-channel MOSFET without an arrow is attached.
Are shown separately from

In FIG. 3, the burst counter BC is
n, that is, a predecoder PD receiving 2-bit address signals A0 to A1, and a 2nth power of this predecoder PD, that is, a 4-bit output signal, that is, a predecode signal / A
4 registers for receiving 0 / A1, A0 / A1, / A0A1 and A0A1, that is, a unit burst register UB
R0 to UBR3 and inverted output signals / φ / A0 / A of unit burst registers UBR0 to UBR3 corresponding to the inverted set input terminal / S or the inverted reset input terminal / R.
1, / φA0 / A1, / φ / A0A1, / φA0A1 and non-inverted output signals φ / A0 / A1, φA0 / A1,
A shift register composed of four flip-flops FF1 to FF4 receiving φ / A0A1 and φA0A1, respectively, and four carry selection circuits CS each composed of four logic gates GW, Ga to Gc to GZ, Gj to Gl.
1 to CS4.

Predecoder PD of burst counter BC
Includes four logic gates GP to GS. One of the input terminals of the logic gate GP is provided with an address signal A0.
Of the address signal A1 by the inverter V2 is supplied to the other input terminal. A non-inverted signal of the address signal A0 is supplied to one input terminal of the logic gate GQ, and an inverted signal of the address signal A1 is supplied to the other input terminal. Further, an inverted signal of the address signal A0 is supplied to one input terminal of the logic gate GR, and a non-inverted signal of the address signal A1 is supplied to the other input terminal. A non-inverted signal of the address signal A0 is supplied to one input terminal of the logic gate GS, and a non-inverted signal of the address signal A1 is supplied to the other input terminal.

As a result, the output signal of logic gate GP, that is, the predecode signal / A0 / A1 becomes the address signal A
When both 0 and A1 are set to low level, that is, logic "0", they are selectively set to high level. Also, the output signal of logic gate GQ, that is, predecode signal A0 / A1
Are selectively set to a high level when the address signal A0 is set to a high level, that is, logic "1", and the address signal A1 is set to logic "0". Further, the output signal of the logic gate GR, that is, the predecode signal / A0A1 is
When the address signal A0 is set to logic "0" and the address signal A1 is set to logic "1", the address signal is selectively set to a high level. The output signal of the logic gate GS, that is, the predecode signal A0A1 is selectively set to a high level by setting both the address signals A0 and A1 to logic "1".

Next, the unit burst registers UBR0 to UBR3 of the burst counter BC include a latch circuit having inverters V4 and V5 cross-coupled and a logic gate G.
Includes T and GU. The corresponding predecode signal / A0 / of the predecoder PD is applied to the input node of the latch circuit composed of the inverters V4 and V5 via the transfer gate TG which is selectively turned on in response to the low level of the internal clock signal BBC. A1, A0 / A1, / A0A
1 and A0A1 are supplied, respectively. The output signals of these latch circuits are supplied to one input terminal of the logic gate GU and to one input terminal of the logic gate GT via the inverter V6. The internal clock signal BBC is commonly supplied to the other input terminals of the logic gates GT and GU. The output signal of logic gate GT is the inverted output signal / φ of each unit burst register.
/ A0 / A1, / φA0 / A1, / φ / A0A1 and / φA0A1, and the output signal of the logic gate GU is
The non-inverted output signals φ / A0 / A1, φA0 / A1, φ
/ A0A1 and φA0A1.

Here, the internal clock signal BBC is shown in FIG.
As shown in FIG. 5, when the address status control signal ADSCB is at a low level, the address status control signal is at a high level in synchronization with the clock signal CLK. The predecode signals / A0 / A1, A0 / A1, / A0A1 and A0A1 are, as described above, the address signals A0 to A0.
It is alternatively set to a high level in accordance with a logical level of 1.
The logic levels of these predecode signals are transmitted to the latch circuit composed of the inverters V4 and V5 via the transfer gates TG of the unit burst registers UBR0 to UBR3 while the internal clock signal BBC is at the low level. Changes to the high level, the address signals A0 and A1, that is, the predecode signals / A0 / A1, A0 / A1, / A0A1, A0A
It is held without receiving a level change of 1, thereby stabilizing the operation of the burst counter BC.

Unit burst registers UBR0 to UBR3
The output signal of the latch circuit composed of the inverters V4 and V5 is selectively transmitted via the logic gate GT or GU while the internal clock signal BBC is at the high level, and in response to this, the inversion of each unit burst register is performed. Output signal / φ / A0 / A1, / φA0 / A1, / φ / A0A
1, / φA0A1 or φ / A0 / A1, φA0 / A
1, φ / A0A1 and φA0A1 are complementarily set to the low level.

That is, for example, when the predecode signal / A0 / A1 of the predecoder PD is alternatively set to the high level, the inverted output signal / φ / A0 / A1 of the unit burst register UBR0 is alternatively set to the low level. And inverted output signals / φA0 / A1, / φ / A0A1 and / φA0 of other unit burst registers UBR1 to UBR3.
A1 is all kept at a high level. At this time, the non-inverted output signal φ / A0 of the unit burst register UBR0
/ A1 is kept at the high level, and the non-inverted output signals φA of the other unit burst registers UBR1 to UBR3 are output.
0 / A1, φ / A0A1 and φA0A1 are both at low level.

On the other hand, the inversion set input terminals / S of the flip-flops FF1 to FF4 constituting the shift register are connected to the corresponding unit burst register UB as described above.
Inverted output signals of R0 to UBR3 / φ / A0 / A1, / φ
A0 / A1, / φ / A0A1 and / φA0A1 are supplied, respectively.
Corresponding non-inverted output signals φ / A0 / A1, φA0 / A
1, φ / A0A1 and φA0A1 are supplied, respectively. The internal clock signal CBC is commonly supplied to the clock input terminals of the flip-flops FF1 to FF4. Output signals of the logic gates Gc, Gf, Gi and Gl of the corresponding carry selection circuits CS1 to CS4, that is, carry signals, are commonly supplied to the data input terminals J and K of the flip-flops, respectively. The signal Q is the predecode signal / a0 / a1, a
0 / a1, / a0a1 and a0a1.

One input terminal of the logic gate GZ of the carry selection circuit CS1 corresponding to the flip-flop FF1 has a flip-flop FF4 which is a preceding stage in the forward shift.
Of the flip-flop FF1 is supplied to the other input terminal.
Q is supplied. One input terminal of the logic gate GW of the carry selection circuit CS2 corresponding to the flip-flop FF2 is supplied with the inverted output signal / Q of the preceding flip-flop FF1, and the other input terminal is connected to the corresponding flip-flop. The inverted output signal / Q of FF2 is supplied. Further, one input terminal of the logic gate GX of the carry selection circuit CS3 corresponding to the flip-flop FF3 is connected to the inverted output signal / of the preceding flip-flop FF2.
Q is supplied, and the other input terminal is supplied with the inverted output signal / Q of the corresponding flip-flop FF3.
Similarly, one input terminal of the logic gate GY of the carry selection circuit CS4 corresponding to the flip-flop FF4 has
The inverted output signal / Q of the preceding flip-flop FF3 is supplied, and the inverted input signal / Q of the corresponding flip-flop FF4 is supplied to the other input terminal.

The output signals of logic gates GZ, GW, GX and GY of carry signals CS1 to CS4 are supplied to corresponding input terminals of logic gates Gj, Ga, Gd and Gg, respectively. The logic gates Gh, Gk, Gb and Ge are supplied to one input terminal of the circuit. The output signal of the logic gate GV is commonly supplied to the other input terminals of the logic gates Gj, Ga, Gd and Gg of each unit burst register, and the other input terminals of the logic gates Gh, Gk, Gb and Ge are connected to the other input terminals. , The inverted signal of the inverter V7 is commonly supplied. The address signal A0 is supplied to one input terminal of the logic gate GV, and the mode control signal IMOD is supplied to the other input terminal. The output signals of the logic gates Gj and Gk, Ga and Gb, Gd and Ge, and Gg and Gh of the unit burst registers UBR0 to UBR3 are output from the corresponding logic gates Gc, Gf and G, respectively.
It is supplied to one and the other input terminals of i and Gl, respectively.

As a result, carry select circuits CS1-C
Carry signal output from S4, that is, logic gate G
The output signals of c, Gf, Gi and Gl receive the low level of the mode control signal IMOD, and the synchronous SRA
When M is set to the burst mode of the linear sequence,
Flip-flop FF4, FF1, FF2, FF of the preceding stage
3 or the corresponding flip-flops FF1 to FF4 are selectively set to high level on condition that they are set. Further, when the synchronous SRAM is set to the burst mode of the interleave sequence in response to the high level of the mode control signal IMOD, the flip-flops FF2, FF3, FF4, FF1 or the corresponding flip-flops FF1 to FF4 in the substantially subsequent stage are set to the set state. Level is selectively set high.

From these, synchronous SRAM
Is set to the burst mode of the linear sequence, four flip-flops FF1 forming the shift register
As shown in FIG. 4, for example, the flip-flop FF1 corresponding to the predecode signal / a0 / a1 enters the set state upon receiving the rise of the internal clock signal BBC, and the other predecode signals a0 / a
The flip-flops FF2 to FF4 corresponding to 1, / a0a1 and a0a1 are initialized so as to be reset. Each time the internal clock signal CBC is changed to the high level, the set state of each flip-flop shifts in the forward order in synchronization with the rising edge thereof,
Thereby, predecode signals / a0 / a1, a0 / a
1, / a0a1 and a0a1 are sequentially set to the high level in the normal order.

On the other hand, when the synchronous SRAM is set to the burst mode of the interleave sequence, the four flip-flops FF1 to FF
As shown in FIG. 5, for example, the flip-flop FF4 corresponding to the predecode signal a0a1 enters the set state upon receiving the rise of the internal clock signal BBC, and the other predecode signals / a0 / a1, a
The flip-flops FF1 to FF3 corresponding to 0 / a1 and / a0a1 are initialized so as to be in the reset state. Each time the internal clock signal CBC is changed to a high level, the set state of each flip-flop shifts in the reverse order in synchronization with the rising edge, whereby the predecode signals a0a1, / a0a1, a0
/ A1 and / a0 / a1 are sequentially set to the high level in the reverse order.

When the synchronous SRAM is set to the normal operation mode in which a single address is accessed, only the initial setting of the flip-flops FF1 to FF4 by the internal clock signal BBC is performed in the burst counter BC, and the internal clock signal CBC Does not perform the shift operation of the shift register. Therefore, the address signal A0
The predecode signals / a0 / a1, a0 / a1, / a0a1 and a0a1 corresponding to the column address specified by .about.A1 are alternatively set to high level only for a period corresponding to one cycle.

However, the synchronous SR of this embodiment
In the case of AM, as apparent from the above description, the predecode signal / a0 / a based on the address signals A0 to A1.
The signal path up to the formation of 1, a0 / a1, / a0a1 or a0a1 is the same regardless of the operation mode, and the transmission delay time difference between the operation modes of the column address signal is extremely small. When attention is paid to the delay time from the clock signal CLK, since the predecoder PD is located before the flip-flops FF1 to FF4 that operate synchronously in accordance with the internal clock signal CBC, the address signal A
The decoding time of 0 to A1 becomes invisible, and it is possible to prevent the occurrence of hazards for the predecode signals / a0 / a1, a0 / a1, / a0a1, and a0a1. As a result, the operation of the synchronous SRAM can be stabilized and the burst counter B
The timing control of C becomes easy, and thereby the access time of the synchronous SRAM can be shortened. Further, in response to the shortened access time of the synchronous SRAM, the operation of the cache memory CACH including the synchronous SRAM as a data memory is accelerated, and the machine cycle of the personal computer including the cache memory CACH is accelerated.

The functions and effects obtained from the above embodiments are as follows. (1) In a synchronous SRAM or the like having a burst mode and having a burst counter for autonomously specifying a lower-order n-bit column address, for example, the burst counter is set to 2 based on the n-bit column address. A predecoder for selectively forming an n-bit predecode signal and a shift register composed of 2 n flip-flops selectively set or reset in accordance with the corresponding predecode signal. In addition to the configuration, the shift operation of the shift register is selectively performed in the normal order or the reverse order according to whether the burst mode is a linear or interleaved sequence, so that the burst counter operates in the normal operation mode and the burst mode. Compression of column address signal transmission delay time difference The effect that can be obtained is obtained.

(2) In the above item (1), the burst counter is provided with a register for pulsing a set signal or a reset signal for each flip-flop of the shift register, thereby eliminating the effect of a level change due to an intermediate address signal. Thus, the operation of the burst counter can be stabilized. (3) According to the above items (1) and (2), an effect is obtained that the delay time of the predecode signal formed by the burst counter with respect to the clock signal can be reduced and the occurrence of the hazard can be prevented. (4) According to the above items (1) to (3), the effect is obtained that the operation of the burst counter can be easily controlled while the operation thereof is stabilized, and the access time of the synchronous SRAM including the burst counter can be shortened. . (5) According to the above items (1) to (4), the synchronous S
The effect is obtained that the operation of a cache memory or the like including a data memory composed of a RAM can be accelerated, and the machine cycle of a personal computer or the like including the same can be accelerated.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the data memory of the cache memory CACH can include an arbitrary number of synchronous SRAMs, and its block configuration and bus configuration can employ various embodiments. In FIG. 2, a memory array MARY of a synchronous SRAM can be divided into an arbitrary number of memory mats including its direct peripheral circuits. In addition, a synchronous SRAM is, for example, × 16 bits or × 64 bits.
An arbitrary bit configuration such as a bit can be adopted, and the address configuration is also arbitrary. Furthermore, various embodiments can be adopted for the block configuration of the synchronous SRAM, the names and effective levels of the start control signal and each internal signal, the combination thereof, and the like.

In FIG. 3, the number of bits of the burst counter BC, that is, the number of bits of the address signal to be automatically switched in the burst mode can be arbitrarily set.
The bit position is also arbitrary. Further, the predecoder PD of the burst counter BC and the unit burst register UBR
0 to UBR3 and carry selection circuits CS1 to CS4
Is not limited by this embodiment. 4 and 5, the absolute level and timing relationship of each clock signal, internal clock signal, address signal, predecode signal, and the like do not limit the present invention.

In the above description, mainly the case where the invention made by the present inventor is applied to a synchronous SRAM constituting a cache memory of a personal computer, which is a background of application,
The present invention is not limited to this, and can be applied to various semiconductor memories and logic integrated circuit devices such as a synchronous DRAM (dynamic RAM) including a similar burst counter, and various digital devices including the same. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor device having at least a counter and an apparatus or a system including the same.

[0057]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous SRAM or the like having a burst mode and having, for example, a burst counter for autonomously specifying a lower-order n-bit column address, the burst counter is set to 2 n bits based on the n-bit column address. And a predecoder for selectively forming a predecode signal, and selectively set or reset according to a corresponding predecode signal.
And a shift register comprising n flip-flops, and the shift operation of the shift register is selectively performed in a forward or reverse order according to whether the burst mode is a linear or interleaved sequence. By doing so, the difference in transmission delay time of the column address signal between the normal operation mode and the burst mode of the burst counter such as the synchronous SRAM can be compressed, so that the operation is stabilized and the timing control of the burst counter is performed. Therefore, the access time of a synchronous SRAM or the like including a burst counter can be shortened. As a result, the synchronous SRAM
The operation of a cache memory or the like including the data memory as a data memory can be accelerated, and the machine cycle of a personal computer or the like including the cache memory can be accelerated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a cache memory including a synchronous SRAM to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of a synchronous SRAM constituting the cache memory of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a burst counter included in the synchronous SRAM of FIG. 2;

FIG. 4 is a signal waveform diagram showing one embodiment of the burst counter shown in FIG. 3 during a linear sequence.

5 is a signal waveform diagram showing one embodiment of an interleave sequence of the burst counter of FIG. 3;

FIG. 6 is a partial circuit diagram showing an example of a synchronous SRAM burst counter developed by the present inventors prior to the present invention and an example of a peripheral portion thereof;

[Explanation of symbols]

CPU: Central processing unit, CG: Clock generation circuit,
CACH: Cache memory, CCTL: Cache memory control circuit, TAGM: Tag memory, SSRA
M: Synchronous SRAM. MARY: Memory array, AD: Address decoder, WD0 to WD3: Write driver, SA: Sense amplifier, AR, AR0
AR1 ... address register, BC ... burst counter, WR0 to WR3 ... byte write enable signal register, ER ... chip enable signal register, ED
…… chip enable signal delay register, IB …… data input buffer, OB …… data output buffer, ADV
B: Address advance signal or its input terminal, CL
K: clock signal or its input terminal, A0 to A14
... Address or its input terminal, ADSCB ... Address status control signal or its input terminal, GWB ... Global write enable signal or its input terminal, BWE
B, BW0B to BW3B... Byte write enable signal or input terminal thereof, CE1, CE2, CE2B... Chip enable signal or input terminal thereof, ADSPB.
Address status processing signal or its input terminal, IMO
D: Mode control signal or its input terminal, OEB ... Output enable signal or its input terminal, D0 to D31 ...
Input data or output data or their input / output terminals. P
D: Predecoder, UBR0 to UBR3 ... Unit burst register, FF1 to FF4 ... Flip-flop,
CS1 to CS4 ... carry selection circuit. G1 to Gp ...
Logic gates, V1 to V7, inverters, TGs, transfer gates, EO1 to EO4, exclusive OR circuits.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Sadayuki Morita 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Nichi-cho SLS Engineering Co., Ltd. (72) Inventor Eiichi Nishimura Tokyo 5-20-1, Josui Honcho, Kodaira-shi Nippon Cho LSI Engineering Co., Ltd. (72) Inventor Hirofumi Kuriko 5-20-1, Josui Honcho, Kodaira-shi, Tokyo Nichicho Cho LS・ I-Engineering Co., Ltd. (72) Inventor Takahiro Sonoda 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Nichi-Cho LSI Engineering Co., Ltd. (72) Inventor Atsushi Hiraishi, Kodaira, Tokyo 5-2-1, Honcho, Josui, Ichimizu Semiconductor Company, Hitachi, Ltd. (72) Toshio Waku, Inventor Josui, Kodaira, Tokyo Town 5-chome No. 20 No. 1 Date standing ultra-El es Eye Engineering within Co., Ltd. (72) inventor Shuji Yahata Tokyo Kodaira Josuihon-cho, Chome No. 20 No. 1 Co., Ltd. Hitachi semiconductor business unit

Claims (5)

[Claims] 1. An n-bit digital input signal based on 2
And a shift register including 2 n flip-flops selectively set or reset according to the corresponding predecode signal. A semiconductor device comprising a counter. 2. The semiconductor device according to claim 1, wherein the shift register has a first operation mode in which the shift operation is performed in a forward order and a second operation mode in which the shift operation is performed in a reverse order. . 3. The flip-flop according to claim 1, wherein the flip-flop constituting the shift register is selectively set or reset according to a first internal clock signal and selected according to a second internal clock signal. The shift operation is performed, wherein the counter captures the predecode signal in accordance with the first internal clock signal, and pulsates the register into 2 n registers. 2. A semiconductor device comprising: 2 n carry selection circuits for selectively forming a carry signal in accordance with an output signal of a preceding or succeeding flip-flop. 4. The synchronous semiconductor device according to claim 1, wherein said semiconductor device has a burst mode of a linear sequence and an interleave sequence.
A RAM, wherein the counter is a burst counter of the synchronous SRAM, wherein the digital input signal is a predetermined bit of a column address signal, and wherein the first operation mode corresponds to the burst mode of the linear sequence. The second operation mode corresponds to the burst mode of the interleave sequence. 5. The semiconductor device according to claim 4, wherein said synchronous SRAM forms a data memory of a cache memory of a personal computer.