JPH1028375A - Switching power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching power supply, capable of reducing switching loss by resonance operation and of protecting a switching element, even if a load is short-circuited. SOLUTION: An FET 4, as a switching element, is connected to a DC power supply 1 via the primary windings 3 of the transformer 2. A resonance capacitor 32 is connected in parallel to the FET 4. This capacitor 32 can be replaced with the stray capacitance of the FET 4. To generate pulses for switching on/off the FET 4, first, second and third comparators 34, 46, 42, a capacitor 35 for generating saw-tooth wave and discharging resistors 36, 48 are provided. The discharging time constant of the capacitor 35 for generating saw-tooth wave is reduced under the normal operation of a load but is increased if the load is short-circuited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quasi-resonant switching power supply.

[0002]

2. Description of the Related Art A conventional quasi-resonant type switching power supply for reducing switching loss is shown in FIGS.
It is configured as shown in FIG. In FIG. 1, for example, a primary winding 3 having an inductance of a transformer 2, a FET 4 as a switching element, and a current as a current detecting means are provided between one end and the other end of a DC power supply 1 composed of a rectifier circuit and a smoothing circuit. A series circuit with the detection resistor 5 is connected. FET 4 is an insulated gate (MOS) field effect transistor whose source is connected to the substrate,
Built-in diode between drain and source. An output smoothing capacitor 8 is connected in parallel to a secondary winding 6 of the transformer 2 via an output rectifier diode 7.
The polarity of the secondary winding 6 and the polarity of the rectifier diode 7 are FE
It is determined that the rectifier diode 7 conducts during the off period of T4. A load 11 is connected to DC output terminals 9 and 10 connected to the smoothing capacitor 8. A voltage control signal forming circuit 12 for controlling the output voltage at a constant voltage is connected between the DC output terminals 9 and 10. The voltage control signal forming circuit 12 includes voltage detecting resistors 13 and 14 connected between the DC output terminals 9 and 10, a resistor 15 and a Zener diode 16 for forming a reference voltage source, and a transistor 17 as an error amplifier. Consisting of The base of the transistor 17 is connected to a voltage dividing point of the voltage detection resistors 13 and 14, and the emitter is connected to a Zener diode 16 as a reference voltage source. Zener diode 1
6 is connected between the DC output terminals 9 and 10 via the resistor 15. Therefore, the collector current of the transistor 17 changes according to the difference between the detection voltage and the reference voltage. A light emitting diode 18 is connected as a light emitting element between the DC output terminal 9 and the collector of the transistor 17 in order to convert the output of the voltage control signal forming circuit 12 into an optical signal.

A tertiary winding 19 is provided on the transformer 2 to constitute a winding voltage detecting means and a control power supply of the transformer 2. One end of the tertiary winding 19 is connected to a winding voltage detection circuit including a resistor 20 and a rectifier diode 21. A smoothing capacitor 23 is connected as a control power supply via a rectifier diode 22 in parallel with the tertiary winding 19.

A positive power supply line 25 of a control pulse forming circuit 24 for controlling on / off of the FET 4 is connected to one end of a capacitor 23 as a control power supply and is connected to one end of the DC power supply 1 via a starting resistor 26. The ground line 27 is connected to the other end of the DC power supply 1 and the capacitor 2.
3 is connected to the other end. A composite signal of a current detection signal, a winding voltage detection signal, and a constant voltage control signal is input to an input signal line 28 of the control pulse forming circuit 24. In order to form this composite signal, one end of the current detection resistor 5 is connected to the resistor 2
9, one end of a tertiary winding 19 is connected to the input signal line 28 via a resistor 20 and a diode 21.
The phototransistor 30 is connected between the input signal line 28 and one end of the phototransistor 30. Phototransistor 30 is optically coupled to light emitting diode 18. The above-described interconnection of the current detection resistor 5, the tertiary winding 19, and the phototransistor 30 constitutes an addition circuit. The control pulse forming circuit 24 forms a control pulse in response to the input signal line 28 and outputs F
A control pulse is given to the gate of ET4.

In order to generate a quasi-resonance or a partial resonance when the FET 4 is turned off and when it is turned on, the FET 4
4 and the current detecting resistor 5 in parallel with the resonance capacitor 3
2 are connected. Note that, instead of the individual capacitor 32, a stray capacitance (stray capacitance) between the drain and the source of the FET 4 can be used.

FIG. 2 shows only the primary side of a switching power supply including a control pulse forming circuit 24 shown in detail.
The control pulse forming circuit 24 includes a reference voltage source 33, a pulse control comparator 34, and a sawtooth wave generating capacitor 35.
, A discharge resistor 36, a charge control transistor 37,
Diode 38, reference voltage source 39 and base resistor 40
A transistor 41 as charge control and pulse control means, a comparator 42 for control pulse formation, a resistor 43 and a diode 44 for charge control and feedback, and a drive circuit 45
Consisting of One input terminal of the comparator 34 is connected to the input signal line 28, and the other input terminal is connected to the reference voltage source 33.
, And the output terminal is connected to the base of the transistor 41. One end of the saw-wave generating capacitor 35 is connected to the positive power supply line 25 via the charge control transistor 37 and the diode 38, and the other end of the capacitor 35 is connected to the ground line 27. The discharging resistor 36 is connected in parallel with the capacitor 35. The voltage source 39 is connected to the base of the transistor 37 via the resistor 40. The collector of the charge control and output pulse control transistor 41 is connected to the output terminal of the comparator 42, and the emitter is connected to the ground line 27.
One input terminal (positive terminal) of the control pulse forming comparator 42 is connected to the voltage source 39 via the resistor 40,
The other input terminal (negative terminal) is connected to one end of the capacitor 35, and the output terminal is connected to the gate of the FET 31 via the drive circuit 45. The feedback resistor 43 and the diode 44 are connected between one input terminal and the output terminal of the comparator 42.

Next, the operation of the switching power supply device shown in FIGS. 1 and 2 will be described with reference to the waveform diagrams of FIGS. FIG. 3 is a waveform diagram schematically showing the state of each part in FIGS. 1 and 2. When the control pulse shown in FIG. 3B is applied to the FET 4 at time t0, the FET 4 is turned on, and the current I1 is supplied to the closed circuit including the DC power supply 1, the primary winding 3, the FET 4, and the current detecting resistor 5. Flows. Since the primary winding 3 has an inductance, the current I1 increases with a slope as shown in FIG. 3C, and a voltage waveform corresponding to the waveform of the current I1 is obtained from the current detection resistor 5. Since the polarity of the tertiary winding 19 is set so that a downward voltage is generated during the on-period of the FET 4, the diode 21 becomes non-conductive during the on-period, and the winding voltage added to the current detection waveform. Is zero. Assuming that the resistance value of the phototransistor 30 is constant for a short period of time, the voltage Vin of the input signal line 28 of the comparator 34 has a constant slope and has a constant slope at t in FIG.
It gradually increases as shown in the section from 0 to t1. FE
In the ON period t0 to t1 of T4, the transistor 3
7 and the diode 38 conduct to form a charging circuit.
Since no special resistor is connected to this charging circuit,
The capacitor 35 is charged rapidly, for example, to 6.5V. That is, if the voltage Vr of the voltage source 39 is 7.8 V,
From now on, the base-emitter voltage V of the transistor 37
Subtracting the sum of _BE and the forward voltage Vf of diode 38 results in about 6.5V. Since the difference between the two input voltages V1 and V2 of the comparator 42 during the ON period t0 to t1 is about 1.5 V, malfunction of the comparator 42 due to noise can be sufficiently prevented. Thereafter, when the input voltage Vin of the comparator 34 reaches the reference voltage Vth1 provided by the reference voltage source 33, the output of the comparator 34 changes from a low level to a high level, and the transistor 41 is turned on. Transistor 41
Is turned on, the collector voltage, that is, the voltage of the output of the comparator 42 becomes low level, and the diode 44 conducts.
Since the voltage V1 at the positive input terminal of the comparator 42 drops from 6.5V to 3.5V as shown in FIG. 3 (A) and becomes lower than the voltage V2 at the negative input terminal of the comparator 42, Is kept low from the time t1, as shown in FIG. 3B, and the FET 4 is turned off. As a result,
The current I1 of the FET 4 also becomes zero as shown in FIG. Since the transistor 41 is turned on and the diode 44 is conducting while the output of the comparator 42 is at a low level, the voltage V1 at the positive input terminal of the comparator 42 is V1 = ｛(Vr-Vf) (R2 ) / (R2 + R3) + V
It is determined by f and becomes constant at about 3.5V. In the above equation, Vr is the voltage of the voltage source 39, Vf is the diode 38,
44 is the forward voltage, R2 is the value of the resistor 43, R3 is the resistor 4
It is a value of 0. The transistor 41 is turned on, and the voltage V
When 1 drops to 3.5 V, the charging transistor 37 and the diode 38 become non-conductive, and the electric charge of the saw-tooth wave generating capacitor 35 is discharged via the resistor 36.
Now, let the capacitance of the capacitor 35 be C1 and the value of the resistor 36 be R1
As a result, the capacitor 35 discharges at the discharge time constant of C1 R1, and the voltage of the capacitor 35, that is, the voltage V2 of the negative terminal of the comparator 42 is reduced from 5 V to about 3.
It drops to 5V. FIG. 3 shows the voltage V2 of the capacitor 35.
In (A), when the voltage is slightly lower than the voltage V1 indicated by the dotted line, the transistor 39 and the diode 38 conduct, and a charging current flows through the capacitor 35. As a result, both charging and discharging of the capacitor 35 occur, and the voltage V2
Is kept slightly lower than the voltage V1. t0 to t1
During the ON period of the FET 4, the output rectifier diode 7 is off, so that magnetic energy is accumulated in the transformer 2. When the FET 4 is turned off at t1, the discharge of the stored energy of the transformer 2 starts, an upward voltage is generated in the secondary winding 6, and the output rectifier diode 7 is turned on.
A current flows from the secondary winding 6 to the smoothing capacitor 8 and the load 11. During the off period of the FET 4, an upward voltage is generated in the tertiary winding 19 in the same manner as the secondary winding 6, and this voltage is generated by the resistor 20.
And the input voltage Vin of the comparator 34 via the diode 21. That is, as shown in FIG.
The voltage V19 of the next winding 19 has an opposite polarity to the voltage in the section from t0 to t1 and has a higher value than the reference voltage Vth1, and is input to the comparator 34. Accordingly, the output of the comparator 34 during the off period t1 to t2 becomes high, the collector voltage of the transistor 41, that is, the output voltage of the comparator 42 becomes low, and since the diode 44 conducts, the output of the comparator 42 becomes high. The voltage V1 at the positive input terminal is maintained at a relatively low value of 3.5 V as shown in FIG. As a result, the off period t1 to
At t2, the output of the comparator 42 is kept at a low level as shown in FIG. 3B, and the FET 4 is kept off.

When the discharge of the stored energy in the transformer 2 is completed, the primary, secondary and tertiary windings 3, 6, 19 are lowered. However, because of the presence of the resonance capacitor 32, resonance occurs due to the capacitance of the capacitor 32 and the inductance of the primary winding 3, and the resonance capacitor 32 and the primary winding 3
A resonance current flows in a closed circuit between the power supply 1 and the power supply 1. This resonance current is the discharge current of the capacitor 32, and the voltage of the capacitor 32 and the drain-source voltage Vds of the FET 4 are shown in FIG.
As shown in (A), the voltage decreases substantially with a sine wave (waveform in a 90 to 270 degree section). The drain-source voltage Vds of the FET 4 during the off period before t0 in FIG. 4 is the sum of the voltage of the power supply 1 and the voltage of the primary winding 3. When a resonance current flows through the primary winding 3, a voltage is induced in the tertiary winding 19 based on the resonance current. Therefore, the voltage V19 of the tertiary winding 19 immediately changes to a value of the opposite polarity at time t0 in FIG. Without it, it falls with a slope. As shown in FIG. 4B, when the reference voltage Vth1 crosses at the time point t1, the output of the comparator 34 changes from the high level to the low level, and the base current of the transistor 41 decreases and the collector voltage of the transistor 41 increases. Comparator 4
2 changes from low level to high level and the feedback diode 44 is turned off, so that the voltage V1 at the positive input terminal of the comparator 42 becomes high level, and the high level output of the comparator 42 is held. , A gate control pulse is generated as shown in FIG. Note that the voltage V19 of the tertiary winding 19 and the voltage of the input signal line 28 are equal to the reference voltage Vth1
, The gate-source voltage Vgs is changed from the low level to the high level at t2, which is a time Td later than t1, due to the delay inherent in the comparator 34, the transistor 41, and the drive circuit 45. The sum of the delay time Td and the time from t0 to t1 in FIG. 4 is equal to the drain-source voltage Vds
Is substantially equal to the required time from the start of the decrease due to the resonance to the zero or almost zero. At the time of resonance, the drain-source voltage Vds oscillates around the voltage of the power supply 1. It substantially coincides with the time required for the drain-source voltage Vds to start decreasing by resonance and become zero or almost zero. If the gate-source voltage Vgs is changed to a high level when the drain-source voltage Vds is zero, the loss reduction by the zero volt switch can be maximized, but the drain-source voltage Vds starts to decrease. Even if the FET 4 is turned on at an arbitrary point in time, the switching loss can be reduced by an amount corresponding to the decrease in the drain-source voltage Vds. Incidentally, an individual delay circuit can be provided between the comparator 34 and the gate of the FET 4 in order to obtain the delay time Td. Further, the comparator 34 is provided with hysteresis, and the time at which the output of the comparator 34 changes from the high level to the low level can be delayed from t1 in FIG. 4 by this hysteresis effect. Zero volt switching at the time of turning off FET4 is performed by the capacitor 3
2 caused by charging. That is, when the FET 4 is turned off, the drain-source voltage Vds increases. However, since the capacitor 32 is connected in parallel with the FET 4,
As the capacitor 32 is charged, this voltage and the drain-source voltage Vds gradually increase, and zero volt switching is achieved.

During the on-period of the FET 4 shown in the section from t0 to t1 and the section from t2 to t3 in FIG. 3, the voltage V1 at the collector of the transistor 41 becomes 6.5 V, so that the base current of the charging transistor 37 increases. , The sawtooth wave generating capacitor 35 is rapidly charged, and the voltage V2
Becomes about 5V.

Next, the constant voltage control will be described. For example, when the output voltage Vout between the output terminals 9 and 10 becomes higher than a desired value, the light output level of the light emitting diode 18 becomes higher and the resistance value of the phototransistor 30 becomes smaller. As a result, the voltage Vin of the input signal line 28 of the comparator 34 becomes relatively high, and the time width from the time when the FET 4 is turned on to the time when the input voltage Vin crosses the reference voltage Vth1 is shortened. The pulse width becomes narrower, and the output voltage Vout returns to the desired value. When the output voltage Vout becomes lower than the desired value, the operation is reversed.

In the conventional switching power supply device shown in FIGS. 1 and 2, when the load 11 is short-circuited or the like and the output voltage Vout decreases, the operation will be performed after t4 in FIG. That is, when the output voltage Vout decreases as shown after t4 in FIG. 3G, the voltage of the smoothing capacitor 8 naturally decreases. During the off period of the FET 4, the voltage of the smoothing capacitor 8 is applied to the secondary winding 6 because the rectifier diode 7 is conducting, and the voltage V19 of the tertiary winding 19 changes in accordance with the output voltage Vout. However, as shown after the time t4 in FIG. Further, the drain-source voltage Vds during the off period is also equal to t4 in FIG.
It decreases as shown after the time point. As a result, the tertiary winding V19 detected via the resistor 20 and the diode 21 in FIG. 2 becomes equal to or lower than the reference voltage Vth1, and the end point of the off period of the FET 4 cannot be determined by the comparator 34. The end point of the OFF period is determined depending on the discharge time constants C1 and R1 of the capacitor 35 and the resistor 36. That is, when the output of the comparator 34 goes high at time t6 in FIG. 3 and the transistor 41 is turned on, the output of the comparator 42 is turned low and the diode 44 is turned on. As a result, the voltage V1 at the positive input terminal of the comparator 42 becomes equal to that shown in FIG.
As shown in the figure, the off period from t6 to t7 is maintained at approximately 3.5V. Since V2> V1 during the off period t6 to t7, the transistor 37 is non-conductive and the capacitor 35
Has stopped charging. As a result, during the period from t6 to t7, the voltage V1 decreases with a slope as shown in FIG. 3A due to the discharge of the capacitor 35, and crosses the voltage V1 at t7.
The output of comparator 42 goes high. As a result, t
From 7 the FET4 is turned off.

[0012]

By the way, in the conventional switching power supply shown in FIGS. 1 and 2, t4 in FIG.
When the output voltage Vout decreases due to a load short circuit or the like described below, the turning-off end point is not determined depending on the winding voltage V19, but is determined by the voltage V2 of the capacitor 35. The voltage V2 of the capacitor 35 is a relatively small discharge time constant C1.
, R1 so that the on / off frequency of the FET 4 becomes higher, for example, 300 kHz. As a result, a response delay occurs in the oscillation control circuits such as the comparators 34 and 42 and the transistor 41 for detecting the current I1 to determine the ON time width of the FET 4, the ON period is prolonged, an overcurrent flows, and F
ET4 could be destroyed. The capacitor 35
The discharge time constants C1 and R1 cannot be made longer than the discharge period of the stored energy of the transformer 2 during the off period of the FET 4 in order to obtain the effect of the pseudo resonance during the normal operation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a switching power supply capable of preventing the switching element from being destroyed.

[0014]

To achieve the above object, the present invention provides a series circuit comprising a primary winding of a transformer connected between one end and the other end of a DC power supply, and a switching element; A rectifier diode connected to the secondary winding of the transformer so as to be conductive during a period in which the switching element is off, and an output smoothing diode connected in parallel to the secondary winding via the rectifier diode. A capacitor, a pseudo-resonance capacitor or stray capacitance connected in parallel to the switching element, and a current flowing through the switching element is detected, and a current detection voltage having a value corresponding to the value of the current is obtained. Voltage detection means for obtaining a signal indicating the voltage of the primary winding, the secondary winding, or the tertiary winding of the transformer; An addition circuit for adding the current detection voltage and the winding voltage obtained from the winding voltage detection means, a sawtooth wave generation capacitor for generating a sawtooth wave, a DC power supply and the sawtooth wave generation capacitor And a charge control transistor connected between
A first reference voltage source for generating a reference voltage, a first comparator for generating a comparison output between the addition voltage obtained from the addition circuit and the first reference voltage, and a first reference voltage A second reference voltage source for generating a second reference voltage higher than the second reference voltage;
A second comparator for comparing the reference voltage with a reference voltage, a third reference voltage source connected to the base of the charge control transistor via a first resistor, and an ON period of the switching element. Forming a pulse, one input terminal of which is connected to the base of the charge control transistor;
A third comparator having the other input terminal connected to the sawtooth wave generating capacitor, and a third resistor connected between the one input terminal and the output terminal of the third comparator via a second resistor. Responsive to an output of the first comparator connected between the output diode and the output terminal of the third comparator and ground and indicating that the summed voltage is higher than the first reference voltage. A control switch that is turned on in response to an output of the first comparator indicating that the added voltage is lower than the first reference voltage, and a capacitor for generating a sawtooth wave. And forming a circuit of a first discharge time constant in response to an output of the second comparator indicating that the added voltage is higher than the second reference voltage, The added voltage is lower than the second reference voltage And a discharge circuit for forming a circuit having a second discharge time constant larger than the first discharge time constant in response to the output of the second comparator shown in FIG. It concerns the device. Further, as shown in claim 2, three input terminals are provided in the third comparator, and one of the input terminals can be controlled by the output of the second comparator. 7 and FIG.
Explaining the correspondence with the embodiment shown in FIG.
The third and fourth resistors are resistors 40, 55, 43 and 54, the first logic gate circuit is a NOT circuit 51 and an AND gate 52, and the second logic gate circuit is shared. A NOT circuit 51 and a NAND gate 53 are provided, a third logic gate circuit is a NOT circuit 57 and an AND gate 58, and first and second comparison input level switching switches are transistors. The reference voltage control switch is a transistor 59. Preferably, a tertiary winding is provided on the transformer, and this tertiary winding is used for detecting the winding voltage, used as a control power supply, and provided with output voltage control means. .

[0015]

According to the present invention, when the winding voltage of the transformer decreases due to a load short circuit or the like, the on / off frequency of the switching element decreases. This can prevent the switching element from being destroyed due to overcurrent.

[0016]

First Embodiment Next, a quasi-resonant switching power supply according to a first embodiment will be described with reference to FIGS. However, in FIG. 5, substantially the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 5 shows one of the transformers 2 of the switching power supply including the control pulse forming circuit 24a according to the present embodiment.
The next side is shown. The secondary side of the transformer 2 has the same configuration as that of FIG. In the switching power supply device of FIG. 5, a comparator 46 is newly added to the control pulse forming circuit 24a.
The configuration is the same as that of the circuit of FIG. 2 except that a reference voltage source 47 and a discharge resistor 48 are provided. However, the resistor 36 in FIG. 5 has a larger resistance value than the resistor 36 indicated by the same reference numeral in FIG. Further, two resistors 3 connected in parallel with each other in FIG.
The combined resistance value of 6 and 48 has substantially the same value as the resistance 36 of FIG. In addition, the correspondence between each part of FIG. 5 and the invention of each claim is shown.
Is a second comparator, comparator 42 is a third comparator, reference voltage source 33 is a first reference voltage source, reference voltage source 47 is a second reference voltage source, resistors 36 and 48 are discharge circuits, reference Voltage source 39
Is a third reference voltage source, and the resistors 40 and 43 are first and second resistors.

The positive input terminal of the second comparator 46 is connected to a second reference voltage source 47 for generating a second reference voltage Vth2 higher than the first reference voltage Vth1 of the first reference voltage source 33. , This negative input terminal is the line 28 from which the addition output is obtained.
, And this output terminal is connected to one end of the capacitor 35 via the second discharging resistor 48.

FIG. 6 shows the state of each part in FIG. 5 similarly to FIG. The state of each unit during normal operation before t4 in FIG. 6 is the same as the state of each unit during normal operation before t4 in FIG. ON period t0 to t1 during normal operation
, The voltage Vin at the negative input terminal of the second comparator 46 is lower than the second reference voltage Vth2.
Is at a high level, and the second discharge resistor 48 is substantially disconnected. In the ON period t1 to t2, as is apparent from FIG.
Is higher than the reference voltage Vth2 of the second comparator 4
The output of 6 becomes a voltage (ground) lower than the voltage of the capacitor 35, and the second discharging resistor 48 is connected in parallel with the first discharging resistor 36. If the resistance values of the first and second discharge resistors 36 and 48 are Ra and Rb, the combined resistance R
Is RaRb / (Ra + Rb), which is smaller than the value Ra of the first discharge resistor 36. Therefore, during the off period during normal operation, the voltage V2 of the capacitor 35 decreases with a short time constant as in FIG. Therefore, the capacitor 3
The voltage of 5 does not disturb the quasi-resonant operation. That is,
During normal operation, the end of the off period is not determined by the discharge of the capacitor 35, but is determined by the decrease in the voltage V19 of the tertiary winding 19.

A load short circuit occurs in the power supply device of FIG.
When the output voltage Vout decreases as shown after t4 in FIG. 6 (G), the input voltage Vin on the line 28 also decreases, and does not cross the second reference voltage Vth2. Therefore, when the load is short-circuited, the output of the second comparator 46 is always at a high level, and the second discharging resistor 48 is disconnected.
As a result, only the first discharging resistor 36 having a relatively large resistance value Ra is connected to the capacitor 35, the discharging time constants C1 and Ra are increased, and the voltage V2 of the capacitor 35 is reduced as shown in FIG. It decreases slowly as shown in A). When the output voltage Vout is decreasing, the OFF period is not ended in synchronization with the end of the release of the stored energy of the transformer 2 and is determined depending on the voltage V2 of the capacitor 35. Therefore, the on / off frequency of the FET 4 when the load is short-circuited is, for example, 20 kHz lower than the normal state, and the off-period becomes long, so that the response delay by the comparator 34 is small and the FET 4 can be prevented from being destroyed by overcurrent. .

As is apparent from the above description, according to the present embodiment, it is possible to reliably and easily achieve protection of the FET 4 when the output voltage drops due to a load short circuit or the like, while ensuring the effect of reducing the switching loss due to the resonance operation. it can.

[0022]

Second Embodiment Next, a switching power supply according to a second embodiment will be described with reference to FIGS. However, FIG.
In FIG. 8 and FIG. 8, substantially the same parts as those in FIG. 1, FIG. 2, FIG. 5, and FIG. The switching power supply device of the second embodiment has the same configuration as that of the first embodiment except that it has a control pulse forming circuit 24b obtained by modifying the control pulse forming circuit 24a of the first embodiment. Therefore, FIG. 7 shows the control pulse forming circuit 24b.
Only shown. The control pulse forming circuit 24b of FIG.
Is the transistor 41 and the second discharging resistor 48 from FIG.
And instead of the first transistor 50, the first N
OT circuit (inverter) 51, first AND gate 5
2, a NAND gate 53, resistors 54 and 55, second and third NOT circuits 56 and 57, a second AND gate 58,
The second and third transistors 59 and 63 are added, and the third comparator 42a is connected to three input terminals 60, 61 and 62.
The control pulse forming circuit 24 shown in FIG.
It has the same configuration as a.

Next, the deformed portion will be described in detail.
One input terminal of the first AND gate 52 is connected to the output terminal of the third comparator 42a, and the other input terminal is connected to the first input terminal.
Is connected to the output terminal of the first comparator 34 via the NOT circuit 51. One input terminal of the NAND gate 53 is connected to the first NOT circuit 51, the other input terminal is connected to the output terminal of the third comparator 42a, and this output terminal is connected to the first transistor 50. Connected to the base. The emitter of the transistor 50 is connected to the ground line 27, and the collector is connected to the positive input terminal 60 of the third comparator 42a via the resistor 54. The third comparator 42a has a first input terminal 60 in addition to the first input terminal 60.
, And a second negative input terminal 62.
The positive input terminal 60 is connected to the third reference voltage source 3
9 and the first negative input terminal 61 is connected to the sawtooth wave generating capacitor 35 as in FIG. The newly provided second negative input terminal 62 is connected to the ground line 27 via the third transistor 63.
The base of the third transistor 63 is the second NOT circuit 5
6 is connected to the output terminal of the second comparator 46.

To control the voltage at the positive input terminal of the second comparator 46, a second transistor 59 is connected as a control switch in parallel with the second reference voltage source 47. The base of the second transistor 59 is connected to the second AND gate 58. One input terminal of the second AND gate 58 is connected to the output terminal of the first comparator 34, and the other input terminal is connected to the output terminal of the second comparator 46 via the second NOT circuit 57. Have been. The lines 25, 27, 28 and 31 in FIG. 7 are the same as those indicated by the same reference numerals in FIG. 2, and are connected in the same manner as in FIG.

Next, the operation of the control pulse forming circuit 24b of FIG. 7 will be described with reference to FIG. The relationship between the input voltage Vin to the first and second comparators 34 and 46 in FIG. 7 and the first and second reference voltages Vth1 and Vth2 is shown in FIG.
And is the same as FIG. 6F of the first embodiment. During the period from t0 to t1 during normal operation, the two inputs of the first comparator 34 have a relationship of Vth1> Vin, so this output goes low, the output of the NOT circuit 51 goes high, and the first AND gate 52 of the third comparator 4
A state where the output pulse of 2a can pass is obtained. This t
Since both inputs of the NAND gate 53 are at the high level during the interval from 0 to t1, this output is at the low level, the first transistor 50 is kept off, and the positive input terminal 60 of the third comparator 42a is The voltage V1 is kept relatively high, for example, 6.5V. In the section from t0 to t1, the second A
A low level signal is applied to one input terminal of the ND gate 58 as a first signal.
, The output of the second AND gate 58 is kept low, and the output of the second transistor 5
9 is kept off. Therefore, the second section is provided in the section from t0 to t1.
The second reference voltage Vth2 is supplied from the reference voltage source 47 to the second comparator 46. The voltage V1 of the positive input terminal 60 of the third comparator 42a in the section from t0 to t1 is shown in FIG.
It is kept at 6.5 V as shown in FIG. The voltage of the sawtooth wave generating capacitor 35, that is, the voltage V2 of the first negative input terminal 61 of the third comparator 42a is shown in FIG.
The voltage is maintained at 5 V as shown in FIG. Further, in the section from t0 to t1, the input of the second comparator 46 has a relation of Vin <Vth1, and this output becomes high level, and the third comparator 42a
The voltage V3 of the second negative input terminal 62 is 5 V as shown in FIG. Therefore, in the section from t0 to t1, the third
First and second negative input terminals 61 and 62 of the comparator 42a
Is lower than the voltage V1 at the positive input terminal 60, the output voltage of the third comparator 42a is at a high level, and is obtained on the line 31 via the AND gate 52 and the driving circuit 45. The control pulse, that is, the gate-source voltage Vgs becomes a high level as shown in FIG. F
When the current I1 of ET4 increases as shown in FIG. 8 (C) and the input voltage Vin indicating this detection value reaches the first reference voltage Vth1 at time t1, the output of the first comparator 34 goes high. Convert to As a result, the output of the first NOT circuit 51 becomes low, the output of the first AND gate 52 and the gate-source voltage Vgs in FIG. 8B become low, and the FET 4 is turned off. . NA between t1 and t2
Since the output of the ND gate 53 goes high and the transistor 50 is turned on, the positive input terminal 60 of the comparator 42a is
Voltage V1 drops to approximately 3.5 volts. However, as will be apparent from the following description, during the period from t1 to t2, the voltage V3 of the second negative input terminal 62 becomes the voltage V1 of the positive input terminal 60 (3.
Since it is almost 0 volts, which is lower than 5 V), the output of the third comparator 42a remains high. t
Even if the output of the third comparator 42a is at a high level during the period from 1 to t2, the high level output is blocked by the AND gate 52, the gate-source voltage Vgs during the period from t1 to t2 becomes low, and the FET 4 is turned off. become. When the FET 4 is turned off, the voltage V19 of the tertiary winding 19 has the opposite polarity as shown in FIG. 8 (E), and the input voltages Vin of the first and second comparators 34 and 46 are also shown in FIG. As shown in FIG. 8 (F), it becomes higher than the first and second reference voltages Vth1 and Vth2.
As a result, the high level output of the first comparator 34 is maintained, and the output of the second comparator 46 is changed to a low level,
The voltage V3 at the second negative input terminal 62 of the third comparator 42a
Becomes 0 V as shown in FIG. That is, when the output of the second comparator 46 goes low at t1, the second NO
Since the output of the T circuit 57 goes high and the output of the second AND gate 58 goes high, the transistor 59
Is turned on, and the positive input terminal of the second comparator 46 becomes almost 0V. As a result, the low level output of the second comparator 46 becomes t.
The voltage is held in the interval 1 to t2, the output of the third NOT circuit 56 goes high, the transistor 63 is turned on, and the voltage V3 of the second negative input terminal 62 of the third comparator 42a becomes t1 to t2. The section is kept at zero volts. This allows
As described above, the output of the third comparator 42a becomes high even during the off period of the FET4.

When the release of the stored energy of the transformer 2 shown in FIG.
19 becomes negative as shown in FIG. 8 (E), and the input voltage Vin of the first and second comparators 34 and 46 becomes the first and second reference voltages Vth1 and Vth1 as shown in FIG. 8 (F). It becomes lower than Vth2. As a result, the output of the first comparator 34 goes low, the output of the first NOT circuit 51 goes high,
The blocking of the control pulse by the first AND gate 52 is released. Further, since the output of the third AND gate 58 goes low, the transistor 59 is turned off, and the second reference voltage Vth2 is applied to the positive input terminal of the second comparator 46. Since the input voltage Vin is lower than the second reference voltage Vth2 during the interval from t2 to t3, the output of the second comparator 46, that is, the voltage V of the second negative input terminal 62 of the third comparator 42a is obtained.
3 becomes 5 V as shown in FIG. The voltage V1 of the positive input terminal 60 of the third comparator 42a is not changed until t2.
It is maintained at 5V, but at time t2, the NAND gate 53
Since both inputs are high, transistor 50 is turned off and returns to 6.5V. Voltage V1 of positive input terminal 60
Is 6.5V in the interval from t1 to t2 and also in the interval from t2 to t3.
, This output is also at a high level in the interval from t2 to t3, and this is output via the first AND gate 52 as the gate-source voltage Vgs shown in FIG.
Sent to T4. When the current I1 of the FET 4 increases from the time t2 and the input voltage Vin becomes higher than the first reference voltage Vth1 at the time t3, the same operation as in the section from t0 to t1 is repeated.

When the output voltage Vout is low due to a load short circuit or the like as shown after the time point t4 in FIG. 8, the same operation as after the time point t4 in FIG. 6 occurs. That is, t4 in FIG.
Later, the voltage Vin on line 28 becomes the second comparator 46
Is not higher than the second reference voltage Vth2 of the
Is always high, and transistors 59 and 63 are kept off. Therefore, the voltage V3 at the second negative input terminal 62 of the third comparator 42a is approximately 5 V
And becomes substantially independent of comparison with the voltage V1 of the positive input terminal 60. Therefore, the output of the third comparator 42a changes based on the comparison between the voltage V1 of the positive input terminal 60 and the voltage V2 of the first negative input terminal 61.

The operations during the ON period immediately before t4 and during the ON period from t5 to t6 are substantially the same as the ON periods during t0 to t1 and t2 to t3 in the normal state. At time t4, when the voltage Vin reaches the first reference voltage Vth1 and the output of the first comparator 34 goes high, the output of the NOT circuit 51 goes low,
The output of the first AND gate 52 also goes low, and FE
T4 turns off. Further, when the output of the NOT circuit 51 goes low at t4, the output of the NAND gate 53 goes high, turning on the transistor 50, and the voltage V1 of the positive input terminal 60 of the third comparator 42a becomes three. 0.5V. Therefore, the voltage V1 of the positive input terminal 60 is equal to the first and second voltages.
Are lower than the voltages V2 and V3 of the negative input terminals 61 and 62, and the output terminal of the third comparator 42a goes low.
Thereby, the off state of the FET 4 is maintained.

When the load is short-circuited, the voltage V19 of the winding 19 is low as shown at t4 to t5 in FIG. 8, so that the voltage Vin on the line 28 becomes the first reference voltage immediately after t4 as shown in FIG. It becomes lower than the voltage Vth1. Therefore, the output of the first comparator 34 goes low immediately after t4, and the output of the NOT circuit 51 goes high. However, since the low level output from the third comparator 42a is input to the NAND gate 53, the output of the NAND gate 53 is maintained at a high level, and the voltage V1 of the positive input terminal 60 is maintained at 3.5V. As a result, the output of the third comparator 42a and the output of the AND gate 52 do not change, and the off period from t4 to t5 is maintained.

The end of the OFF period is determined by the voltage V2 of the first negative input terminal 61 of the third comparator 42a. That is, since the output of the third comparator 42a is at a low level during the period from t4 to t5, the diode 44 is turned on, the transistor 37 is turned off, and the discharge of the sawtooth wave generating capacitor 35 is performed via the resistor 36. Occurs. Capacitor 35
8, that is, the voltage V2 of the first negative input terminal 61 is
As shown in (A), the voltage gradually decreases with a time constant determined by the capacitor 35 and the resistor 36. When the voltage V2 becomes lower than the voltage V1 of the positive input terminal 60 at time t5, the third comparator 4
The output of 2a changes to high level, the output of AND gate 52 also changes to high level, and FET4 turns on. Then t
The operation in the section from 5 to t6 is substantially the same as the operation in the section from t5 to t6 in FIG.

As is apparent from the above description, also in the second embodiment, the ON / OFF cycle of the FET 4 becomes longer when the load is short-circuited, and the same operation and effect as those of the first embodiment can be obtained.

[0032]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Instead of the FET 4, an anti-parallel circuit of a bipolar transistor and a diode can be connected. (2) The winding voltage of the transformer 2 can be detected based on the primary winding 3 or the secondary winding 6 without being detected by the tertiary winding 19. (3) In FIG. 5, a second discharging resistor 48 is connected in parallel to the first discharging resistor 36 via a transistor, and this transistor can be turned on / off by the output of the second comparator 46.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a conventional switching power supply device.

FIG. 2 is a circuit diagram showing a primary side of the transformer of FIG. 1 in detail.

FIG. 3 is a waveform diagram showing a state of each unit in FIGS. 1 and 2;

FIG. 4 is a waveform diagram of each part in FIG. 2 for schematically explaining a resonance operation.

FIG. 5 is a circuit diagram showing a primary side of a transformer of the switching power supply according to the first embodiment.

FIG. 6 is a waveform chart showing each part of FIG. 5 and an output voltage.

FIG. 7 is a circuit diagram showing a control pulse forming circuit according to a second embodiment.

8 is a waveform chart showing the state of each part in FIG.

[Explanation of symbols]

 4 FET 5 Current detection resistor 21 Winding voltage detection diode 34, 42, 46 Comparator 35 Saw wave generation capacitor 36, 48 Discharge resistor

Claims (3)

[Claims] 1. A series circuit of a primary winding of a transformer and a switching element connected between one end and the other end of a DC power supply, having a directivity of conducting during an OFF period of the switching element. A rectifier diode connected to a secondary winding of the transformer, an output smoothing capacitor connected in parallel to the secondary winding via the rectifier diode, and a pseudo-parallel connected to the switching element in parallel A resonance capacitor or a stray capacitance; current detection means for detecting a current flowing through the switching element to obtain a current detection voltage having a value corresponding to the value of the current; and the primary winding of the transformer Or, a winding voltage detecting means for obtaining a signal indicating a voltage of the secondary winding or the tertiary winding; and the current detection voltage obtained from the current detecting means and the winding voltage detecting means. An addition circuit for adding the obtained winding voltage, a sawtooth wave generating capacitor for generating a sawtooth wave, a charge control transistor connected between the DC power supply and the sawtooth wave generating capacitor, A first reference voltage source for generating a first reference voltage; a first comparator for generating a comparison output between the addition voltage obtained from the addition circuit and the first reference voltage; A second reference voltage source that generates a second reference voltage higher than the reference voltage; a second comparator that compares the added voltage obtained from the adding circuit with the second reference voltage; A third reference voltage source connected to a base of the charge control transistor via a first resistor, and a pulse indicating an on-period of the switching element, wherein one input terminal is connected to the input terminal; Charge control transistor A third comparator connected to the base of the third comparator, the other input terminal of which is connected to the sawtooth-wave generating capacitor; and between the one input terminal and the output terminal of the third comparator. A diode connected via a second resistor; and a diode connected between an output terminal of the third comparator and ground and indicating that the added voltage is higher than the first reference voltage. A control that becomes conductive in response to the output of the first comparator and becomes nonconductive in response to the output of the first comparator indicating that the added voltage is lower than the first reference voltage. A switch for discharging the sawtooth wave generating capacitor, wherein the first signal is output in response to an output of the second comparator indicating that the added voltage is higher than the second reference voltage.
To form a circuit having a discharge time constant of
And a discharge circuit for forming a circuit having a second discharge time constant larger than the first discharge time constant in response to an output of the second comparator indicating that the second discharge time constant is lower than a reference voltage of the second comparator. A switching power supply device characterized in that: 2. A series circuit of a primary winding of a transformer and a switching element connected between one end and the other end of a DC power supply, having a directivity of conducting during an off period of the switching element. A rectifier diode connected to a secondary winding of the transformer, an output smoothing capacitor connected in parallel to the secondary winding via the rectifier diode, and a pseudo-parallel connected to the switching element in parallel A resonance capacitor or a stray capacitance; current detection means for detecting a current flowing through the switching element to obtain a current detection voltage having a value corresponding to the value of the current; and the primary winding of the transformer Or, a winding voltage detecting means for obtaining a signal indicating a voltage of the secondary winding or the tertiary winding; and the current detection voltage obtained from the current detecting means and the winding voltage detecting means. An addition circuit for adding the obtained winding voltage, a sawtooth wave generating capacitor for generating a sawtooth wave, a charge control transistor connected between the DC power supply and the sawtooth wave generating capacitor, A first reference voltage source for generating a first reference voltage; a first comparator for generating a comparison output between the addition voltage obtained from the addition circuit and the first reference voltage; A second reference voltage source that generates a second reference voltage higher than the reference voltage; a second comparator that compares the added voltage obtained from the adding circuit with the second reference voltage; A third reference voltage source connected to the base of the charge control transistor via a first resistor; a positive input terminal; and first and second negative input terminals, wherein the positive input terminal is Connects to the third reference voltage source via a second resistor A third comparator having the first negative input terminal connected to the sawtooth wave generating capacitor; and a base between the base of the charge control transistor and an output terminal of the third comparator. A diode connected via a third resistor, and a first comparison input level switch connected via a fourth resistor between the positive input terminal of the third comparator and ground. A switch, a discharging resistor connected in parallel to the sawtooth wave generating capacitor, one input terminal connected to the output terminal of the third comparator, and the other input terminal connected to the output terminal of the first comparator. A first logic connected to an output terminal for outputting a signal for turning on the switching element only when the output of the third comparator is at a low level while the output of the third comparator is at a high level; Gate circuit and one input terminal The output terminal of the first comparator is connected to the output terminal of the third comparator, and the other input terminal is connected to the output terminal of the third comparator. A second logic gate circuit for turning off the first comparison input level changeover switch only when the output of the comparator is at a high level, and a reference voltage control circuit connected in parallel to the second reference voltage source. A switch connected to an output terminal of the first comparator and an output terminal of the second comparator, wherein the output of the first comparator is at a high level and the second comparator is at a low level. A third logic gate circuit for turning on the reference voltage control switch only at the time of; and a third logic gate circuit connected between the second negative input terminal of the third comparator and ground, A second comparison input level that is turned on in response to the low level output of the comparator. Switching power supply apparatus characterized by and a Le switching switch. 3. The transformer has a tertiary winding and is connected to a rectifying and smoothing circuit for a control power supply. The tertiary winding detects an output voltage of the output smoothing capacitor. A circuit for forming a voltage control signal corresponding to the voltage difference; a light emitting element responsive to the voltage control signal; and a phototransistor optically coupled to the light emitting element for the control power supply. The winding voltage detecting means is connected between a rectifying / smoothing circuit and an output terminal of the adding circuit, and has a direction of conducting by a voltage obtained in the tertiary winding during an OFF period of the switching element. 3. The switching power supply according to claim 1, wherein the switching power supply is a diode connected to the tertiary winding.