JPH10283266A - Semiconductor integrated circuit and test method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent data in an ROM from being deciphered without enciphering any test signal by providing a dummy signal generating circuit with which a dummy signal is generated when the test signal is inputted to a test signal input terminal. SOLUTION: On the periphery of a semiconductor chip 1, an input/output terminal and an input/output buffer 13 are formed. Besides, a dummy signal generating circuit 7 is installed on the semiconductor chip 1 and connected with dummy signal output terminals 15a-15d. The dummy signal generating circuit 7 generates the dummy signal while the test signals are outputted from the test signal output terminals 11a-11b. This dummy signal is outputted through dummy signal output terminals 15a-15d to the outside. Thus, since the signals are simultaneously generated from the test signal generating terminals 11a-11b and the dummy signal generating terminals 15a-15d, it is made difficult to discriminate which output terminal generates the data stored in an ROM 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having security measures for data stored in a semiconductor device. In particular, the present invention relates to a semiconductor integrated circuit having a built-in read-only memory, and to a security measure for data stored in the read-only memory.

[0002]

2. Description of the Related Art A read-only memory (hereinafter referred to as a ROM) is a non-volatile memory that retains stored data even when a power supply is turned off. Widely used for memory. Since the amount of data stored in ROM has become enormous with the increase in the degree of integration of semiconductor integrated circuits, R
It is essential for a semiconductor integrated circuit having a built-in OM to test whether or not a program stored at the time of pickup operates normally. In the ROM test method, a test signal is input to a designated area of the ROM, the output test signal is read, and a test is performed to determine whether the output program data operates normally.

A conventional semiconductor integrated circuit having a ROM and a method of testing a ROM incorporated in the semiconductor integrated circuit will be described with reference to FIGS. 3, 4 and 5. FIG. Figure 3 shows RO
FIG. 11 is a schematic block diagram showing a first conventional example of a semiconductor integrated circuit incorporating M. First, a ROM 203 for storing data on a semiconductor chip 201, a central processing unit (hereinafter referred to as a CPU) 205 for performing arithmetic processing and control of a microcomputer based on data from the ROM, and a ROM 20
3 and a data bus for transmitting and receiving signals between functions of the CPU 205, input / output terminals (111a to 111b, 112a to 112b) for transmitting and receiving signals to and from the outside, and an input / output buffer 213 for driving signals to and from the inside and outside. Are formed to constitute a semiconductor integrated circuit.

The ROM 203 has data read terminals D0 to D7 connected to a data bus. Further, it has a lead terminal RD, a chip select terminal CS, and an address terminal AD as data input terminals.

Next, a method of testing data stored in the ROM 203 shown in FIG. 3 will be described. First, when a read signal is input to the RD terminal of the data input terminal and a chip select signal is input to the CS terminal to specify an address, a test signal is output from the data read terminals D0 to D7. The test signal is the ROM output from the data read terminal
The program data is stored in the program 203. This data is sent to the input / output buffer 213 and the test signal output terminal 11
1a to 111b, the ROM 2
03 can be tested.
When testing the ROM 203, the test signal output terminal 11
Output signals are output only from 1a to 111b, and no output signals are output from other output terminals 112a to 112b.

However, the test signal output terminals 111a-1111
Since the data output from 11b is the data itself stored in the ROM 203, there is a possibility that reading the data will decrypt the data stored in the ROM 203.

Therefore, a second conventional example having a countermeasure for making it impossible to decode data stored in the ROM will be described below. The second conventional example is a semiconductor integrated circuit that encrypts a test output signal of a ROM so that the data stored in the ROM cannot be decrypted. A test method for a semiconductor integrated circuit will be described below with reference to FIG. First, a test signal is input to the ROM, and a test signal is generated from the data output terminal (first step). Next, some processing is performed on the test signal to encrypt the test signal. As an encryption method, it is conceivable to input the output test signal to an encryption circuit (second step).

Next, the encrypted test signal is output from the test signal output terminal to the outside (third step). Next, restoration of returning the encrypted test signal to the original test signal is performed. (4th step).

Next, using the restored test signal, R
The data stored in the OM is tested (fifth step). FIG. 5 shows a block diagram of a semiconductor integrated circuit having this encryption circuit. The semiconductor integrated circuit shown in FIG. 5 has a ROM 30 in which data is stored on a semiconductor chip 301.
3. CPU 305, which performs arithmetic processing and control of the microcomputer based on data from ROM 303, ROM
A data bus for transmitting / receiving signals between functions of the CPU 303 and the CPU 305; an encryption circuit 304 for encrypting a test signal output from the ROM 303;
4, a test signal output terminal 311 for transmitting and receiving signals to and from the outside constitutes a semiconductor integrated circuit.

The test signal output from the ROM 303 is output from the read terminals D0 to D7 and input to the encryption circuit 304, where the test signal is encrypted. One example of encryption is to invert all signals using an inverter. Then the encrypted test signal is
The test signal is output from the test signal output terminal 311 to the outside. The encrypted test signal is input to a decryption circuit and the original R
It is returned to the data stored in the OM. The test of the data stored in the ROM is performed using the decoded test signal. The decryption circuit is a circuit provided outside the semiconductor chip 301 and can be prepared according to the encryption circuit.

The second conventional example is disadvantageous in that an encryption circuit must be added to complicate the design process, and at the same time, the circuit becomes large-scale and the chip area increases with the advancement of encryption. Occurs. Further testing of the added circuit is also required. In addition, it is necessary to decrypt the encrypted signal or create a test pattern that can confirm the encrypted data. Further, there is a possibility that the encrypted ROM data is specified from the test output signal of the ROM data. In many cases, the encryption circuit itself is known, and there is a possibility that the encrypted data can be decrypted.

[0012]

A first conventional example is an internal ROM.
Since the stored data itself stored in the internal ROM is directly output to the outside, there is a disadvantage that important information and program data stored in the internal ROM can be easily read.

In the second conventional example, it is possible to decrypt encrypted data if (1) an encryption method (technique) and (2) encrypted data are available. Regarding 〓, the technology may be public or the technology may be publicly known, and the encrypted data itself may be known to an external person, and the encrypted data may be decrypted. In other words, data encryption alone is not currently a perfect security measure, and it is necessary to ensure that the encrypted data itself cannot be seen from outside. For this purpose, the encryption circuit must be complicated, which causes problems such as a complicated circuit design and an increase in circuit area.

An object of the present invention is to provide a semiconductor integrated circuit having a security measure for preventing decryption of data in a ROM without encrypting a test signal when testing data stored in a semiconductor element of the semiconductor integrated circuit. Aim.

[0015]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a semiconductor element formed on a semiconductor chip; a test signal input terminal for inputting a test signal of the semiconductor chip; A test signal output terminal for outputting a test signal of the semiconductor chip to the outside, a dummy signal generation circuit formed on the semiconductor chip for generating a dummy signal, and a dummy for outputting a dummy signal generated from the dummy signal generation circuit to the outside And a signal output terminal. Since signals are simultaneously generated from the test signal generation terminal and the dummy signal generation terminal when testing the semiconductor device, it is difficult to determine from which signal terminal the data stored in the semiconductor device is generated.

Further, the method for testing a semiconductor integrated circuit according to the present invention includes a step of inputting a test signal from a test signal input terminal to a semiconductor element and a step of outputting a test signal from the semiconductor element from a test signal output terminal to the outside. Generating a dummy signal from a dummy signal generating circuit in response to a test signal, and outputting the dummy signal from a dummy signal output terminal to the outside.

Further, the output of the test signal and the output of the dummy signal are performed simultaneously, and the test signal output terminal and the dummy signal output terminal are different terminals. According to the present invention, the output of the test signal and the output of the dummy signal are performed from different terminals. Therefore, it is difficult to specify the output terminal of the test signal, and to prevent the data stored in the semiconductor element from being read. Can be done.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.
The outline of the present invention will be described.

The semiconductor integrated circuit according to the present invention includes a ROM 3 formed on a semiconductor chip 1, test signal input terminals 9a to 9b for inputting a test signal of the ROM 3 on the semiconductor chip 1, and an externally provided test signal for the ROM 3. Test signal output terminals 11a to 11b to be output to the semiconductor chip 1
It has a dummy signal generation circuit 7 formed thereon and dummy signal output terminals 15a to 15d for outputting a dummy signal generated from the dummy signal generation circuit 7 to the outside. Since signals are simultaneously generated from the test signal generation terminals 11a to 11b and the dummy signal generation terminals 15a to 15d during a test, it is difficult to determine from which output terminal the data stored in the ROM 3 is generated.

First, the ROM 3 is widely used for storing fixed programs, fixed numbers, characters, and the like in a computer that need not be rewritten as needed. The ROM 3 has data read terminals D0 to D7 connected to a data bus. Further, it has a lead terminal RD, a chip select terminal CS, and an address terminal AD as input terminals.

On the periphery of the semiconductor chip 1, input / output terminals and input / output buffers 13 are formed. The input / output terminals are test signal input terminals 9a to 9b for inputting test signals to the ROM 3, test signal output terminals 11a to 11b for outputting test signals, and a dummy for outputting a dummy signal generated from the dummy signal generation circuit 7 to the outside. Signal output terminal 15
a to 15d. The structure of the input / output terminal has the same structure, and the name is changed depending on the form of use.

A dummy signal generating circuit 7 is provided on the semiconductor chip 1 and is connected to dummy signal output terminals 15a to 15d. The dummy signal generation circuit 7 supplies test signals to the test signal output terminals 11a to 11a when testing the ROM 3.
1b, it has a structure to generate a dummy signal when outputting. The dummy signal is supplied to the dummy signal output terminal 15a.
-15d. In this case, the dummy signal outputs the internal signal as it is to the outside, forms a simple logic between the internal signals, or combines the signals input to and output from the ROM so that a signal synchronized with the data in the ROM is output. To generate and output a random signal. When a dummy signal generation circuit is created by the above method, a small circuit having several gates is added, but a sufficient security effect can be obtained. It is also possible to generate a more sophisticated dummy signal by using a somewhat complicated circuit such as a counter. The greater the number of terminals of the dummy signal output from the dummy signal output terminal, the greater the effect can be obtained. Since the dummy signal generation circuit only generates a random signal, there is no need to test. Since data output from the test output terminal to the outside is not encrypted, there is no need to add a circuit for decryption or change the test pattern.

The number of dummy pattern output terminals is not limited to four as shown in this embodiment, but can be increased by the structure of the dummy pattern generating circuit 7. FIG. 2 is a block diagram of a semiconductor integrated circuit on which a specific dummy signal generation circuit is mounted. The semiconductor integrated circuit shown in FIG. 2 is characterized in that a test signal input terminal is connected to a dummy signal generation circuit, and a dummy signal is generated from the dummy signal generation circuit when a test signal is input to a semiconductor element.

First, the ROM 103 is widely used for storing fixed programs, fixed numbers, characters, and the like in a computer that need not be rewritten at any time. The ROM 103 has data read terminals D0 to D7 connected to a data bus. Further, it has a lead terminal RD, a chip select terminal CS, and an address terminal AD as input terminals.

On the periphery of the semiconductor chip 101, input / output terminals and input / output buffers 113 are formed. The input / output terminals are test signal input terminals 109a to 109c for inputting test signals to the ROM 103, test signal output terminals 111a to 111b for outputting test signals to the outside, and outputting a dummy signal generated from the dummy signal generation circuit 107 to the outside. Dummy signal output terminals 115a to 115d.

On the semiconductor chip 101, a CPU 105 for performing arithmetic processing and control of a microcomputer based on data from the ROM 103, the ROM 103 and the CPU 1
It has a common data bus for transmitting and receiving signals between functions such as 05.

A dummy signal generation circuit 107 is provided on the semiconductor chip 101, and a test signal input terminal 109a
To 109c and dummy signal output terminals 115a to 115d
Is connected to Dummy signal generation circuit 107 has R
It has a structure in which a dummy signal is generated when a test signal is output from the test signal output terminal 111 at the time of testing the OM 103. The dummy signal is a dummy signal output terminal 1
It is output to the outside via 15a-115d. The dummy signal and the test signal are simultaneously output to the outside.

The dummy signal generating circuit includes a NOR circuit and a NO
It is composed of a T circuit. One input terminal of the NOR circuit is connected to the RD terminal, and the other input terminal is connected to the CS terminal. The output terminal of the NOR circuit is connected to the dummy signal output terminal 115. The input terminal of the NOT circuit is AD
Output terminal is connected to the dummy signal output terminal 115.
It is connected to the. Further, there is a NOT circuit in which an input terminal is connected to the data read terminals D0 to D7 and an output terminal is connected to the dummy signal output terminal 115.

Next, the operation of the semiconductor integrated circuit will be described. First, test signal input terminals 109a to 109
A test signal is input to c, and a read signal, an address signal, and a chip select signal are input to the ROM 103.
The ROM 103 receives the test signal, outputs a test signal from the designated data area via the data read terminals D0 to D7, and outputs the test signal output terminals 111a to 111a.
Output to the outside via 1b.

Test signal input terminals 109a-109
When the test signal is inputted to the dummy signal generation circuit 1c,
A test signal is input to 07. The data output signal output from the ROM 103 is also supplied to the dummy signal generation circuit 10.
7 is input. The test signal and the data output signal are changed by the NOR circuit and the NOT circuit in the dummy signal generation circuit 107, and the dummy signal output terminals 115a to 115
Output to the outside via 5d.

When outputting a test signal, it is necessary to know in advance which terminal outputs a data signal and which terminal generates a dummy signal by the circuit structure of the dummy signal generation circuit. is there. In the case of the present embodiment, the data signals are output from the test signal output terminals 111a to 111a.
11b, and the dummy signal is output from the dummy signal output terminals 115a to 115d.

The number of dummy signal output terminals varies depending on the circuit structure of the dummy signal generation circuit. It is also possible to change the positions of the data signal output terminal and the dummy signal output terminal.

[0033]

According to the present invention, the dummy signal generation circuit having a relatively simple structure without the complicated encryption circuit and having the above structure makes it difficult to analyze the data output from the semiconductor element. As a result, external data analysis can be prevented. Further, the configuration of the dummy signal generation circuit can be easily changed, and even if the configuration changes, only the terminal to which the data signal is output changes, so that the test method can be easily performed only by changing the setting. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram of a semiconductor integrated circuit according to the present invention.

FIG. 3 is a block diagram of a conventional semiconductor integrated circuit.

FIG. 4 shows a conventional method for testing a semiconductor integrated circuit.

FIG. 5 is a block diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 101 Semiconductor chip 3 103 ROM 5 105 CPU 7 107 Dummy signal generation circuit 9 109 Test signal input terminal 11 111 Test signal output terminal 13 113 I / O buffer 15 115 Dummy signal output terminal

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11C 29/00 673 G01R 31/28 V B

Claims (16)

[Claims] A semiconductor device formed on a semiconductor chip; a test signal input terminal for inputting a test signal of the semiconductor chip; a test signal input to the test signal input terminal formed on the semiconductor chip; And a dummy signal generating circuit for generating a dummy signal. A semiconductor element formed on the semiconductor chip; a test signal input terminal for inputting a test signal of the semiconductor chip; a test signal output terminal for outputting a test signal of the semiconductor chip; And a dummy signal output terminal for outputting a dummy signal generated from the dummy signal generation circuit. 3. The semiconductor integrated circuit according to claim 2, wherein said dummy signal generation circuit generates a dummy signal when a test signal is input to said test signal input terminal. 4. The test signal output terminal and the dummy signal output terminal are different terminals.
A semiconductor integrated circuit as described in the above. 5. When a test signal is input to the test signal input terminal, a test signal is output from the test signal output terminal, and at the same time, a dummy signal is output from the dummy signal output terminal. Item 3. A semiconductor integrated circuit according to item 2. 6. The test signal output terminal and the dummy signal output terminal are input / output terminals formed in the periphery of the semiconductor chip. 3. The semiconductor integrated circuit according to claim 2, wherein the position of the output terminal changes. 7. The semiconductor integrated circuit according to claim 2, wherein said dummy signal generation circuit is connected to said test signal input terminal. 8. The semiconductor integrated circuit according to claim 2, wherein a data output signal output from said semiconductor element is input to said dummy pattern generation circuit. 9. The semiconductor device according to claim 1, wherein said semiconductor element is a storage element storing data such as a program.
9. The semiconductor integrated circuit according to any one of items 8 to 8. 10. A step of inputting a test signal from a test signal input terminal to a semiconductor element, a step of outputting a test signal from the semiconductor element from a test signal output terminal to the outside, and a dummy signal generation circuit based on the test signal. A step of generating a dummy signal from the semiconductor device, and a step of outputting the dummy signal from a dummy signal output terminal to the outside. 11. The method according to claim 10, wherein the output of the test signal and the output of the dummy signal are performed simultaneously. 12. The test method for a semiconductor integrated circuit according to claim 10, wherein said test signal output terminal and said dummy signal output terminal are different terminals. 13. The semiconductor integrated circuit according to claim 10, wherein the circuit configuration of said dummy pattern generation circuit is changed to change the positions of a terminal for outputting a test signal and a terminal for generating a dummy signal. How to test the circuit. 14. The test method for a semiconductor integrated circuit according to claim 10, wherein the test signal input to the test signal is input to the dummy signal generation circuit to generate a dummy signal. 15. The method according to claim 10, wherein a test signal output from the semiconductor element is input to the dummy signal generation circuit. 16. The semiconductor integrated circuit according to claim 10, wherein said semiconductor element is a storage element, and said test signal is inputted to test data stored in said storage element. Test method.