JPH10283192A - Prefetching code generation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hide a main memory penalty in the case that a data area accessed by a loop exceeds a cache capacity by dividing an inner side loop into two and starting the prefetching of data in a second half loop at the time of the repetition of an outer side loop one before for the data required in a first half loop and in the first half loop for the data required in the second half loop. SOLUTION: The inner side loop is divided into two and a code for incorporating the prefetching processing of the data required at the first part of the repetition processing of the outer side loop one after in the second half loop 41 and incorporating the prefetching of the data required in a second half in the repetition processing of the same outer side loop in the first half loop 40 is generated. For the distribution of the front half loop 40 and the second half loop 41, the processing time of the second half loop 41 is turned to be more than main memory penalty time. In the case that the processing time of the second half loop 41 can not be turned to be more than the main memory penalty, loop development is performed relating to the outer side loop and an arithmetic amount is increased so as to completely hide the main memory penalty.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of executing a program for performing instruction level parallel processing, and more particularly to a code generation method suitable for a loop in a case where data accessed by the program is large and cannot be stored in a cache.

[0002]

2. Description of the Related Art As one direction of a supercomputer, a parallel processing system using a scalar processor as a node processor is considered promising. Parallel supercomputers using scalar processors are expected to be improved by improving the clock frequency due to advances in semiconductor technology, and by realizing instruction-level parallel processing such as the superscalar method that makes effective use of multiple arithmetic units that can execute in parallel. This is because the processing performance of the processor has been dramatically improved. However,
Its high scalar processor throughput is only achieved when the cache works.

A scalar processor generally has an instruction processing device, a cache and a memory device. A scalar processor stores a program and data in a memory, and processes the data in the memory according to instructions described in the program. The cache is a relatively small-capacity storage unit having a short reference time from the instruction processing device, and temporarily stores a program and a part of data. Data necessary for executing the instruction is read from the memory, but at the same time, a data block including the data is copied to a line constituting the cache, and when a reference to the data in the block is designated thereafter, the data is read from the cache line. refer. The transfer of the data block from the memory to the cache line is called line transfer.

When data necessary for instruction execution is not in the cache, this is called a cache miss. When a cache miss occurs, line transfer is executed. In a conventional scalar processor, when this line transfer occurs along with the execution of an instruction, the execution of the instruction is awaited until its completion. Therefore, when cache misses occur frequently, the execution time of the program increases due to the queuing associated with the line transfer,
There is a problem that the processing performance of the scalar processor deteriorates. In particular, in large-scale scientific and technical calculations, the performance is greatly reduced due to a cache miss due to the property that the data area is large and the locality of data is small.

On the other hand, recently, an attempt has been made to avoid the performance degradation associated with the line transfer by executing a special instruction for prefetching data in advance in a program in advance of an instruction which may cause a cache miss. It has been done. This data prefetch is called prefetch. For example, the microprocessor Powe of IBM of the United States
In rPC, there is a prefetch instruction for reading data located at a specified operand address into a cache. In this operation, when a cache miss occurs, the line transfer is performed without waiting for the completion of the prefetch instruction. Therefore, when an instruction that refers to the data is executed, the performance degradation is avoided because the data is in the cache.

Using such a prefetch instruction,
A paper on code generation technology that effectively hides main memory latency by overlapping data transfer and operation
ToddC. Mowry, Monica S. Lam, Anoop Gupta “Design and
Evaluation of a CompilerAlgorithm for Prefetchin
g ”ASPLOS-V, ACM 0-89791-535-6 / 92/0010/0062 pp.62-
Shown at 73.

[0007]

However, the above-mentioned conventional code generation technology has the following problems. DO20 (20) and DO10 as shown in FIG.
In the generation of the prefetch code for the multiplex loop shown in (21), only the inner loop DO10 (21) has been considered. The problem will be specifically described using an example.

First, the assumption of the architecture assumed in the following code generation will be described. The target scalar processor has two load / store instructions and two floating-point operations.
And two integer operations can be executed simultaneously, the cache line size is 32 bytes, and the main memory penalty at the time of a cache miss is 75 cycles.

For the source program of FIG. 2, the compiler first searches for a prefetch target operand by locality analysis or the like. As a result, reference b (i, j)
Assume that 22 is a prefetch target operand. If the size of the operand is 8 bytes, continuous 32-byte data including the target operand is stored in the cache in one prefetch, so it is useless to execute the prefetch instruction for each loop iteration. Thus, in this example, the prefetch instruction may be output once every four times. For this reason, generally, the loop structure conversion unit of the compiler performs
Perform double loop unrolling.

FIG. 3 shows the result. Here, loop 2
1 is divided into a loop 25 and a loop 26. The loop 26 is a remainder loop of the loop expansion. Hereinafter, for the sake of simplicity, the remainder of the loop expansion will be omitted. After normal optimization and code generation, a prefetch code is generated.

Generation of the prefetch code is performed as follows. First, the number of execution cycles per loop of the loop 25 is estimated. In the loop 25, the load instruction is 4
, Four store instructions, four floating-point operations, and one prefetch instruction, so the number of processing cycles per loop is five (= max (ceil ((4 + 4 + 1)
/ 2) and 2/2). Where the ceil function is
Means the smallest integer that does not exceed the value of the argument. Since the main memory penalty at the time of a cache miss is 75 cycles,
In the loop processing, if a code for prefetching data used 15 times (ceil (75/5) = 15) is generated, the main storage penalty can be hidden.

FIG. 4 is obtained by adding a prefetch instruction to the code of FIG. Here, the A section 30 is a section for performing prefetching of data required at the beginning of the loop iteration, the B section 31 is a loop section including a data prefetch instruction to be used 15 times later for arithmetic processing and loop iteration, and C section. The unit 32 is a loop part that does not include a prefetch instruction in the latter half of the loop processing.

FIG. 5 schematically shows the state of execution at that time. The horizontal axis indicates time, the hatched box indicates prefetch processing, and the empty box indicates arithmetic processing. However, for the convenience of the drawing, the program does not numerically match the program in FIG. That is, part A of FIG. 4 is a prefetch loop of 15 times, but is omitted three times in FIG. Here, the problem is the part A, and the main memory access penalty becomes apparent. This is a problem particularly when the number of loop processes is small.

In the following, we will look at the performance of this code.
When the loop length is N = 100, the execution time of the part A is at least 75 cycles of the main memory access penalty, the part B is 50 cycles (5 cycles per loop × 10 times the loop), and the part C is 60 cycles. (4 cycles per loop × 15 loops), a total of 185 cycles, 40% of the total time (75/185 × 100
%) Is the overhead of waiting for main memory. Further, when the loop length is as small as 50, the portion A is at least 75 cycles, the portion B is not executed because the loop length is small, and 0 cycle, and the portion C is 48 cycles (4 cycles per loop × 12 loops). Execution), for a total of 133 cycles, 56% (75/133 × 100
%) Is a major problem that results in an overhead of waiting for main memory. The reason for writing at least 75 cycles in part A is that there is a limit to the number of prefetch instructions that can be processed simultaneously in a real computer. Here, it is assumed that it is sufficiently large.

The code generation using the inner loop unrolling method for reducing the prefetch instructions described above is as follows.
There are the following problems. Usually, it is considered that such a loop structure conversion is performed in the first half of the compiler, and thereafter, optimization processing is performed, and a prefetch instruction is inserted in the code generation unit. In this way, most of the compiler processing has to deal with large intermediate words by loop unrolling,
Requires a long compilation time. Here, since the example in which the line size is 32 bytes is shown, the expansion is at most 4 times.
A loop expansion as much as six times is required, which is even more serious.

An object of the present invention is to provide a code generation method using a prefetch instruction which solves the above-mentioned problems.

[0017]

The object of the present invention is to divide the inner loop processing into two, as shown in FIG.
1, a data prefetching process required at the beginning of the repetition processing of the next outer loop is incorporated, and in a first half loop 40, a prefetching process of data required in the latter half of the same outer loop repetition processing is performed. This is achieved by generating code that incorporates

In the example, when the outer loop J = 1 and the inner loop I = 3, 4, 5, 6, 7, the outer loop J =
2 inserts an instruction for prefetching necessary data in inner loop I = 1, 2, 3, 4, 5 and outer loop J =
At the time of the processing of the inner loop I = 1, 2, the instruction for prefetching the necessary data in the latter half I = 6, 7 of the inner loop is inserted. Here, the distribution of the former half loop 40 and the latter half loop 41 divides the loop processing so that the processing time of the latter half loop 41 becomes equal to or longer than the main storage penalty time.

Here, when the number of operations in the inner loop is small and the loop length is short, the processing time of the second half loop 41 may not be longer than the main storage penalty. In this case, if the processing time of the loop is a loop length that is equal to or greater than the assumed specified value, the loop expansion is performed on the outer loop so that the main memory penalty can be completely hidden, and the amount of calculation is increased. Achieve this goal.

The problem of an increase in compile time due to code generation using the inner loop unrolling method for reducing the number of prefetch instructions can be solved by a method of duplicating code in the code generation processing in the second half of the compiler processing.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a compiler according to the present invention. FIG. 1 shows the overall structure of the compiler. The source program 1 in FIG. 1 is converted into the intermediate language 3 by the syntax analysis 2. The loop structure conversion unit 4 receives the input as an input, performs loop expansion on the outer loop in order to increase the concealment rate of the main storage latency of the prefetch code for the multiplex loop, and outputs the intermediate language 5. The optimizing unit 6 performs an ordinary well-known traditional optimization, and outputs an intermediate language 7. Code generator 8
Changes the object code including the prefetch instruction to 9
Is generated based on the intermediate language 7. The present invention relates to 4 and 8, and relates to improving the execution efficiency of the object code 9.

FIG. 7 shows a part of the loop structure conversion unit 4 shown in FIG. 1 which relates to efficient concealment of a main memory access penalty in a multiplex loop. The source program 1 input to FIG. 7 will be described with reference to the FORTRAN program of FIG. DO20 (20) and DO10 (21) in FIG.
Indicates a loop, and these constitute a double loop.
FIG. 7 performs the following processing on such a program to convert it into an intermediate language 5.

The process shown in FIG. 7 sequentially processes multiple loops 50 in the source program. The decision 51 selects a multiplex loop that outputs a prefetch code in consideration of the multiplex loop. Here, the normal type multiple loop including one loop is limited to one loop. The source program shown in FIG. 2 is suitable because the outer loop DO20 (20) has only one loop DO10 (21). In this example, in the outer loop DO20 (20),
When there are a plurality of DO loops, the present invention does not output a prefetch instruction in consideration of multiple loops, and thus determines that the loop structure does not match.

In the process 52, the number of execution cycles per original inner loop is estimated. In the loop, there is one floating point operation, one load operation, and one store operation. Therefore, in the assumed architecture, II = max (ceil ((1 + 1) / 2 ), Ceil
(1/2)) = 1 cycle.

In the process 53, the minimum loop length MINL for completely concealing the main storage access penalty of the data necessary for the process in the next outer loop is obtained. In this case, since the main storage access penalty is 75, MINL = 7
It becomes 5. That is, in this state, the inner loop length is 75
If the value is less than the above, data necessary for execution of the next outer loop cannot be prepared without overhead, and a data waiting state occurs. In an actual program, it is often smaller than this loop length.

Therefore, as a code generation policy of the compiler, if the loop length is 40 or more, a code capable of completely concealing the main memory access penalty will be generated. In the determination 54, the specified value is a value determined in this way by the code generation policy of the compiler. In the case of the source program of FIG. 2, since MINL = 75 and the specified value = 40, the flow proceeds to determination 55. The judgment 55 indicates whether the same processing as the original program is performed even if the outer loop is unrolled,
Check from data dependencies. Whether or not outer loop unrolling is possible is the same as whether or not loop switching of the multiple loops is possible. This is a known technique, for example, Yoshikazu Tanaka, Kyoko Iwasawa, "Compiling Techniques for Vector Computers" 31, No. 6, pp. 736-743 (1990). In the source program of FIG.
Since the same result can be obtained even if the loops of 0 (20) and DO10 (21) are exchanged, the outer loop can be expanded.

In step 56, the number of outer loop expansions is determined, and outer loop expansion is performed on the intermediate language. Ceil in the example shown
(75/40) = Double expansion is performed to obtain a result as shown in FIG. Here, the language expressed in Fortran-like is used as the intermediate language. DO20 (60) and DO1
0 (61) is a multiplex loop expanded twice with respect to the outer loop, and DO11 (62) is a residual loop expanded twice with respect to the outer loop. Hereinafter, the remaining loop will be omitted for simplicity. By the judgment 57, the above processing is performed for all the multiplex loops.

Thereafter, in FIG. 1, the processing of the optimizing unit 6 for ordinary intermediate language is performed, and code generation 8 is performed. FIG. 9 and FIG. 1 show parts related to efficient concealment of the main memory access penalty in the multiplex loop in the code generation unit 8.
0 is shown.

A process 90 selects a prefetch target load operand in the innermost loop. The selection method is
For example, the aforementioned document ACM 0-89791-535-6 / 92 which is a known technique
/ 0010/0062 Follow pp.62-73. As a result, DO1 in FIG.
It is assumed that b (i, j) and b (i, j + 1) in 0 are prefetch target operands.

The process 91 finds a loop interval in which prefetch instructions are to be inserted for all prefetch target operands, and finds their greatest common divisor. Since the cache line size is 32 bytes, when b (i, j) is prefetched, continuous 32 bytes of data including b (i, j) are prefetched. If b (i, j) is at the head of the cache line, b (i, j), b
(I + 1, j), b (i + 2, j), b (i + 3, j)
, The prefetch instruction may be issued once every four loops. Similarly, b
(I, j + 1) may be performed once in four loops. b (i,
Since the intervals at which the prefetch instructions for j) and b (i, j + 1) are to be inserted are 4, respectively, the loop interval at which the prefetch instructions are issued is LC = 4, which is the greatest common divisor as a whole.

In the process 92, the loop range of the innermost loop is divided into two. As described in the box describing this processing, the loop length in the latter half of the loop is either a loop length that makes the execution time longer than the main memory access penalty, or a loop length that is shorter and longer than the main memory access penalty. If not, the original loop length is set, and the processing in the first half of the loop is left. Therefore, the first half loop may not be executed.

The execution estimation cycle per loop of DO10 (61) in FIG. 8 is 2 (= max (ceil ((2 + 2)
/ 2), ceil (2/2)), LC = 4, the prefetch instruction is issued for b (i, j) and b (i, j + 1), so the execution cycle by the prefetch instruction is 1.
Therefore, the estimated execution cycle when the innermost loop is executed LC times is 9 cycles. Therefore, the loop length of the latter half loop is min (the original loop length, ceil (75 /
9)). As a result, DO10 (61) in FIG.
First half loop DO10 (65), second half loop DO in FIG.
11 (66).

In FIG. 11, the first half loop DO10 (6
5), the latter half loop DO11 (66) is shown by the structure of the DO loop. If this is left as it is, there is a level gap with the actual object code, so that an intermediate language expression in which the innermost loop is close to the machine language level is shown in FIG. Here, the sentence 70-sentence 78 is the first half loop DO in FIG.
The sentence 80-88 corresponds to the latter half loop DO11 (66) in FIG.

Here, sentence 71, sentence 72, sentence 73, sentence 7
6, sentence 77 and sentence 78 mean the processing of the DO loop 10. The loop processing length to be processed is set to the variable cnt at 71, reduced by one at sentence 76, and repeated at sentence 77. Statement 74 is the original processing in the loop body, statement 70 is the initial setting of the loop control variable, and statement 75 means the update of the loop control variable.

Similarly, sentence 81, sentence 82, sentence 83, sentence 8
6, sentence 87 and sentence 88 mean the processing of the DO loop 11. The loop processing length to be processed is set to the variable cnt by 81, reduced by one at sentence 86, and repeated at sentence 87. Statement 84 is the original processing in the loop body, statement 80 is the initial setting of the loop control variable, and statement 85 means the update of the loop control variable.

Proceeding to FIG. 10, a process 93 performs code generation for the first half loop. First, a prefetch instruction for the latter half of the inner loop is inserted. Statement 10 in FIG.
0, sentence 101 and sentence 102 are this code. Sentence 100
Calculates the address of the data required before the ceil (75/9) times in the inner loop. Statement 101 is a prefetch instruction, and statement 102 is an address update code for issuing a prefetch code every LC times. Next, the loop body code is copied and inserted three (= LC-1) times. The loop body sentence 74-77 in FIG. 12 is duplicated to become sentence 103-sentence 106 and sentence 107-sentence 110. Loop jump judgment code statement 77, statement 106, statement 110 jump destination
lab1 (sentence 73) is changed to lab2 (sentence 78) immediately after the loop. Then, the code of the loop body is copied again and inserted into the sentences 111-114.

A process 94 generates a code for the latter half loop. The difference from the first half loop is that in the first half loop, the first address of the operand to be prefetched is required in the first half of the inner loop processing of the next outer loop for the data required in the second half of the inner loop processing in the outer loop. This is the data that First, a prefetch instruction is inserted for data needed in the next outer loop. The sentences 120, 121, and 122 in FIG. 14 are the codes. The statement 120 calculates the address of the data required in the next outer loop. Statement 121 is a prefetch instruction, and statement 122 is an address update code for issuing a prefetch code every LC times. Next, the loop body code is copied and inserted 3 (= LC-1) times. FIG.
The loop body statement 84-87 in step 2 is duplicated and the statement 123-
Sentence 126 and sentence 127-sentence 130. The lab 3 (sentence 83) at the jump destination of the loop end determination code statements 87, 126, and 130 is changed to lab 4 (sentence 88) immediately after the loop.
Then, the code of the loop body is duplicated again, and the statement 13
Insert 1-134.

A process 95 inserts an initial prefetch instruction at the entrance of the multiple loop. This is the sentence 140 in FIG. That is, the data required at the beginning of the first inner loop during the first outer loop iteration is prefetched here. However, this prefetch is a part where the main memory penalty cannot be concealed because it cannot overlap with other processing. J = 1, i in FIG.
= 1,2,3,4,5.

[0039]

According to the code generation method of the present invention, even in the case where the data area to be accessed exceeds the cache capacity in the multiplex loop, the inner loop processing is divided into two loops, and the data necessary for the first half loop is one before. Since the prefetch of data is started in the latter half loop when the outer loop is repeated, and the data required in the latter half loop is started in the first half loop, the main memory penalty can be concealed.

For example, in the conventional method, as described above, the inner loop length N is set to 10 without depending on the outer loop length M.
If 0, 40% of the total time is waiting for data,
When the inner loop length N is 50, 56% of the total time
Was waiting for data. On the other hand, according to the embodiment of the present invention, the innermost loop length is 9 (= ceil (75/9)).
If so, the main memory penalty can be completely hidden in the second and subsequent processes except for the first process of the outer loop. That is, in both cases where the inner loop length is 100 or 50,
If the outer loop length is very large, no data wait condition occurs. When the outer loop length is 50, when the inner loop length is 100, 50, 1.3% of the total time,
When 2.6% is waiting for data and the outer loop length is 10, when the inner loop length is 100 and 50, 6.25% and 11.8% of the total time are waiting for data. And can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an entire compiler.

FIG. 2 is a diagram showing an example of a source program.

FIG. 3 is a diagram showing a code example after inner loop expansion according to a conventional method.

FIG. 4 is a diagram showing a code example using a prefetch instruction in a multiple loop according to a conventional method.

FIG. 5 is an explanatory diagram showing a state of execution by a conventional method.

FIG. 6 is an explanatory diagram showing a state of execution according to the present invention.

FIG. 7 is a processing flow diagram of an unrolling method of an outer loop of a multiple loop according to the present invention.

FIG. 8 is a diagram showing a code example after the outer loop is expanded according to the present invention.

FIG. 9 is a flowchart of a prefetch code generation process in a multiplex loop according to the present invention.

FIG. 10 is a flowchart of a prefetch code generation process in a multiplex loop according to the present invention.

FIG. 11 is a diagram showing a code example after loop division according to the present invention.

FIG. 12 is a diagram showing a code example close to a machine language after loop division according to the present invention.

FIG. 13 is a diagram showing a code example using a prefetch instruction in a multiple loop according to the present invention.

FIG. 14 is a diagram showing a code example using a prefetch instruction in a multiple loop according to the present invention.

[Explanation of symbols]

1. Source program, 2. Parsing unit, 3. Intermediate language,
4 ... Loop structure conversion unit, 5 ... Intermediate language, 6 ... Optimization unit, 7
... intermediate language, 8 ... code generation unit, 9 ... object code.

Claims (5)

[Claims] In a method of compiling a source program into an object program, in a case where each of the multiple loops is a loop whose number of times of execution is determined immediately before execution of the loop with respect to a multiple loop portion of the source program, When the outer loop is the loop 1 and the innermost loop is the loop 2 of the multiple loops, the loop 2
A code generation method for generating a prefetch code for transferring a part of data necessary for an operation in a cache to a cache at the time of the previous loop repetition processing with respect to the loop 1. 2. A method for compiling a source program into an object program, wherein, for each of the multiple loops of the source program, each of the multiple loops is a loop whose number of times of execution is determined immediately before the execution of the loop. When the outer loop is the loop 1 and the innermost loop is the loop 2 of the multiple loops, the loop 2
Is divided into two loop repetition ranges, each of which is a first half loop and a second half loop, the code of the second half loop includes the data necessary at the beginning of the operation of the first half loop in the next iteration of the loop 1 The pre-fetch code to be transferred to the cache and the original code, and the code of the first half loop transfers, to the cache, data other than the data transferred to the cache in the second half loop among the data required for the operation of the first half loop. A code generation method comprising a prefetch code to be executed and an original code. 3. The code generation method according to claim 2, wherein in the division of the loop repetition range of the loop 2, the number of repetitions of the latter loop estimates a processing time of the latter loop, and the processing time is cached from a memory. Estimated number of loop iterations determined to exceed main memory access penalty, which is the transfer time to
A code generation method characterized by setting a small number of repetitions among the number of loop repetitions of (1). 4. The code generation method according to claim 3, wherein the processing time of the latter half loop is estimated, and there is an estimated number of loop iterations in which the processing time exceeds a main storage penalty which is a transfer time from a memory to a cache. When the value is larger than the given reference value, analysis is performed to determine if loop unrolling can be performed for loop 1. If unrolling is possible, the processing time of the latter half loop after expansion is estimated. A code generation method for generating a code in which loop expansion for loop 1 is performed until the estimated number of loop repetitions exceeding a main memory access penalty, which is a transfer time, becomes smaller than the reference value. 5. The code generation method according to claim 2, wherein the number of loop repetition intervals required for the prefetch is determined, and the code of the latter half loop is used in the first iteration of the operation of the former half loop during the next repetition processing with respect to the loop 1. The prefetch code for transferring data required to the cache and the original processing code are duplicated for the number of expansions, and the code of the first half loop is one of the data required for the operation of the first half loop. A code generation method comprising a prefetch code for transferring data other than data transferred to the cache in the latter half loop to the cache and a code obtained by duplicating the original processing code by the number of expansions.