JPH06290057A - Loop optimizing method - Google Patents

Abstract

PURPOSE:To optimize a loop by a compiler for architecture having a function for invalidating the execution result of a previously executed instruction in accordance with judgement whether branching is to be executed by a succeeding condition branch or not. CONSTITUTION:A loop conversion selecting part 107 in a loop optimizing part 104 determines a loop converting method, and when an instruction for using an invalidating function is usable, a loop conversion executing part 108 converts a loop using the instruction to optimize the loop. Consequently the number of instructions or the number of registers to be used can be reduced without losing a convensional loop conversion effect, and even when the repeated frequency of the loop is not determined at the time of starting the loop, loop conversion can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to optimization by a compiler for an architecture having a function of invalidating an execution result depending on whether or not to branch in a subsequent conditional branch. It relates to a loop optimization method for improving speed.

[0002]

2. Description of the Related Art In many modern computers, particularly a reduced instruction set computer (RISC), pipeline processing is ideally performed for one instruction per cycle. However, in reality, it is difficult to issue a new instruction every cycle due to the dependency relationship between data and functional units.

It is said that there is a data dependency between an instruction and an instruction that refers to the execution result of the instruction. Such a dependency occurs, for example, when a value is set in a register or a condition code by loading data from a memory or arithmetic operation, and a subsequent instruction refers to the value. Instructions that have a dependency relationship cannot be changed in their execution order, and there is a restriction that the instruction on the referencing side must not start execution until the reference value is set. Further, when the functional units used by the two instructions compete with each other, the execution order of the instructions is not limited, but there is a constraint that the other cannot be executed while one is being executed.

Due to these restrictions, a mechanism for delaying the start of execution of a subsequent instruction when the subsequent instruction must not be executed immediately is called pipeline interlock (hereinafter abbreviated as interlock), which is an interlock. While the error occurs, the processor cannot start executing a new instruction, and there is a space in the pipeline where the instruction cannot be issued.

Regarding RISC and pipeline processing,
For example, J. L. JL Hennessy and D.H. A.
DA Patterson's Computer Architecture: An Qualitative Approach, Morgan
Published by Kaufman Publisher (Computer Architecture: A Quan
titative Approach, Morgan Kaufmann Publishers, Inc,
1990 (reference 1)).

The execution time of the program can be shortened by optimizing the instruction execution number per clock cycle by generating an instruction sequence that reduces the empty space of the pipeline during execution.

Among such optimizations, the local instruction scheduling reduces the pipeline vacancy due to the interlock by rearranging the instructions in the basic block within the range that does not change the meaning of the program. However, the basic block is an instruction series that does not include a branch instruction or an instruction to be a target of branch in the middle. Therefore, in the local instruction scheduling, only the instructions in one basic block are targeted at a time, and the instructions are rearranged only in the instructions. This optimization is generally performed on an intermediate language that corresponds to the machine language in a nearly one-to-one manner, or on the machine language itself. In the case of the intermediate language, physical register allocation is performed after physical register allocation and physical register allocation is performed. It may be done before, or both.

The following literature is available as a survey on local instruction scheduling for pipelines. S.
M. A Brief Survey of Papers on Scheduling for Pipelined Processors from SM Krishnamurthy,
Sigplan Naughties 25, No. 7 (A BriefSur
vey of Papers on Scheduling for Pipelined Processo
rs, SIGPLAN Notices, Vol.25, No.7), 1990 (reference 2).

However, in a general program, the parallelism existing in the basic block is limited, and the interlock cannot be completely avoided only by the local instruction scheduling. Furthermore, superscalar, super pipeline, VLIW (Very Long Instruction Word)
In a computer such as a computer capable of executing more than one instruction per cycle, the local instruction scheduling alone cannot provide sufficient parallelism. Local instruction scheduling for superscalar processors is described in: M. S.
MSLam Instruction Scheduling for Superscalar Architecture Annual Review on Computing Vol. 4 (Instruction Scheduling for Superscalar Archi
tectures, Annual Reviewson Computing, Vol.4), 199
0 (Reference 3), pages 183 to 184. M. Johnson
(M.Johnson) Superscalar Microprocessor
Design, published by Prentice Hall ("Superscalar M
icroprocessor Design ", Prentice Hall), 1991 (Reference 4), pages 177 to 202.

For the above reasons, instruction scheduling beyond basic blocks, which is called global instruction scheduling, has been studied and put into practical use in recent years. They are roughly classified into those for a loop and those for a plurality of basic blocks that are not loops.

First, software pipelining and loop unrolling are typical optimizations for loops. Both of these allow instruction scheduling across multiple iterations of the loop. For details, see pages 187 to 193 of (Reference 3), 2 of (Reference 4).
Pp. 13-229. These optimizations have drawbacks such as an increase in the number of static instructions and an increase in execution time when the number of iterations is small.

Various schedulings for a plurality of basic blocks that are not loops have been proposed. A typical example is trace scheduling. Trace scheduling is described in (Reference 1) pages 325 to 328, (Reference 3) pages 184 to 187, and (Reference 4) pages 205 to 213 and 229 to 2
It is described on page 33. In trace scheduling, the loop schedules only in that one iteration.

Other global instruction scheduling is disclosed in, for example, Japanese Patent Laid-Open No. 4-263331.

An important concept in global instruction scheduling is speculative instruction movement. Speculative instruction movement is, for example, movement of an instruction in a basic block of one branch destination of a conditional branch to a basic block having the conditional branch instruction. The moved instruction will be executed regardless of the branch destination of the conditional branch. Therefore, when branching to the other, an instruction that does not need to be executed is executed, and therefore an instruction whose execution result is changed cannot be moved. Instructions so moved are called speculative instructions.

If sufficient parallelism cannot be obtained in a basic block B1, an instruction in the subsequent basic block B2 can move to B1 without changing the meaning of the program and without increasing the execution time of B1. If there is one, it can be expected that the execution time of B2 is reduced by speculatively moving the instruction to B2. However, the types of commands that can be speculatively moved are usually limited. This is because moving an instruction that can cause an exception across a branch causes an exception that would not occur when branching in another direction at execution. Instructions in which such an exception occurs generally include memory access instructions, floating point arithmetic instructions, and integer division instructions. Therefore, as a simple method, there is a method in which those instructions do not move beyond the branch instruction. However, it is not possible to obtain sufficient parallelism because there are few instructions that can be moved.

There are two ways to solve the problem. One is to prevent the exception from occurring and the other is to delay the detection of the exception. The former method prepares an instruction that can cause an exception but does not cause an exception, and when speculatively moves, replaces it with an instruction that does not cause an exception corresponding to the original instruction. is there. This method has the drawback of not being able to detect exceptions correctly. The latter, that is, methods for delaying the detection of exceptions include boosting and sentinel scheduling. By adding hardware that supports speculative instruction execution and exception handling, these methods speculatively move even the instruction causing the exception and handle it correctly when the exception occurs. can do.

Regarding the execution of these speculative instructions, S.
A. Sentinel Scheduling Forbuyer IW and Superscalar Processors, Aspors-V by SA Mahlke et al.
Proceedings (Sentinel Scheduling for VLIW
and Superscalar Processors, ASPLOS-V Proceedings),
Pages 238 to 247 (Reference 5) of 1992, and M.M.
D. Efficient Superscalar Performance Through Boosting, Ess-V Proceedings (Efficient) by MDSmith et al.
Superscalar Performance Through Boosting, ASPLOS-V
Proceedings), 1992, pp. 248-259 (reference 6). These documents use speculative instructions for global scheduling within blocks that do not contain loops.

As an example of conventional loop optimization, C in FIG.
Consider compiling a piece of program written in a language. This program multiplies the value of each element of the array a by the value of the variable b and makes it the new value of the element (that is, the vector is scalar-multiplied). The number of loop iterations is given by a variable n whose value is determined at run time.

Assuming that the object code of the compiler is an assembly language, if optimization other than loop conversion is performed, the result shown in FIG.
It can be compiled into the code shown in.

The meaning of this assembly language will be described below.

First, sp, r0 to r5 are 32-bit general-purpose registers, fr0 to fr5 are 64-bit floating point registers, of which r0 and fr0 always have a value of 0.

In the program of FIG. 3, each register is used for the following purposes. sp: Stack pointer. Each variable is allocated in the stack. r0: Always has a value of 0. A value obtained by multiplying the value of r1: n by 8 is preset. r2: Holds the value of i. r3: Holds the address of a [0]. The value of fr1: b is preset. fr2: Holds the value of a [i]. fr3: Holds the product of a [i] and b.

Further, disp_a in (3) is a [0].
Position relative to the stack pointer of L, and L $ 1 and L
$ 2 is the label, and the memory is addressed in bytes.

The processing executed by each instruction written in assembly language, which is also used in the embodiment, is as follows. mov r, q ... r, q are general-purpose registers, and copy the value of r into q. ld r (q), f ... r, q are general-purpose registers, f is a floating point register, and a load that transfers 8-byte data starting from an address obtained by adding the value of r to the value of q to the target register f order. st f, r (q) ... f is a floating point register, r and q
Is a general-purpose register, and is a store instruction for transferring the content of f to the address obtained by adding the value of r to the value of q. i i, r, q ... i are positive constants, r and q are general-purpose registers, and the values of i and r are added to obtain the value of q. and i i, r, q ... i are integer constants, r and q are general-purpose registers, and the bitwise logical product of the values of i and r is taken as the value of q. mul f, g, h ... F, g, h are floating point registers, and the product of the value of f and the value of g is the value of h. com r, q ... r, q are general-purpose registers or floating-point registers, and are comparison instructions that compare the values of r and q as signed integers and set the condition code. ble L ... L is a label, and r in the above com command
A conditional branch instruction that branches to L when> = q. bgt L ... L is a label, and r in the above com instruction
Conditional branch instruction that branches to L when <q. bge L ... L is a label, and in the above com command, r
Conditional branch instruction that branches to L when <= q. bne L ... L is a label, and in the above com command, r
A conditional branch instruction that branches to L when and are not equal. beq L ... L is a label, and r in the above com instruction
A conditional branch instruction that branches to L when and q are equal. bnz L ... L is a label, and in the above andi instruction,
A conditional branch instruction that branches to L if the logical product of each bit is not 0. bra L ... L is a label, and is an unconditional branch instruction that branches to L.

As an example of a processor that executes this assembly code, consider the following simplified RISC. One instruction can be executed in one cycle by hardware pipeline processing. The latency of the instruction (the number of cycles from issuing the instruction to completing it) is 2 for the load instruction, 4 for the floating point add / subtract instruction,
Others are set to 1. This means that, for example, the value of the target register of the load instruction can be referenced after two cycles, and if an instruction immediately after the load instruction attempts to reference the target register, a one-cycle interlock occurs.

At this time, when n of the above-mentioned assembly code is sufficiently large, the execution time per iteration of the loop is 10 cycles per iteration. This takes 1 cycle each to execute 6 instructions, plus ld
1 cycle between instruction (201) and mul (202) instruction,
This is because an interlock of 3 cycles, that is, 4 cycles in total, occurs between the mul instruction (202) and the st instruction (203). This is the case of the scalar processor, but the ratio of interlock becomes higher in the case of superscalar or VLIW.

This program uses three general-purpose registers and three floating-point registers in the loop.

Software pipelining, one of the loop optimization methods, increases instruction level parallelism and reduces interlocks. However, when implementing software pipelining for this program, it is necessary to use loop unrolling and register renaming together, as described on pages 225 to 229 of (Reference 4).

Loop unrolling is a method of transforming a loop so that multiple iterations of the original loop are processed in a single iteration.

Register renaming is a method of changing the dependence of registers by reallocating them to facilitate scheduling. In particular, when the same data is reassigned to another register during execution, a copy instruction from the initially assigned register to the newly assigned register is generated.

FIG. 4 (first half) and FIG. 5 (second half) show the same source program subjected to those loop optimizations. In this case, in addition to software pipelining, one-time loop unrolling and register renaming are used together. In this case, the pipeline processing by software pipelining is composed of two stages.

In a two-stage pipeline, the first stage of the first iteration must be executed before executing the pipelined loop, the code for which is called the (pipeline) prolog. . Similarly, the second stage of the last iteration needs to be executed after the loop, and the code for that is called the epilogue (of the pipeline).

When the pipeline has two stages and is unrolled once, the first stage instruction is executed once in the prologue and twice in each iteration of the loop, and the second stage instruction is executed in each loop. It is executed twice in iterations and once in the epilogue. Therefore, the pipelined loop executes an odd number of three or more of the original iterations.

When the number of iterations of the original loop is less than 3, the pipelined loop cannot be executed, and when the number of iterations is even, one execution needs to be executed separately from the pipelined loop. There is.

FIG. 6 shows a flowchart of the processing of the assembly code shown in FIGS. 4 and 5.

The outline of each processing of the assembly code and the corresponding flowchart will be described below. Four
In 01, when the number of loop iterations is 0, the following processing is not performed and control is passed to the next processing. In 402, when the number of loop iterations is three or more, the pipelined loop is executed, and when it is less than three, a determination for executing the original loop is made. In 403, it is executed as an original loop without loop conversion. At 404, one iteration is processed when the original loop has an even number of iterations. 405 is a pipeline prologue. 40
Reference numeral 6 is a pipelined loop. 407 is
It is an epilogue of the pipeline.

The execution time of this pipelined loop is 1 because interlocks are completely avoided.
It takes 12 cycles to execute two instructions. This is 6 cycles per original iteration. Similarly, there are 5 general-purpose registers and 5 floating-point registers.
The number is 2 and the number is increased by 2 by register renaming. The number of static instructions in the entire loop (the number of instructions in the target code, which does not consider the execution frequency) is increased from 35 instructions to 10 instructions. In this, there are less than 3 iterations, one iteration of the original loop for an even number of iterations, and an unrolled and pipelined loop. The code for is included. Therefore, the number of instructions is generally three times or more the original number.

When the number of iterations is small, there is overhead such as whether or not to execute the loop-transformed code, so that not only the number of static instructions but also the execution time can be increased.

Further, the software pipe lining is
It is often necessary to use loop unrolling and register renaming together, and loop unrolling increases the number of static instructions and register renaming increases the number of registers used.

In addition, such optimization cannot be performed when the number of iterations cannot be known at the start of loop execution because the loop termination condition depends on the execution result of each iteration. .

[0041]

In the optimization of the loop as described in the prior art, the number of static instructions and the number of registers used increase. Furthermore, conventionally, these optimizations could not be performed unless the number of executions was determined at the start of execution of the loop.

It is an object of the present invention to provide a method of using fewer speculative instructions and fewer registers to be used by using speculative instructions when optimizing a loop.
It is to be able to perform loop optimization even when the number of executions is not determined at the start of the loop.

[0043]

The present invention is a compiler for converting a program written in a high-level language into a machine language, an assembly language, or another high-level language, and the converted program executes speculative instructions. A method for optimizing a loop using its speculative instructions when executed on a processor.

As a conventional technique, there is the following loop conversion method. The number of iterations of a loop is known at the beginning of the loop, and it is stored in n from 0 to n-1.
If i, j, p, and q are non-negative integers, the i-th (0 <= i and i <= n−1) iteration of the converted loop starts from the i + p-th iteration of the original loop. Convert to perform all or part of one or more iterations out of (q-p + 1) iterations up to the i + qth iteration. An example is software pipelining.

The present invention performs the following operations in such loop transformation according to the target architecture.

First, in the case of an architecture in which it is possible to select whether or not to detect an exception caused by the execution of an instruction, depending on whether or not one or more subsequent conditional branch instructions branch to the instruction, respectively. Do the following:

When the number of loop iterations is known at the start of loop execution, 1 <= t and t <in the loop transformation.
For all t = q-p, all s for which s <= t
Then, there is an instruction to perform the i + sth processing of the original loop,
If the instruction can cause an exception, the instruction is replaced with a corresponding instruction that is detected only when conditional branch instructions forming a loop branch s consecutive times. Further, the number of loop iterations is n−q + t.

Further, although it is known that the loop loops p + 1 times or more, but it is not known how many times the loop is performed at the start of execution of the loop. Perform replacement and perform loop transformation.

Next, depending on whether or not one or more subsequent conditional branch instructions branch to an instruction, the execution result of the instruction is written to the register, the condition code, the memory, and the execution occurs. For architectures that allow you to choose whether or not to detect exceptions, do the following:

When the number of loop iterations is known at the start of loop execution, 1 <= t and t <in the loop transformation.
= T-q-p for all s for which s <= p + t, when the conditional branch instruction forming the loop continuously branches s times for the instruction performing the i + sth processing of the original loop Replace with an instruction that only writes the result. At the same time, refer to the execution result of the instruction with the above replacement,
Before the branch of the conditional branch is performed, if the instruction that references the execution result of the replaced instruction is in the same iteration, it is replaced with the instruction that references the execution result. Further, the number of loop iterations is n−q + t.

Further, although it is known that the loop loops p + 1 times or more, but it is not known how many times the loop is performed at the start of execution of the loop. Perform replacement and perform loop transformation.

[0052]

[Operation] The following can be said for both architectures.

In the i-th iteration of the transformed loop, when n-q + 1 <= i and i <= n-q + t, the processing up to the (n-1) -th time in the original iteration and the n-th and subsequent processes not originally necessary are performed. However, according to the present invention, even if an exception occurs, this processing is not performed because it is not executed.

Therefore, according to the present invention, the processing of the n-1th iteration in the original iteration executed in this range in the transformed loop needs to be separately generated as an epilogue. You can now execute the instruction within, so you no longer need to generate an epilogue.

In particular, in an architecture capable of delaying writing of execution results, registers, condition codes,
By delaying writing to memory, it is possible to avoid breaking the dependencies that may occur due to the processing of multiple iterations of the original loop, eliminating the need for loop unrolling and register renaming.

When the number of iterations of the loop is not determined at the start of the loop, when the ending condition is satisfied in the i-th iteration after conversion, the original i + 1th and subsequent processings already executed are processed to the next conditional branch. Since it is invalid because it does not branch with, the correct result is obtained.

[0057]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an example of an architecture on which optimization according to the present invention is based will be described. In this example, it is assumed that the processor used in the example described in the related art has the function of supporting speculative execution as follows.

There are two types of register files, a general-purpose register and a floating-point register, which have 32 bits and 6 bits, respectively.
It is assumed that 4-bit data can be stored, and each of them can store 2 bits.
Prepare a group. One set uses a conventional register set as it is, and this is called a table register. The other set is called a back register and is constructed as follows.

Each register has a bit (valid bit) indicating whether or not the register is valid and a bit (exception bit) indicating whether or not an exception occurs, in addition to the area for storing a value. The front and back are numbered the same.

The instruction set is changed as follows. A bit indicating whether it is a front register or a back register is added to each register referred to by each instruction. In the assembly code, for each register, ".B" is added after the register name to specify the back register.

For example, if the target register is turned to make the floating-point number load instruction ld r2 (r3), fr1 speculative, ld r2 (r3), fr1. It becomes B. The instruction that uses the back register is a speculative instruction. Note that, here, for the sake of simplicity of explanation, it is assumed that an instruction that refers to the back register cannot change the value of the front register.

Speculative instructions are executed as follows.

In the initial state, the valid bit of each back register is set to 0, which means invalid, and the exception bit is set to 0, which indicates that no exception has occurred.

The operation of each instruction is processed as follows depending on whether the register is referenced or written.

When writing a value to a register, whether it is the front or the back is written in a designated register set. At this time, if an exception occurs in the operation, it will be processed immediately in the case of the front register, but in the case of the back register, the address of the instruction in which the exception occurred will be written to the exception register of the register To If no exception occurs, the value is written to the specified back register and the valid bit is set to 1.

Since the reference of a register is clearly indicated in the instruction word whether it is front or back, a designated register set is used.
When referring to the back register, if the exception bit of the register is 1, and the instruction writes a value to the register, the exception register of the instruction in which the exception bit occurred is the value of the reference register with the exception bit of 1 in the register to be written. Copy the address and set the exception bit to 1.

The conditional branch instruction is assumed to perform static branch prediction by hardware. That is, when the branch destination is forward as in the if statement, it is predicted that the branch is not taken, and when the branch destination is backward as in the loop, it is predicted that the branch is taken. When executing a conditional branch instruction, processing for validating and invalidating the speculatively executed instruction based on branch prediction is performed. If the branch prediction hits, in the back register,
If there is an exception bit of 1, the exception processing is performed. If there is no exception bit, the value of the effective bit of 1 is copied to the corresponding table register, and all the effective bits and the exception bits are set to 0. This processing is assumed to be performed immediately before the execution of the branch destination instruction. Therefore, the instruction in the branch slot of the conditional branch instruction is referred to and written in the register before the back register is invalidated or copied to the front register.

The optimization method according to the present invention, which is based on such an architecture, will be described below.

First, the configuration of the compiler is shown in FIG. A compiler is a source program written in a high-level language,
Convert to target processor assembly or machine language. There are also those that convert a high-level language into another high-level language.

The processing of the compiler can be roughly classified as follows. Lexical analysis unit 101, semantic analysis and intermediate language generation unit 102, optimization unit 103, object code generation unit 1
It is 10. The optimization unit is an intermediate language generated by the parsing unit,
Alternatively, another intermediate language obtained by further converting it is converted so as to reduce the execution speed or the size of the object code without changing the meaning of the program.

The processing performed by the optimizing unit is generally performed by moving a loop invariant expression, optimizing at the stage of the source program such as constant propagation, optimizing depending on the target machine such as strength reduction, or the like. Includes optimizations that include both.

Hereinafter, of the optimizing unit, a portion for optimizing the loop for implementing the present invention will be described.

The structure of the loop optimization unit is shown at 104. First, the loop structure is detected from the intermediate language 105, and the degree of occurrence of interlock is evaluated 106,
Decide whether to apply a loop transform, and if so, select one or more applicable combination of loop transforms 107, depending on the selected loop transform,
Perform 108 the transformation of the loop on the intermediate language.

It is also possible to perform another loop transformation 109 on the loop that has undergone the loop transformation 109.

The loop conversion implementation unit 108 also includes the following processing. If the selected conversion cannot be performed alone, then the conversion combined with other conversions is performed. If the transformed loop can only execute the iterative function under certain conditions, the code to execute the original loop when the conditions are not satisfied, or the preprocessing to satisfy the conditions Including code generation for.

In this example, the selection unit for loop transformation and the loop transformation unit are different from the above conventional method.

The loop conversion selecting unit 107 considers that a speculative instruction can be used when selecting a loop. This may allow conversions not previously possible.

The loop conversion unit uses the converted instruction sequence and its pre-processing and post-processing, and the instruction sequence of the original loop when it cannot be executed in the converted loop, and speculative instructions if necessary. To generate.

Hereinafter, a detailed description will be given based on an example of software pipelining described in the prior art.

Consider pipelining a program written in the C language of FIG. An intermediate word corresponding to the machine word assigned to the logical register and the one-to-one correspondence is input to the loop optimization unit.

FIG. 7 shows the flow of processing in the case of software pipelining in this embodiment. In this figure, the number of iterations of the original loop is n and the number of pipeline stages is 2.
The processing at the stage is shown.

When there is no branch or function call in the loop and the interlock is a certain value or more, the software pipelining is selected by the selection unit of the loop conversion. In the prior art, software pipelining could not be performed unless the number of loop iterations was determined at the beginning of the loop, but the present invention does not have such a restriction.

First, at 701, the loop body instructions are rearranged so that the interlock is minimized. In the case of the program of FIG. 2, the program before conversion is the one shown in FIG. 3, so the instructions can be rearranged as shown in FIG. At this time, the dependency relationship determines the number of stages of the pipeline and which stage each instruction performs. An example of the method is described on pages 220 to 225 of (Reference 4).

In the case of FIG. 8, the pipeline is composed of two stages, 801, 802 and 804 compose the first stage of the pipeline, and 803, 805 and 806 compose the second stage. So, in the ith iteration of the loop of Figure 2,
While 803, 805, and 806 perform the original i-th iteration process, 801, 802 and 804 perform the i + 1-th iteration process. Therefore, if physical registers are assigned according to the logical register numbers, then 801 and 803, 801
And 805 break the data dependency.

In order to avoid this, in the conventional technique, as described above, the loop unrolling is performed once and the register renaming is performed.

In the present invention, by replacing the instructions 801, 802, 804 for performing the first stage processing in 702 with speculative instructions, the reflection of the results of these processing is delayed until the time of entering the next iteration. This solves the above problem. The replacement to the speculative instruction performed here replaces the target register with the corresponding back register for each instruction of the first stage, and replaces the instruction that refers to the same register with the instruction that refers to the same back register in the subsequent instruction. It is to replace. Since the use of this back register is the same as performing register renaming for the back register, the usage of the front register does not increase. Furthermore, it is not necessary to perform loop unrolling, and it does not matter whether the number of iterations is odd or even.

Generally, when the pipeline has k stages, the instruction belonging to each i stage where 2 <= i <= k is k
The conditional branch instruction forming the loop is replaced with a speculative instruction that becomes valid when branching k-i times so that the execution result becomes valid after -i iterations. However, in the architecture of this example, speculative execution can be performed only for the conditional branch immediately after, so even if three or more stages of pipelining are performed, only the first stage is speculatively executed. Therefore, in pipelining with three or more stages, if the number of executions is unknown at the start of loop execution, pipelining cannot be performed, and in that case, loop conversion is not performed. Hereinafter, only the processing when the pipeline has two stages will be described.

Next, at 703 and 704, the number of iterations is determined and the pipeline prolog code is generated. As the prologue, the first-stage instructions 801, 802, 804 are generated in the first iteration of the original loop as in the conventional case.
Conventionally, the number of iterations of the loop after the conversion is set to n−1, and the instruction 803 excluding the instruction for the loop is generated as the epilogue from the second-stage instruction in the original n-th iteration.
In the present invention, assuming that the number of iterations is n, even if the original n + 1th first-stage instruction is executed nth time, they are speculative.
Since it is invalid because there is no next iteration, there is no problem even if the number of iterations is set to n and the instruction in the second stage performs processing for the (n + 1) th iteration in the original loop. Therefore, no epilogue is generated.

In this case, when the number of iterations is one or more, it can be executed in a pipelined loop. This is because the loop unrolling has not been performed, so that the processes other than the first stage process in the prologue and the second stage process executed in the first iteration can be invalidated. For the same reason,
If the number of iterations is one or more, the number of iterations need not be known in advance. Therefore, since the constraint on the number of iterations is one or more, a code that does not execute the converted loop when the number of iterations is 0 is generated 705.

The target program generated by the above processing is shown in FIG.

In this program, the number of instructions is 1 before conversion.
There are 13 instructions that are 0 instructions plus 3 prologue instructions.
Since the interlock no longer occurs, it can be executed in 6 cycles per iteration.

The newly used registers are two general-purpose registers and two floating-point registers, respectively. However, the number of table registers used does not increase.

FIG. 10 shows how the program is executed. Reference numeral 1001 indicates a prologue instruction, and 1002 indicates a pipelined loop instruction with operands omitted.

When the number of iterations of the original loop is 3,
The processing in the first, second, and third iterations is 100
3,1004,1005. Although 1006 corresponds to the process of the fourth iteration in the original loop, the process of 1006 is invalidated because the conditional branch of 1005 does not branch.

As a second embodiment, a case where the number of loop iterations is not determined at the start of the loop will be described. FIG. 11 shows an example of such a source program. In the prior art, this program could not be software pipelined. Also in this case, the assembly code shown in FIG. 12 is converted by the method described in the above embodiment.
At that time, it is not necessary to change the loop termination condition. The loop can be executed by this converted code when the number of iterations is one or more.

[0096]

According to the present invention, firstly, the number of static instructions is reduced. As shown in the example, this is because the loop unrolling and register renaming are not required, the epilogue is not required, and it can be applied to one or more loops. This is because the number of instructions required is three times or more the number of instructions, but according to the present invention, the same processing can be realized with a slight increase in the number of instructions.

Secondly, the number of registers used is reduced.
However, this is an effect when another register set is provided for speculative execution, and at that time, the number of normal registers used is the same as when the loop conversion is not performed.

Third, loop transformation can be performed even if the number of loop iterations is not determined at the beginning of the loop. This is because even if some of the instructions are executed excessively, it is possible to cancel their effect or prevent an extra exception.

[Brief description of drawings]

FIG. 1 is a flowchart of a compiler that implements loop optimization of the present invention.

FIG. 2 is an explanatory diagram of an example of a source program written in C language.

FIG. 3 is an explanatory diagram of an example of an object code when the program shown in FIG. 2 is compiled without performing loop optimization.

FIG. 4 is an explanatory diagram showing the first half of an example of the target code when the program shown in FIG. 2 is compiled by performing loop optimization.

5 is an explanatory diagram showing the latter half of the example of the target code when the program shown in FIG. 2 is compiled by performing loop optimization.

6 is a flowchart showing the processing of the programs of FIGS. 4 and 5. FIG.

FIG. 7 is a flowchart of a process of an embodiment of software pipelining according to the present invention.

FIG. 8 is an explanatory diagram showing the instructions of the loop body of FIG. 3 rearranged so that the execution time is minimized.

9 is an explanatory diagram of an object code of the program of FIG. 2 according to the present invention.

FIG. 10 is an explanatory diagram showing how the program of FIG. 9 is executed.

FIG. 11 is an explanatory diagram showing an example of a program in which the number of loop iterations is unknown at the start of loop execution.

12 is an explanatory diagram of the object code of the program of FIG. 11 according to the present invention.

[Explanation of symbols]

801, 802, 804 ... Instructions using the invalidation function generated by the present invention.

Claims (12)

[Claims] 1. A function for invalidating a part or all of an execution result of a designated instruction depending on whether or not a branch is caused by one or more conditional branch instructions executed after the instruction. In a compiler that generates a target code to be executed in a processor having the source code of a program written in a computer language, an instruction having the invalidating function is included in a target code generated for a loop in the source code. By using it, it is possible to suppress the generation of some or all of the loop pre-processing instruction sequence, post-processing instruction sequence, and loop body instruction sequence that are generated when the invalidation function is not used. A characteristic loop optimization method. 2. The method according to claim 1, wherein the invalidating function branches an exception caused by execution of a designated instruction by one or more conditional branch instructions executed after the instruction. The pre-processing instruction sequence of the loop, the post-processing instruction sequence, and the instruction sequence of the loop body, which are generated when the invalidating function is not used, when realized by performing after determining Loop optimization method that suppresses the generation of some or all of 3. The invalidating function according to claim 1, wherein the writing to the register, the condition code, the memory, and the exception processing which are caused by the execution of the designated instruction are executed after the instruction. After determining whether or not one or more conditional branch instructions branch, if realized by performing them, the pre-processing instruction sequence of the loop, the post-processing instruction sequence, and the instruction sequence of the loop body, respectively. Loop optimization method that suppresses the generation of some or all of 4. The invalidating function according to claim 1, wherein the execution of the writing to the register, the condition code, the memory, and the exception processing, which are caused by the execution of the designated instruction, is executed after the instruction. If one or more conditional branch instructions are implemented after it has been determined whether or not to branch, and even before the writing is performed, it is realized to have a means for referencing the value to be written. To
A loop optimization method for suppressing generation of a part or all of a preprocessing instruction sequence of a loop, a postprocessing instruction sequence, and an instruction sequence of a loop body. 5. The existing loop optimization method for a processor according to claim 1, wherein an integer i in a range and k integers p1 to pk arranged in ascending order without duplication are not optimized. Is divided into processes of k iterations of i + p1 to i + pk of the loop after optimization by dividing the processing of the i-th iteration of
For some integer q less than or equal to pk, i of the loop after optimization
2. If there is an instruction sequence for processing the i-th iteration of the pre-optimization loop at the + q-th iteration, the instruction sequence is used when the number of iterations of the loop after optimization is not i + q-p1 or more. Loop optimization method with an instruction sequence that is invalidated by the invalidation function of. 6. The loop according to claim 5, wherein the number of iterations of the loop before optimization is n, and the loop after optimization is a part of the (n + 1) th and subsequent iterations of the loop before optimization which are not originally necessary. Alternatively, a loop optimizing method for executing all the processes but optimizing such unnecessary processes by the invalidating means. 7. The invalidation function according to claim 1,
The loop optimization method according to claim 5, which is realized by the method according to claim 3 or 4. 8. The invalidation function according to claim 1 is realized by the method according to claim 4, and by using the referencing means according to claim 4, the invalidation function is not used. The loop optimization method according to claim 5, wherein the number of registers used is also reduced. 9. The loop optimization method according to claim 5, wherein the loop optimization method is software pipelining. 10. The loop optimization method according to claim 5, wherein the nullification function according to claim 1 is not used,
A loop optimization method for applying the loop optimization method by using the invalidation function, when the loop transformation cannot be performed because the number of loop iterations is not determined at the start of execution of the loop. 11. The loop optimization method according to claim 5, wherein the invalidation function according to claim 1 is used for a loop whose number of iterations is determined at the start of execution of the loop. When the loop optimization method is not executed when it is not repeated a certain number of times, the loop optimization is executed for a smaller number of iterations by using the invalidation function. A loop optimization method for generating a target code executed by an instruction sequence. 12. The loop optimization method according to claim 5, wherein the invalidation function according to claim 1 is used for a loop in which the number of iterations is determined at the start of execution of the loop. , The loop optimization method is not implemented by using the invalidation function when it is necessary to execute a part of the iterations by an instruction sequence that does not implement the loop optimization method depending on the number of iterations. A loop optimization method that produces less repetitive target code executed by a sequence of instructions.