JP2010186487A - Compiler apparatus and system therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly flexible compiler which allows a user to precisely control optimization by the compiler. <P>SOLUTION: The compiler includes: an analysis part 110 for detecting instructions (option and pragma) from a user to the compiler 100; and an optimization part 120 or the like comprising a processing part (global area allocation part 121, software pipelining part 122, loop unrolling part 123, if conversion part 124 and pair instruction generation part 125) for performing individual optimization processing specified by the option and the pragma by the user. When the instruction on guaranteeing that the number of times of repetition of specified loop processing is a set of values equal to or larger than a certain specified value in a source program is detected, the loop unrolling part 123 performs the optimization processing of suppressing the generation of an escape code to be needed when the number of times of the repetition is zero when the guaranteed set of the values is the set of the values ≥1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a compiler that converts a source program written in a high-level language such as C language into a machine language program, and more particularly to an instruction for optimization by the compiler.

  Conventional compilers are primarily made for control processing applications. In control processing applications, precise execution performance and code size tuning are not so much required. Rather, from the viewpoint of reducing development man-hours, users can select “performance priority”, “code size priority”, or “performance and Only rough instructions (such as options to be specified at compile time) such as "Balance of code size" are given, and most of the optimization strategy is left to the compiler.

  On the other hand, in the field of media processing applications where critical execution performance and code size are required, development is being conducted with the primary goal of realizing the required performance and code size by performing hand coding in assembly language. .

  However, in recent years, development man-hours have increased due to the increase and diversification of media processing applications, and application development using high-level languages has become necessary in the media processing field. For this reason, attempts are being made to develop media processing applications in high-level languages. At that time, the user expects that fine tuning can be performed even in high-level language development, and it is necessary to control in detail the optimization strategy performed by the compiler.

  Therefore, it is not a rough instruction as in the past, but ON / OFF and its degree are specified for each type of optimization by the compiler, and optimization is turned on / off in units such as variables and loop processing in the program. It is necessary to have fine-tuned control.

  Therefore, the present invention has been made in view of such a situation, and an object thereof is to provide a highly flexible compiler or the like that allows a user to precisely control optimization by the compiler.

  In order to achieve the above object, a compiler according to the present invention is a compiler device that translates a source program into a machine language program, an instruction acquisition unit that acquires an instruction to optimize a generated machine language program, An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction, and the instruction acquisition unit sets a minimum value of the number of repetitions of a specific loop process in the source program. An instruction for guaranteeing is detected, and the optimization means suppresses generation of an escape code required when the number of iterations is zero when the guaranteed minimum value is 1 or more. To do.

  The compiler according to the present invention is a compiler device that translates a source program into a machine language program, an instruction acquisition unit that acquires an instruction to optimize a generated machine language program, and a machine according to the acquired instruction. Optimization means for performing optimization by generating a word instruction sequence, wherein the instruction acquisition means is an instruction for guaranteeing a minimum number of repetitions of a specific loop process in the source program. And the optimization means performs optimization by loop unrolling when the guaranteed minimum value is equal to or greater than the number of expansions by loop unrolling.

  The compiler according to the present invention is a compiler device that translates a source program into a machine language program, an instruction acquisition unit that acquires an instruction to optimize a generated machine language program, and a machine according to the acquired instruction. Optimization means for performing optimization by generating a word instruction sequence, wherein the instruction acquisition means is a set of odd values or even values in which the number of repetitions of a specific loop process is set in the source program The optimization means detects an indication of guaranteeing that, and the optimization means optimizes by loop unrolling depending on whether the guaranteed set of values is a set of only even values or a set of only odd values It is characterized by performing.

  The compiler according to the present invention is a compiler device that translates a source program into a machine language program, an instruction acquisition unit that acquires an instruction to optimize a generated machine language program, and a machine according to the acquired instruction. And an optimization unit that performs optimization by generating a word instruction sequence, and the instruction acquisition unit includes, in the source program, data indicated by a pointer variable indicated by a specific variable name in a certain alignment. An instruction for guaranteeing that the value is a value is detected, and the optimization unit is configured to guarantee the alignment value for the data indicated by the pointer variable that is the target of the instruction detected by the instruction acquisition unit. The above optimization is performed on the assumption that the data is arranged in the memory area.

  Note that the present invention can be realized not only as a compiler apparatus as described above, but also as a program having steps as means provided in such a compiler apparatus, or as a source program including instructions to the compiler. It can also be realized as a system including a target processor and a compiler device that translates a source program into a machine language program for the target processor. Needless to say, such a program can be widely distributed via a recording medium such as a CD-ROM or a transmission medium such as the Internet.

  Specifically, the following configuration may be provided as one form of the compiler and system according to the present invention.

  The compiler according to the present invention receives an instruction regarding the allocation of variables to the global area, and maps various variables to the global area based on the instruction.

  As one of them, the user can specify the maximum data size of a variable to be allocated to the global area by a compile time option. As a result, the user can control the data size of the variable to be arranged in the global area, and can optimize the global area effectively.

  Further, the user can specify whether or not to allocate to the global area for each variable by a pragma command placed in the source program. As a result, the variable that should be preferentially allocated to the global area and the variable that should not be allocated are individually distinguished, and the user can manage the optimal global area allocation.

  The compiler according to the present invention receives an instruction for software pipelining, and performs optimization by software pipelining according to the instruction.

  As one of them, the user can specify that software pipelining is not performed by a compile-time option. As a result, an increase in code size due to software pipelining is suppressed. Also, since the assembler code subjected to software pipelining is complicated, debugging is facilitated by suppressing software pipelining for the purpose of program function verification.

  Further, the user designates whether or not to perform software pipelining for each loop processing by a pragma instruction in the source program, or performs software pipelining without or without removing the prolog portion and the epilog portion. Can be specified. This makes it possible to select whether or not to perform software pipelining for each loop processing, or to select software pipelining that emphasizes code size (removes prologue epilogue) or speed (removes prologue epilogue). It becomes.

  The compiler according to the present invention receives an instruction for loop unrolling and performs optimization by loop unrolling according to the instruction.

  As one of them, the user can instruct the loop unrolling not to be performed by an option at the time of compilation. This avoids an increase in code size due to loop unrolling.

  Further, the user can instruct whether or not to perform loop unrolling for each loop process by a pragma command in the source program. As a result, the user can select the optimization for placing importance on the execution speed or the code size in consideration of the number of repetitions for each loop process.

  The compiler according to the present invention receives an instruction regarding the number of loop processing iterations, and performs optimization in accordance with the instruction.

  As one of them, the user can guarantee the minimum number of repetitions for each loop process by a pragma command in the source program. As a result, it is not necessary to generate a code (escape code) required when the number of repetitions is 0, and optimization by software pipelining or loop unrolling is possible.

  In addition, the user can guarantee that the number of repetitions is an even number / odd number for each loop process by a pragma command in the source program. As a result, even if the number of repetitions is unknown, optimization by loop unrolling is possible for each loop process, and the execution speed can be improved.

  In addition, the compiler according to the present invention receives an instruction regarding if conversion and performs optimization by if conversion according to the instruction.

  As one of them, the user can give an instruction not to perform the if conversion by a compile-time option. As a result, when the number of instructions on the then side and else side of the if structure is imbalanced, the occurrence of a problem that execution on the side with a small number of instructions is restricted to the side with a large number of instructions by if conversion is prevented. it can.

  Further, the user can instruct whether or not to perform the if conversion for each loop process by a pragma command in the source program. As a result, the selection (if for which the execution speed is expected to be further improved in consideration of the characteristics of each loop processing (the balance of the number of instructions on each of the then side and the else side, the balance of the expected occurrence frequency, etc.)) Conversion / not conversion).

  Further, the compiler according to the present invention receives an instruction regarding alignment in arrangement of array data in a memory area, and performs optimization in accordance with the instruction.

  As one of them, the user can specify alignment by the number of bytes for array data of a specific type by a compile-time option. As a result, a pair instruction for simultaneously transferring two data between the memory and the register is generated, and the execution speed is improved.

  Further, the user can specify the alignment of the data pointed to by the pointer variable by a pragma command in the source program. As a result, a pair instruction can be generated for each data, and the execution speed is improved.

  As described above, the compiler and the system according to the present invention allow the user to specify ON / OFF and the degree of each optimization type by the compiler, rather than the rough instruction as in the past. Detailed control such as turning on / off optimization in units of variable variables and loop processing, etc. is possible, especially effective for media processing application development that requires precise optimization tuning. The practical value is extremely high.

It is a schematic block diagram of the processor used as the object of the compiler which concerns on this invention. A schematic diagram of an arithmetic logic / comparison arithmetic unit of the processor is shown. It is a block diagram which shows the structure of the barrel cutter of the processor. It is a block diagram which shows the structure of the converter of the processor. It is a block diagram which shows the structure of the divider of the processor. It is a block diagram which shows the structure of the multiplication / product-sum calculator of the processor. It is a block diagram which shows the structure of the instruction control part of the processor. It is a figure which shows the structure of the general purpose register | resistor (R0-R31) of the processor. It is a figure which shows the structure of the link register (LR) of the processor. It is a figure which shows the structure of the branch register (TAR) of the processor. It is a figure which shows the structure of the program status register (PSR) of the processor. It is a figure which shows the structure of the condition flag register (CFR) of the processor. It is a figure which shows the structure of the accumulator (M0, M1) of the processor. It is a figure which shows the structure of the program counter (PC) of the processor. It is a figure which shows the structure of the register | resistor for PC saving (IPC) of the processor. It is a figure which shows the structure of the PSR save register (IPSR) of the processor. FIG. 10 is a timing chart showing a pipeline operation of the processor. It is a timing chart showing each pipeline operation at the time of instruction execution by the processor. It is a figure which shows the parallel operation | movement of the processor. It is a figure which shows the format of the command which the processor performs. It is a figure explaining the instruction which belongs to the category "ALUadd (addition) system". It is a figure explaining the instruction which belongs to the category "ALUsub (subtraction) system". It is a figure explaining the instruction which belongs to a category "ALUlogic (logic operation) system etc.". It is a figure explaining the instruction which belongs to the category "CMP (comparison operation) system". It is a figure explaining the instruction which belongs to the category "mul (multiplication) system". It is a figure explaining the instruction which belongs to the category "mac (product-sum operation) system". It is a figure explaining the instruction which belongs to the category "msu (product difference operation) system". It is a figure explaining the instruction which belongs to the category "MEMld (memory read) system". It is a figure explaining the instruction which belongs to the category "MEMstore (memory writing) system". It is a figure explaining the instruction which belongs to the category "BRA (branch) system". It is a figure explaining the instruction which belongs to the category "BSasl (arithmetic barrel shift) system etc.". It is a figure explaining the instruction which belongs to the category "BSlsr (logical barrel shift) system etc.". It is a figure explaining the instruction which belongs to the category "CNVvaln (arithmetic conversion) system". It is a figure explaining the instruction which belongs to the category "CNV (general conversion) system". It is a figure explaining the instruction which belongs to the category "SATvlpk (saturation processing) system". It is a figure explaining the instruction which belongs to a category "ETC (others) system". It is a functional block diagram which shows the structure of the compiler which concerns on this invention. (A) is an example of arrangement of data in the global area, and (b) is a diagram showing an example of arrangement of data in an area other than the global area. It is a flowchart which shows operation | movement of a global area | region allocation part. It is a figure which shows the specific example of the optimization by a global area | region allocation part. It is a figure which shows the specific example of the optimization by a global area | region allocation part. It is a figure which shows the specific example of the optimization by a global area | region allocation part. It is a figure explaining software pipelining optimization. It is a flowchart which shows operation | movement of a software pipelining part. It is a figure which shows the specific example of the optimization by a software pipelining part. It is a flowchart which shows operation | movement of a loop unrolling part. It is a figure which shows the specific example of the optimization by a loop unrolling part. It is a figure which shows the specific example of the optimization by a loop unrolling part. It is a figure which shows the specific example of the optimization by a loop unrolling part. It is a figure which shows the example which cannot apply loop unrolling optimization. It is a figure which shows the specific example of the optimization by a loop unrolling part. It is a flowchart which shows operation | movement of an if conversion part. It is a figure which shows the specific example of the optimization by an if conversion part. It is a flowchart which shows operation | movement of a pair instruction generation part. It is a figure which shows the specific example of the optimization by a pair instruction generation part. It is a figure which shows the specific example of the optimization by a pair instruction generation part. It is a figure which shows the specific example of the optimization by a pair instruction generation part.

Hereinafter, embodiments of a compiler according to the present invention will be described in detail with reference to the drawings.
The compiler in the present embodiment is a cross compiler that translates a source program written in a high-level language such as C language into a machine language program that can be executed by a specific processor, and relates to the code size and execution time of the machine language program to be generated. It has a feature that an instruction for optimization can be specified in detail.

  First, an example of a processor that is a target of a compiler in this embodiment will be described with reference to FIGS.

  The processor that is the target of the compiler in the present embodiment is, for example, a general-purpose processor that has higher parallelism of instructions that can be executed than a normal microcomputer and has been developed targeting the AV media signal processing technology field.

  FIG. 1 is an example of a schematic block diagram of such a processor. The processor 1 includes an instruction control unit 10, a decoding unit 20, a register file 30, an operation unit 40, an I / F unit 50, an instruction memory unit 60, a data memory unit 70, an expansion register unit 80, and an I / O interface unit 90. Composed. The arithmetic unit 40 includes arithmetic logic / comparison arithmetic units 41 to 43 for executing arithmetic operations of SIMD type instructions, a multiplication / product-sum arithmetic unit 44, a barrel shifter 45, a divider 46 and a converter 47. The multiplication / product-sum calculator 44 accumulates up to 65 bits so as not to degrade the bit precision. Further, the multiplication / product-sum operation unit 44 can execute SIMD type instructions similarly to the arithmetic logic / comparison operation units 41 to 43. Further, the processor 1 can execute a maximum of three arithmetic logic / comparison operation instructions in parallel.

  FIG. 2 shows a schematic diagram of the arithmetic logic / comparison arithmetic units 41-43. Each of the arithmetic logic / comparison arithmetic units 41 to 43 includes an ALU unit 41a, a saturation processing unit 41b, and a flag unit 41c. The ALU unit 41a includes an arithmetic operation unit, a logical operation unit, a comparator, and a TST unit. The corresponding arithmetic data has a bit width of 8 bits (4 arithmetic units are used in parallel), 16 bits (2 arithmetic units are used in parallel), and 32 bits (32-bit data processing in all arithmetic units). Further, for the arithmetic operation result, overflow detection and condition flag generation are performed by the flag unit 41c and the like. The arithmetic unit, the comparator, and the TST unit are subjected to arithmetic right shift, saturation by the saturation processing unit 41b, maximum / minimum value detection, and absolute value generation processing.

  FIG. 3 is a block diagram showing the configuration of the barrel shifter 45. The barrel shifter 45 includes selectors 45a and 45b, an upper barrel shifter 45c, a lower barrel shifter 45d, and a saturation processing unit 45e, and executes an arithmetic shift (shift of 2's complement system) or logical shift (unsigned shift) of data. Normally, 32-bit or 64-bit data is input / output. For the data to be shifted stored in the registers 30a and 30b, the shift amount is designated by another register or an immediate value. The data is arithmetically or logically shifted from the left 63 bits to the right 63 bits and output with an input bit length.

  In addition, the barrel shifter 45 can shift 8, 16, 32, and 64-bit data with respect to the SIMD type instruction. For example, a shift of 8-bit data can be processed in 4 parallel.

  Arithmetic shift is a shift of 2's complement system, and alignment of decimal point at the time of addition or subtraction, multiplication by power of 2 (2, 2 squared, 2 (-1) power, 2 (-2) Etc.) etc.

  FIG. 4 is a block diagram showing the configuration of the converter 47. The converter 47 includes a saturation block (SAT) 47a, a BSEQ block 47b, an MSKGEN block 47c, a VSUMB block 47, a BCNT block 47e, and an IL block 47f.

  The saturation block (SAT) 47a performs saturation processing on the input data. By having two blocks that saturate 32-bit data, two parallel SIMD instructions are supported.

The BSEQ block 47b counts consecutive 0s or 1s from the MSB.
The MSKGEN block 47c outputs the designated bit interval as 1, and outputs the other as 0.

  The VSUMB block 47d divides input data into designated bit widths and outputs the sum.

The BCNT block 47e counts the number of bits that are 1 in the input data.
The IL block 47f divides the input data into a designated bit width and outputs a value obtained by replacing each data block.

  FIG. 5 is a block diagram showing a configuration of the divider 46. The divider 46 sets the dividend to 64 bits and the divisor to 32 bits, and outputs the quotient and the remainder each 32 bits. 34 cycles are required to find the quotient and the remainder. Both signed and unsigned data can be handled. However, the setting of the presence / absence of a sign is common to the dividend and the divisor. In addition, it has a function of outputting an overflow flag and a division by zero flag.

  FIG. 6 is a block diagram showing a configuration of the multiplication / product-sum calculator 44. The multiplier / product-sum calculator 44 includes two 32-bit multipliers (MUL) 44a and 44b, three 64-bit adders (Adder) 44c to 44e, a selector 44f, and a saturation processing unit (Saturation) 44g. Multiply and multiply and accumulate.

32 × 32 bit signed multiplication, product sum, product difference operation 32 × 32 bit unsigned multiplication 16 × 16 bit 2-parallel signed multiplication, product sum, product difference operation 32 × 16 bit 2 parallel signed multiplication, product sum, product difference operation

  These operations are performed on data in integer and fixed-point format (h1, h2, w1, w2). Also, rounding and saturation are performed for these operations.

  FIG. 7 is a block diagram illustrating a configuration of the instruction control unit 10. The instruction control unit 10 includes an instruction cache 10a, an address management unit 10b, instruction buffers 10c to 10e, a jump buffer 10f, and a rotation unit (rotation) 10g, and supplies instructions at normal time and branch time. By having three 128-bit instruction buffers (instruction buffers 10c to 10e), the maximum number of parallel executions is supported. Regarding branch processing, a branch destination address is stored in advance in a TAR register, which will be described later, via the jump buffer 10f or the like before branch execution (settar instruction). Branch is performed using the branch destination address stored in the TAR register.

  The processor 1 that is the target of the compiler in the present embodiment is, for example, a processor having a VLIW architecture. Here, the VLIW architecture is an architecture that stores a plurality of instructions (load, store, operation, branch, etc.) in one instruction word and executes them all at the same time. The programmer can process the issue groups in parallel by describing instructions that can be executed in parallel as one issue group. In this specification, the issue group delimiters are indicated by ";;". A notation example is shown below.

(Example 1)
mov r1, 0x23 ;;
This instruction description means that only the instruction mov is executed.

(Example 2)
mov r1, 0x38
add r0, r1, r2
sub r3, r1, r2 ;;
These instruction descriptions mean that instructions mov, add, and sub are executed in parallel.

  The instruction control unit 10 identifies the issue group and sends it to the decoding unit 20. The decoding unit 20 analyzes the instruction of the issuing group and controls necessary resources.

Next, a register included in such a processor 1 will be described.
The register set of the processor 1 is as shown in Table 1 below.

  The flag set of the processor 1 (flags managed by a condition flag register or the like described later) is as shown in Table 2 below.

  FIG. 8 is a diagram illustrating the structure of the general-purpose registers (R0 to R31) 30a. The general-purpose registers (R0 to R31) 30a constitute a part of the context of the task to be executed and are a 32-bit register group for storing data or addresses. The general-purpose registers R30 and R31 are used by hardware as a global pointer and a stack pointer, respectively.

  FIG. 9 is a diagram illustrating the structure of the link register (LR) 30c. In connection with the link register (LR) 30c, the processor 1 also includes a save register (SVR) not shown. The link register (LR) 30c is a 32-bit register that stores a return address at the time of a function call. The save register (SVR) is a 16-bit register that saves the condition flag (CFR.CF) of the condition flag register at the time of function call. The link register (LR) 30c is also used for increasing the loop speed, similarly to a branch register (TAR) described later. The lower 1 bit is always read as 0, but 0 must be written when writing.

For example, when a call (brl, jmpl) instruction is executed, the processor 1 returns the address to the link register (LR) 30c and saves the condition flag (CFR.CF) to the save register (SVR). . When the jmp instruction is executed, the return address (branch destination address) is extracted from the link register (LR) 30c, and the program counter (PC) is restored. Further, when the ret (jmpr) instruction is executed, the branch destination address (return address) is extracted from the link register (LR) 30c and stored (returned) in the program counter (PC). Further, the condition flag is extracted from the save register (SVR) and stored (returned) in the condition flag area CFR.CF of the condition flag register (CFR) 32.

  FIG. 10 is a diagram showing the structure of the branch register (TAR) 30d. The branch register (TAR) 30d is a 32-bit register that stores a branch target address. Mainly used to speed up loops. The lower 1 bit is always read as 0, but 0 must be written when writing.

  For example, when a jmp, jloop instruction is executed, the processor 1 extracts the branch destination address from the branch register (TAR) 30d and stores it in the program counter (PC). When the instruction at the address stored in the branch register (TAR) 30d is stored in the branch instruction buffer, the branch penalty is zero. By storing the top address of the loop in the branch register (TAR) 30d, the speed of the loop can be increased.

  FIG. 11 is a diagram showing the structure of the program status register (PSR) 31. The program status register (PSR) 31 is a 32-bit register that constitutes a part of the context of the task to be executed and stores the processor status information shown below.

  Bit SWE: indicates an LP (Logical Processor) switching enable of VMP (Virtual Multi-Processor). “0” indicates that LP switching is not permitted, and “1” indicates that LP switching is permitted.

  Bit FXP: indicates a fixed point mode. “0” indicates mode 0, and “1” indicates mode 1.

  Bit IH: This is an interrupt processing flag and indicates that maskable interrupt processing is in progress. “1” indicates that interrupt processing is in progress, and “0” indicates that interrupt processing is not in progress. Set automatically when an interrupt occurs. It is used to determine whether the place where the rti instruction has returned from the interrupt is processing another interrupt or program.

  Bit EH: a flag indicating that an error or NMI is being processed. “0” indicates that an error / NMI interrupt is not being processed, and “1” indicates that an error / NMI interrupt is being processed. When EH = 1, if an asynchronous error or NMI occurs, it is masked. When VMP is enabled, VMP plate switching is masked.

  Bit PL [1: 0]: indicates a privilege level. “00” indicates privilege level 0, that is, processor abstraction level, “01” indicates privilege level 1 (cannot be set), “10” indicates privilege level 2, that is, system program level, and “11” indicates Indicates privilege level 3, that is, the user program level.

  Bit LPIE3: indicates LP specific interrupt 3 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit LPIE2: indicates LP specific interrupt 2 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit LPIE1: Indicates LP specific interrupt 1 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit LPIE0: indicates LP specific interrupt 0 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit AEE: indicates misalignment exception enable. “1” indicates that misalignment exception is permitted, and “0” indicates that misalignment exception is not permitted.

  Bit IE indicates level interrupt enable. “1” indicates that a level interrupt is permitted, and “0” indicates that a level interrupt is not permitted.

  Bit IM [7: 0]: indicates an interrupt mask. Levels 0-7 are defined and can be masked at individual levels. Level 0 is the highest level. Only the interrupt request having the highest level among the interrupt requests not masked by the IM is accepted by the processor 1. When an interrupt request is accepted, the level below the accepted level is automatically masked by hardware. IM [0] is a level 0 mask, IM [1] is a level 1 mask, IM [2] is a level 2 mask, IM [3] is a level 3 mask, and IM [ 4] is a level 4 mask, IM [5] is a level 5 mask, IM [6] is a level 6 mask, and IM [7] is a level 7 mask.

  reserved: Indicates a reserved bit. 0 is always read. When writing, it is necessary to write 0.

  FIG. 12 is a diagram showing the structure of the condition flag register (CFR) 32. The condition flag register (CFR) 32 is a 32-bit register that constitutes a part of the context of the task to be executed, and includes a condition flag (condition flag), an operation flag (operation flag), and a vector condition flag (vector). Condition flag), a bit position designation field for operation instructions, and a SIMD data alignment information field.

  Bit ALN [1: 0]: indicates an alignment mode. Sets the alignment mode of the valnvc instruction.

  Bit BPO [4: 0]: indicates a bit position. Used in instructions that require bit position specification.

  Bits VC0 to VC3: Vector condition flags. The LSB side byte or halfword sequentially corresponds to VC0, and the MSB side corresponds to VC3.

  Bit OVS: an overflow flag (summary). Set when saturation occurs or overflow is detected. If not detected, the value before instruction execution is held. Clearing must be done by software.

  Bit CAS: carry flag (summary). Set when a carry occurs with the addc instruction or a borrow occurs with the subc instruction. If no carry occurs with the addc instruction or a borrow does not occur with the subc instruction, the value before the instruction execution is retained. Clearing must be done by software.

  Bits C0 to C7: Condition flags. A condition (TRUE / FALSE) in a conditional execution instruction is shown. The correspondence between the condition of the conditional instruction and the bits C0 to C7 is determined by the predicate bit included in the instruction. Note that the value of the flag C7 is always 1. Reflecting the FALSE condition (writing 0) to the flag C7 is ignored.

  reserved: Indicates a reserved bit. 0 is always read. When writing, it is necessary to write 0.

  FIG. 13 is a diagram showing the structure of the accumulator (M0, M1) 30b. This accumulator (M0, M1) 30b constitutes a part of the context of the task to be executed, and is a 32-bit register MH0-MH1 (multiplication / multiplication / sum of products register (high order) shown in FIG. 13 (a). 32 bits)) and the 32-bit register ML0-ML1 multiplication / division / product-sum register (lower 32 bits) shown in FIG. 13 (b).

Registers MH0-MH are used to store the upper 32 bits of the result in multiply instructions. In the product-sum instruction, it is used as the upper 32 bits of the accumulator. Further, when handling a bit stream, it can be used in combination with a general-purpose register. Register ML0-ML1
Is used in multiply instructions to store the lower 32 bits of the result. In the product-sum instruction, it is used as the lower 32 bits of the accumulator.

  FIG. 14 is a diagram showing the structure of the program counter (PC) 33. This program counter (PC) 33 is a 32-bit counter that constitutes a part of the context of the task to be executed and holds the address of the instruction being executed. 0 is always stored in the lower 1 bit.

  FIG. 15 is a diagram showing the structure of the PC save register (IPC) 34. The PC save register (IPC) 34 is a 32-bit register that constitutes a part of the context of the task to be executed. The lower 1 bit is always read as 0, but 0 must be written when writing. There is.

  FIG. 16 is a diagram showing the structure of the PSR save register (IPSR) 35. The PSR save register (IPSR) 35 is a 32-bit register that constitutes a part of the context of the task to be executed and saves the program status register (PSR) 31. 0 is always read out from the portion corresponding to the reserved bit of (PSR) 31, but it is necessary to write 0 when writing.

  Next, the memory space of the processor 1 that is the target of the compiler in this embodiment will be described. For example, in the processor 1, a 4 GB linear memory space is divided into 32, and an instruction SRAM (Static RAM) and a data SRAM are allocated to a 128 MB unit space. With this 128 MB space as one block, a block to be accessed in the SAR (SRAM Area Register) is set. When the accessed address is a space set by the SAR, the instruction SRAM / data SRAM is directly accessed. When the accessed address is not the space set by the SAR, an access request is sent to the bus controller (BCU). Take out. An on-chip memory (OCM), an external memory, an external device, an I / O port, and the like are connected to the BCU, and reading and writing can be performed on these devices.

  FIG. 17 is a timing chart showing the pipeline operation of the processor 1 that is the target of the compiler in this embodiment. As shown in the figure, the processor 1 is basically composed of, for example, a 5-stage pipeline of instruction fetch, instruction allocation (dispatch), decode, execution, and write.

  FIG. 18 is a timing chart showing each pipeline operation at the time of instruction execution by the processor 1. In the instruction fetch stage, the instruction memory at the address specified by the program counter (PC) 33 is accessed, and the instruction is transferred to the instruction buffers 10c to 10e and the like. In the instruction allocation stage, branch destination address information is output to a branch system instruction, an input register control signal is output, a variable length instruction is allocated, and the instruction is transferred to an instruction register (IR). In the decode stage, IR is input to the decode unit 20 and an arithmetic unit control signal and a memory access signal are output. In the execution stage, the operation is executed, and the operation result is output to the data memory or the general-purpose register (R0 to R31) 30a. In the write stage, data transfer and operation results are stored in general purpose registers.

  The processor 1 that is the target of the compiler in the present embodiment can perform the above-described processing in up to three parallels by using, for example, the VLIW architecture. Therefore, the processor 1 executes the operations shown in FIG. 18 in parallel at the timing shown in FIG.

Next, an example of an instruction set of the processor 1 configured as described above will be described.
Tables 3 to 5 below are tables in which instructions executed by the processor 1 that is a target of the compiler according to the present embodiment are classified by category.

  Note that “operator” in the table indicates an arithmetic unit used by the instruction. The meaning of the abbreviation of the arithmetic unit is as follows. That is, “A” is an ALU instruction, “B” is a branch instruction, “C” is a conversion instruction, “DIV” is a division instruction, “DBGM” is a debug instruction, “M” is a memory access instruction, “S1”, “ “S2” means a shift instruction, and “X1” and “X2” mean a multiplication instruction.

  FIG. 20 is a diagram showing an example of the format of an instruction executed by such a processor 1. The formats include a 16-bit instruction format shown in FIG. 20A and a 32-bit instruction format shown in FIG.

  In addition, the meaning of the symbol in the figure is as follows. That is, “E” is an end bit (parallel execution boundary), “F” is a format bit (00, 01, 10:16 bit instruction format, 11:32 bit instruction format), and “P” is a predicate (execution condition: "OP" means an operation code field, "R" means a register field, "I" means an immediate field, and "D" a displacement field. Note that the “E” field is unique to VLIW, and an instruction with E = 0 is executed in parallel with the next instruction. That is, a VLIW having a variable parallelism is realized by the “E” field.

  FIG. 21 to FIG. 36 are diagrams illustrating schematic functions of instructions executed by the processor 1. That is, FIG. 21 is a diagram for explaining instructions belonging to the category “ALUadd (addition) system”, FIG. 22 is a diagram for explaining instructions belonging to the category “ALUsub (subtraction) system”, and FIG. FIG. 24 is a diagram illustrating instructions belonging to the category “ALUlogic (logical operation) system, etc.”, FIG. 24 is a diagram illustrating instructions belonging to the category “CMP (comparison operation) system”, and FIG. FIG. 26 is a diagram illustrating instructions belonging to the category “mac (product-sum operation) system”, and FIG. 27 is a category “msu (product-difference operation)”. FIG. 28 is a diagram illustrating instructions belonging to the category “MEMld (memory read) system”, and FIG. 29 is a category “MEMstore (memory write) system”. Diagram explaining the instruction to which it belongs FIG. 30 is a diagram for explaining instructions belonging to the category “BRA (branch) system”, and FIG. 31 is a diagram for explaining instructions belonging to the category “BSasl (arithmetic barrel shift) system, etc.” 32 is a diagram for explaining instructions belonging to the category “BSlsr (logical barrel shift) system, etc.”, FIG. 33 is a diagram for explaining instructions belonging to the category “CNVvaln (arithmetic conversion) system”, and FIG. FIG. 35 is a diagram illustrating instructions belonging to the category “SATvlpk (saturation processing) system”, and FIG. 36 is a diagram illustrating the category “ETC”. It is a figure explaining the instruction which belongs to (others) type | system | group.

  In these figures, item “SIMD” indicates the type of instruction (distinguishing between SISD (SINGLE) and SIMD), item “size” indicates the size of each operand to be operated, and item “SIMD” "Instruction" indicates the opcode of the instruction, item "operand" indicates the operand of the instruction, item "CFR" indicates a change in the condition flag register, and item "PSR" indicates a change in the processor status register The item “representative operation” indicates an outline of the operation, the item “operation unit” indicates the operation unit to be used, and the item “3116” indicates the size of the instruction.

  Hereinafter, the operation of the processor 1 with respect to main instructions used in specific examples to be described later will be described.

ld Rb, (Ra, D10)
The word data is loaded into the register Rb from the address obtained by adding the displacement value (D10) to the register Ra.

ldh Rb, (Ra +) I9
Halfword data is sign-extended and loaded from the address indicated by the register Ra. Further, the immediate value (I9) is added to the register Ra and stored in the register Ra.

ldp Rb: Rb + 1, (Ra +)
Two word data are sign-extended and loaded into the registers Rb and Rb + 1 from the address indicated by the register Ra. Further, 8 is added to the register Ra and stored in the register Ra.

ldhp Rb: Rb + 1, (Ra +)
Two halfword data are sign-extended and loaded from the address indicated by the register Ra. Further, 4 is added to the register Ra and stored in the register Ra.

setlo Ra, I16
The immediate value (I16) is sign-extended and stored in the register Ra.

sethi Ra, I16
Store immediate value (I16) in upper 16 bits of register Ra. It does not affect the lower 16 bits of register Ra.

ld Rb, (Ra)
Word data is loaded into the register Rb from the address indicated by the register Ra.

add Rc, Ra, Rb
Registers Ra and Rb are added and stored in register Rb.

addu Rb, GP, I13
The immediate value (I13) is added to the register GP and stored in the register Rb.

st (GP, D13), Rb
The halfword data stored in the register Rb is stored at the address obtained by adding the displacement value (D13) to the register GP.

sth (Ra +) I9, Rb
The halfword data stored in the register Rb is stored at the address indicated by the register Ra. Further, the immediate value (I9) is added to the register Ra and stored in the register Ra.

stp (Ra +), Rb: Rb + 1
The two word data stored in the registers Rb and Rb + 1 are stored at the address indicated by the register Ra. Further, 8 is added to the register Ra and stored in the register Ra.

Ret
Used for return from subroutine call. Branches to the address stored in LR. Transfer SVR.CF to CFR.CF.

mov Ra, I16
The value (I16) is sign-extended and stored in the register Ra.

settar C6, D9
The following processing is performed. (1) The address obtained by adding the PC and the displacement value (D9) is stored in the branch register TAR. (2) Fetch the instruction at that address and store it in the branch instruction buffer. (3) Set C6 to 1.

settar C6, Cm, D9
The following processing is performed. (1) The address obtained by adding the PC and the displacement value (D9) is stored in the branch register TAR. (2) Fetch the instruction at that address and store it in the branch instruction buffer. (3) Set C6 to 1 and Cm to 0.

settar C6, C2: C4, D9
The following processing is performed. (1) The address obtained by adding the PC and the displacement value (D9) is stored in the branch register TAR. (2) Fetch the instruction at that address and store it in the branch instruction buffer. (3) Set C4 and C6 to 1 and set C2 and C3 to 0.

jloop C6, TAR, Ra2, -1
Use in a loop. The following processing is performed. (1) Add −1 to the register Ra2 and store it in the register Ra2. When register Ra2 becomes smaller than 0, C6 is set to 0. (2) Jump to the address indicated by the branch register TAR.

jloop C6, Cm, TAR, Ra2, -1
Use in a loop. The following processing is performed. (1) Set 1 to Cm. (2) Add −1 to the register Ra2 and store it in the register Ra2. When register Ra2 becomes smaller than 0, C6 is set to 0. (3) Jump to the address indicated by the branch register TAR.

jloop C6, C2: C4, TAR, Ra2, -1
Use in a loop. The following processing is performed. (1) Transfer C3 to C2, and transfer C4 to C3 and C6. (2) Add −1 to the register Ra2 and store it in the register Ra2. When register Ra2 becomes smaller than 0, C4 is set to 0. (3) Jump to the address indicated by the branch register TAR.

mul Mm, Rb, Ra, I8
The register Ra is multiplied by the immediate value (I8) with a sign, and the result is stored in the register Mm and the register Rb.

mac Mm, Rc, Ra, Rb, Mn
The registers Ra and Rb are multiplied by an integer and added to the register Mn. The result is stored in register Mm and register Rc.

lmac Mm, Rc, Ra, Rb, Mn
Handle register Rb in halfword vector format. The lower 16 bits of registers Ra and Rb are multiplied by integer and added to register Mn. The result is stored in register Mm and register Rc.

jloop C6, C2: C4, TAR, Ra2, -1
Use in a loop. The following processing is performed. (1) Transfer C3 to C2, and transfer C4 to C3 and C6. (2) Add −1 to the register Ra2 and store it in the register Ra2. When register Ra2 becomes smaller than 0, C4 is set to 0. (3) Jump to the address indicated by the branch register TAR.

asr Rc, Ra, Rb
The register Ra is shifted to the right by the number of bits indicated by Rb. Register Rb is saturated within ± 31, and if negative, it is an arithmetic left shift.

br D9
Add the displacement value (D9) to the current PC and branch to that address.

jmpf TAR
Branches to the address stored in the branch register TAR.

cmpCC Cm, Ra, I5
The following CC comparison conditions can be described in CC.

eq / ne / gt / ge / gtu / geu / le / lt / leu / ltu
When CC is eq / ne / gt / ge / le / lt, I5 is a signed value and is compared with a sign extension. When CC is gtu / geu / leu / ltu, I5 is an unsigned value.

[compiler]
Next, a compiler in the present embodiment targeting the above processor 1 will be described.

  FIG. 37 is a functional block diagram showing the configuration of the compiler 100 in the present embodiment. The compiler 100 is a cross compiler that converts a source program 101 specified in a high-level language such as C language into a machine language program 102 using the processor 1 as a target processor, and is executed on a computer such as a personal computer. The analysis unit 110, the optimization unit 120, and the output unit 130 are roughly implemented.

  The analysis unit 110 performs lexical analysis on the source program 101 to be compiled and instructions from the user to the compiler 100, and the instructions (options and pragmas) to the compiler 100 are sent to the optimization unit 120 and the output unit 130. The program to be transmitted and compiled is converted to internal format data.

The “option” is an instruction to the compiler 100 that can be arbitrarily specified by the user along with the specification of the source program 101 to be compiled when the compiler 100 is started. Instructions for optimizing the code size and execution time of 102 are included. For example, when compiling the source program 101 “sample.c”, the user uses the command “ammmp-cc” on the computer,
c: \> ammmp-cc -o -max-gp-datasize = 40 sample.c
Can be entered. Additional instructions “-o” and “-max-gp-datasize = 40” in this command are optional. An instruction with such an option is handled as an instruction for the entire source program 101.

The “pragma (or pragma command)” is an instruction to the compiler 100 that can be arbitrarily designated (placed) by the user in the source program 101, and the machine language program 102 to be generated is the same as the option. Instructions for optimizing the code size and execution time are included. In the compiler 100 according to the present embodiment, the character string starts with “#pragma”. For example, the user may include in the source program 101
A statement called #pragma_no_gp_access variable name can be described. This statement is a pragma (pragma directive). Unlike an option, such a pragma is treated as an individual instruction only for a variable, a loop process, or the like arranged immediately after the pragma.

  The optimization unit 120 performs, on the source program 101 (internal format data) output from the analysis unit 110, according to an instruction from the analysis unit 110, (1) optimization that prioritizes improvement in execution speed, and (2) In addition to performing optimization that gives priority to code size reduction, and (3) optimization of both execution speed and code size, overall optimization processing to achieve optimization selected from A processing unit (global area allocation unit 121, software pipelining unit 122, loop unrolling unit 123, if conversion unit 124, and pair instruction generation unit 125) that performs individual optimization processing specified by options and pragmas by the user. Have.

  The global area allocating unit 121 specifies a maximum data size of a variable (array) to be arranged in a global area (a memory area that can be referenced beyond a function as a common data area), designation of a variable to be arranged in the global area, and Performs optimization processing according to options and pragmas related to the designation of variables that are not placed in the global area.

  The software pipelining unit 122 can do without removing the software pipelining, the instruction to perform the software pipelining within the range where the prolog / epilog can be removed, and without removing the prolog / epilog. Performs optimization processing according to the option and pragma regarding the instruction to perform software pipelining in the range.

  The loop unrolling unit 123 includes an instruction to perform loop unrolling, an instruction to not perform loop unrolling, a guarantee of the minimum number of times the loop is repeated, a guarantee that the loop is repeated even times, and an odd number of loops. Performs optimization processing according to the option and pragma regarding the guarantee that it will be repeated.

  The if conversion unit 124 performs optimization processing according to an option and pragma regarding an instruction to perform if conversion and an instruction to not perform if conversion.

  The pair instruction generation unit 125 performs an optimization process according to a pragma related to the specification of the alignment of the start address of the array and the structure, and the alignment guarantee of the data indicated by the pointer variable of the function argument or the local pointer variable.

  The output unit 130 replaces the internal format data with a corresponding machine language instruction for the source program 101 that has been optimized by the optimization unit 120, or resolves addresses such as labels and modules. The machine language program 102 is generated and output as a file or the like.

  Next, a characteristic operation of the compiler 100 according to the present embodiment configured as described above will be described with a specific example.

[Global area allocation unit 121]
First, the operation of the global area allocation unit 121 and its significance will be described. The global area allocating unit 121 roughly performs (1) optimization relating to designation of the maximum data size of global area arrangement and (2) optimization relating to designation of global area arrangement.

  First, (1) optimization relating to designation of the maximum data size of the global area arrangement will be described.

  The processor 1 is provided with a global pointer register (gp; general-purpose register R30), and holds the head address of the global area (hereinafter referred to as gp area). In the range where the displacement from the top of the gp area is 14 bits at the maximum, it can be accessed with one instruction.

  In this gp region, an array of external variables, static variables, etc. can be arranged. However, if the range that can be accessed with one instruction is exceeded, the performance will be degraded.

  FIG. 38A is a diagram illustrating an arrangement example of data and the like in the global area. Here, the data size of the array A is a value that does not exceed the maximum data size, and the data size of the array C is a value that exceeds the maximum data size.

  Access to the array A whose entities are contained in the gp area is possible with one instruction as in the following example.

Example: ld r1, (gp, _A-.MN.gptop) ;;
In this example, “.MN.gptop” is a section name (label) indicating the same address as the global pointer register.

On the other hand, in the case of the array C exceeding the maximum data size of the gp area arrangement, the entity is arranged in addition to the gp area, and only the address of the array C is arranged in the gp area. In this case, neither an entity nor an address is stored in the gp area).

  In this case, access to the array C requires a plurality of instructions as in the following example.

Example: For gp address indirect access
ld r1, (gp, _C $-.MN.gptop) ;;
ld r1, (r1,8) ;;

Example: Absolute address access
setlo r0, LO (_C + 8) ;;
sethi r0, HI (_C + 8) ;;
ld r0, (r0) ;;

  Even in the case of the array Z in which entities are arranged outside the range accessible by one instruction in the gp area, as in the arrangement example in the area other than the global area shown in FIG. Generated.

  ld r0, (gp, _Z-.MN.gptop) ;;

  Since this code exceeds the range accessible by one instruction, it is expanded into a plurality of instructions by the linker. Therefore, it is not one instruction access.

  The one instruction access range of the gp area is a maximum 14-bit range, but the range varies depending on the type size of the object. That is, the 8-byte type has a 14-bit range, the 4-byte type has a 13-bit range, the 2-byte type has a 12-bit range, and the 1-byte type has an 11-bit range.

  The compiler 100 places an array / structure entity having a maximum data size (default 32 bytes) or less in the gp area. On the other hand, for an object that exceeds the maximum data size of the global area arrangement, an entity is arranged outside the gp area, and only the top address of the object is arranged in the gp area.

  Here, if there is room in the gp area, it is possible to generate a better code by arranging objects having a data size of 32 bytes or more.

  Therefore, by using the following option, the user can designate the maximum data size as an arbitrary value.

・ Compile options
-mmax-gp-datasize = NUM

  Here, NUM is a designated byte (default 32 bytes) of the maximum data size of one array and structure that can be arranged in the global area.

  FIG. 39 is a flowchart showing the operation of the global area allocating unit 121. When the above option is detected by the analysis unit 110 (steps S100 and S101), the global area allocation unit 121 determines that all variables (arrays) that are equal to or less than the specified size (NUM bytes) declared in the source program 101 are displayed. ) Is placed in the global area, and for variables exceeding NUM bytes, only the head address is placed in the global area, and the entity is placed in a memory area other than the global area (step S102). This option allows for optimization of speed and size reduction.

Note that with this -mmax-gp-datasize option, you cannot specify the placement of individual variables. In order to specify whether or not to be placed in the gp area for each variable, a #pragma_gp_access command described later may be used. Further, it is preferable that the external variable / static variable is arranged in a gp area accessible by one instruction as much as possible. Furthermore, when using an extern declaration to access an external variable defined in another file, it is preferable to specify the size of the external variable without omitting it. For example, the definition of an external variable is
int a [8];
If the file used is
extern int a [8];
It is preferable to declare

  When using the #pragma _gp_access directive for an extern declaration external variable, it is necessary to match the definition specification (area to be allocated) with the specification on the use side (access method).

Next, a specific example of optimization using such an option will be shown.
FIG. 40 is a diagram illustrating a specific example of optimization when the maximum data size is changed. In other words, since the gp area is still empty as a result of compiling in the default state, examples of generated code obtained in both cases when compiling with the maximum data size changed are as shown in the following command example. It is shown.

  c: \> ammmp-cc -O -mmax-gp-datasize = 40 sample.c

  Here, it is assumed that the object size of the array c is 40 bytes. The left column of this figure is an example of code generated when compiled in the default state, and the right column of this figure shows code generated when compiled with the maximum data size changed to 40 It is an example. The uppermost, middle upper, middle lower, and lowermost rows in the figure are the title of each column, sample program (source program 101), code generated therefrom (machine language program 102), and generated code, respectively. The number of cycles and the code size are shown (hereinafter the same applies to other figures showing specific examples of optimization).

  As can be seen from the generated code in the left column of the figure, since the entity of the array c is arranged outside the gp area, absolute address access is performed with a plurality of instructions. On the other hand, as can be seen from the generated code in the right column of this figure, since the maximum data size (40) is specified so that the entity of the array c is placed in the gp region, the entity of the array c is placed in the gp region, Gp-relative access with one instruction access improves execution speed. That is, by default, an 8-byte code that is executed in 10 cycles is generated, whereas a 5-byte code that is executed in 7 cycles is generated by changing the maximum data size.

  As another specific example, FIG. 41 shows a specific example in the case of an external variable defined outside a file. Here, it is assumed that the maximum data size of the gp region arrangement is 40. The left column of this figure shows an example of code that is generated when no size is specified for an external variable defined outside the file, and the right column of this figure shows an example of code that is generated when a size is specified. ing.

  As shown in the left column of this figure, since the sizes of the externally defined array a and the externally defined array c are both unknown, the compiler 100 cannot determine whether they are arranged in the gp area, and the absolute address in a plurality of instructions. An access code has been generated.

  On the other hand, as shown in the right column of the figure, since the definition size of the array a is 40 bytes or less, the entity is placed in the gp area and the gp relative access code with one instruction using the global pointer register (gp). Has been generated. In addition, since the size of the externally defined array c is also explicitly specified and is less than or equal to the maximum data size of the gp area arrangement, it is assumed that the entity of the array c is arranged in the gp area, and the gp relative access code is Has been generated. In this way, when the size of the external variable defined outside the file is not specified, a 12-byte code that is executed in 10 cycles is generated, whereas the change of the maximum data size and the specification of the size of the external variable are If done, a 5-byte code that is executed in 7 cycles is generated.

  Next, (2) optimization related to designation of global area arrangement by the global area allocating unit 121 will be described.

  In the above-described maximum data size specification (-mmax-gp-datasize option) for global area arrangement, since the arrangement of the gp area is specified only at the maximum data size, an unexpected variable may be arranged in the gp area. .

Therefore, a #pragma directive that specifies the arrangement of the gp area for each variable is prepared.
#Pragma directive
#pragma _no_gp_access variable-name [, variable-name, ...]
#pragma _gp_access variable name [, variable name, ...]

Here, the inside of [] means that it can be omitted. When specifying multiple variables, the variable names can be separated by "," (comma). If the option and the pragma command overlap or contradict each other, the pragma command takes precedence.

  In response to such a pragma command, the compiler 100 operates as follows. That is, in FIG. 39, when the analysis unit 110 detects the pragma command “#pragma _no_gp_access variable name [, variable name,...]” (S100, S101), the global area allocation unit 121 For the specified variable, regardless of the option specification, a code that is not placed in the global area is generated (step S103). On the other hand, the analysis unit 110 uses the pragma command “#pragma _gp_access variable name [, variable name, ...]. "Is detected (S100, S101), the global area allocating unit 121 generates a code to be arranged in the global area regardless of the option designation for the variable designated here (step S104). These #pragma directives enable optimization of speed improvement and size reduction.

  When the #pragma_no_gp_access directive is specified, the global area allocating unit 121 does not place an entity or address in the gp area for the variable. The #pragma_gp_access directive takes precedence over the maximum data size specification. If different designations appear for the same variable, the operation of the compiler 100 is undefined. It is preferable that the external variable / static variable be arranged in the gp area accessible by one instruction as much as possible.

  Next, a specific example of optimization using such a pragma command will be shown. When the #pragma_gp_access directive is used, an external variable / static variable larger than the maximum data size of the gp area arrangement can be arranged in the gp area.

  FIG. 42 is a diagram illustrating an example of code generated when the #pragma_no_gp_access directive is used (left column) and an example of code generated when the #pragma _gp_access directive is used (right column). .

  As shown in the left column of the figure, since the size of the array c is 40 bytes, in the case of default, only the top address is arranged in the gp area, and the entity is not arranged in the gp area. In addition, since the size of the externally defined array a is 32 bytes, the compiler 100 determines that the entity is arranged in the gp area in the default case.

  However, with the #pragma_no_gp_access command, for the array c, the top address and the entity are not arranged in the gp area, but the entity is arranged outside the gp area, and an absolute address access code is generated. Also for the externally defined array a, an absolute address access code is generated on the assumption that entities are located outside the gp area.

  On the other hand, as shown in the right column of the figure, since the size of the array c is 40 bytes, it is not arranged in the gp area by default, but the entity of the array c is arranged in the gp area by the #pragma_gp_access command. The array a defined outside the file has an unknown size, but is arranged in the gp area by the #pragma directive, and a gp relative access code is generated.

  Thus, when the #pragma_no_gp_access command is used, a 12-byte code is generated that is executed in 10 cycles, whereas when the #pragma_gp_access command is used, it is executed in 7 cycles. A 5-byte code is generated.

  When using the #pragma_gp_access directive for an extern declaration external variable, it is preferable to always match the definition specification (area to be allocated) with the specification on the use side (access method).

[Software pipelining unit 122]
Next, the operation of the software pipelining unit 122 and its significance will be described.

  Software pipelining optimization is one of loop acceleration methods. When this optimization is performed, the loop structure is converted into a prolog part, a kernel part, and an epilog part. The software pipelining optimization is performed when it is determined that the execution speed is improved. The kernel unit overlaps each iteration (repetition) with the previous and subsequent iterations. This reduces the average processing time for each iteration.

  FIG. 43A is a conceptual diagram of a prolog part, a kernel part, and an epilog part in the loop processing. Here, an example of an instruction code, an execution image, and a generated code image when instructions X, Y, and Z having no dependency relationship between iterations are repeated five times is shown. The loop process is an iterative process using a for statement, a while statement, a do statement, or the like.

  Here, the prolog part and the epilog part are removed as shown in the processes of FIGS. 43B and 43C if possible. However, if it is not possible, the code size may increase without being removed. Therefore, an option to specify the operation of software pipelining optimization and #pragma directive are prepared.

  FIG. 43B is a conceptual diagram showing processing for removing the prolog portion and epilog portion in the loop processing. That is, for the five iterations of the instructions X, Y, and Z that have no dependency relationship between the iterations shown in FIG. 43 (a), the loop shown in the conceptual diagram of the prolog portion, kernel portion, and epilog portion described above. A reordered generated code image is shown. However, instructions with [] in the figure are read but not executed.

  In this way, it can be seen that the prolog part and epilog part have the same instructions as the kernel part. Therefore, the number of loops increases by the amount of execution (4 times) of the prolog part and epilog part, but as shown in FIG. 43 (c) by controlling the instruction with [] according to the predicate (execution condition). The code can be generated only by the kernel part.

  The execution order of the generated code shown in FIG. 43 (c) is as follows.

  In the first time, the instruction with the predicates [C2] and [C3] is not executed. Therefore, only [C4] X is executed.

  In the second time, the instruction with the predicate [C2] is not executed. Therefore, only [C3] Y and [C4] X are executed.

  In the third to fifth rounds, [C2] Z, [C3] Y, and [C4] X are all executed.

  In the sixth time, the instruction with the predicate [C4] is not executed. Therefore, only [C2] Z and [C3] Y are executed.

  In the seventh time, the instructions with the predicates [C3] and [C4] are not executed. Therefore, only [C2] Z is executed.

  Thus, the prolog part is executed in the first and second loops of the kernel part, and the epilog part is executed in the sixth and seventh times.

  Therefore, in a loop having a prolog part and an epilog part, the code size increases, but since the number of loops decreases, an improvement in execution speed can be expected. Conversely, in the loop from which the prolog part and epilog part are removed, the code size can be reduced, but the number of execution cycles increases because the number of loops increases.

  Therefore, the following compile options and pragma directives are prepared in order to be able to specify such optimization selection.

・ Compile options
-fno-software-pipelining
#Pragma directive
#pragma _no_software_pipelining
#pragma _software_pipelining_no_proepi
#pragma _software_pipelining_with_proepi

  If the option and the pragma command overlap or contradict each other, the pragma command takes precedence.

  FIG. 44 is a flowchart showing the operation of the software pipelining unit 122. When the option “-fno-software-pipelining” is detected by the analysis unit 110 (steps S110 and S111), the software pipelining unit 122 performs software for all the loop processes in the target source program 101. Pipelining optimization is not performed (step S112). This option avoids increasing the code size.

When the analysis unit 110 detects the pragma command “#pragma_no_software_pipelining” (steps S110 and S111), the software pipelining unit 122 is placed immediately after this specification regardless of the option specification. Software pipelining optimization is not performed for the two loop processes (step S113). This reduces the code size.

  If the pragma command “#pragma_software_pipelining_no_proepi” is detected by the analysis unit 110 (steps S110 and S111), the software pipelining unit 122 is placed immediately after this specification regardless of the option specification. For one loop process, software pipelining optimization is performed within a range in which the prolog part and epilog part can be removed (step S114). This improves speed and reduces size.

  If the pragma command “#pragma_software_pipelining_with_proepi” is detected by the analysis unit 110 (steps S110 and S111), the software pipelining unit 122 is placed immediately after this specification regardless of the option specification. For one loop process, software pipelining optimization is performed as much as possible without removing the prolog part and the epilog part (step S115). This improves the speed.

  The software pipelining unit 122 performs software pipelining optimization for the #pragma _software_pipelining_no_proepi command within the range that can remove the prolog and epilog units. Even if the part can be removed, it is not removed. Even in the loop where the prolog / epilog can be removed, as shown in the example shown in FIG. 45, by suppressing the removal of the prolog / epilog, the code size increases, but the execution speed is improved. Because it can be expected. As will be described later, when the minimum number of iterations of the loop processing is equal to or greater than the number of iterations overlapped by software pipelining, the software pipelining unit 122 performs optimization by software pipelining.

  FIG. 45 is a diagram illustrating an example of software pipelining optimization. In this example, in order to perform software pipelining optimization, compilation is performed with the compile option -O (optimization of execution speed and code size reduction).

  As can be seen from the example of the machine language program 102 shown in the middle and lower part of the left column of this figure, when the default software pipelining optimization is performed, the code of the prolog part and the epilog part is also removed, and the loop The number of times is 101 and the number of cycles of the kernel part is 2, which is executed in a total of 207 cycles, improving the loop performance.

  On the other hand, as can be seen from the source program 101 shown in the upper middle of the right column of this figure, the #pragma_software_pipelining_with_proepi directive is additionally specified for the source program 101 in the left column, and the prolog and epilog portions of the loop are removed This is a suppressed example. As a result, as can be seen from the example of the machine language program 102 shown in the lower middle part of the right column, the code size of the prolog part and the epilog part is generated, so the code size is increased compared to the left side. Is reduced to 99 times, and the number of kernel part cycles is 2. Therefore, the execution is performed in a total of 204 cycles, and the execution speed is further improved as compared with the case of the left column. If the prolog part / epilog part can be executed in parallel with the peripheral code, the influence of the speed reduction by the prolog part / epilog part can be concealed.

[Loop unrolling section 123]
Next, the operation of the loop unrolling unit 123 and its significance will be described. The loop unrolling unit 123 roughly performs (1) optimization relating to designation of loop unrolling and (2) optimization relating to guarantees regarding the number of loop iterations.

First, (1) optimization related to designation of loop unrolling will be described.
Loop unrolling optimization is one of loop acceleration methods. Speed up execution in a loop by running multiple iterations simultaneously. By performing loop unrolling optimization, it is possible to improve execution speed by generating ldp / stp instructions and improving parallelism. However, the code size increases and, depending on the case, a spill due to a shortage of registers may occur, and conversely, the performance may be degraded.

  The load pair (store pair) instruction (ldp / stp instruction) is an instruction that realizes two load instructions (store instructions) with one instruction. Further, “spill” is to temporarily save a used register in the stack in order to secure an empty register. In this case, a load / store instruction is generated for saving and restoring the register.

  Options and #pragma directives are provided to specify such loop unrolling optimization behavior.

・ Compile options
-fno-loop-unroll
#Pragma directive
#pragma _loop_unroll
#pragma _no_loop_unroll

  FIG. 46 is a flowchart showing the operation of the loop unrolling unit 123. If the option “-fno-loop-unroll” is detected by the analysis unit 110 (steps S120 and S121), the loop unrolling unit 123 performs loop processing for all loop processes in the target source program 101. Unrolling optimization is not performed (step S122). This option avoids increasing the code size.

  Further, when the pragma command “#pragma_loop_unroll” is detected by the analysis unit 110 (steps S120 and S121), the loop unrolling unit 123 performs loop unrolling with respect to one loop process placed immediately after. Optimization is performed (step S123). This improves the speed.

In addition, when the pragma command “#pragma_no_loop_unroll” is detected by the analysis unit 110 (steps S120 and S121), the loop unrolling unit 123 performs loop unrolling with respect to one loop process placed immediately after. Optimization is not performed (step S124). This avoids an increase in code size.

  If -O / -Ot (optimization with priority on execution speed) is specified in the optimization level specification, the loop unrolling unit 123 defaults to loop if loop unrolling optimization is possible. Perform unrolling optimization. When -Os (optimization with priority given to code size reduction) is designated as the optimization level designation, the loop unrolling unit 123 does not perform loop unrolling optimization. Therefore, the user can control the application of the loop unrolling optimization of each loop with the #pragma_no_loop_unroll instruction and the #pragma_loop_unroll instruction in combination with these optimization level specification compilation options.

  FIG. 47 is a diagram illustrating an example of optimization by the #pragma_loop_unroll command. The left column of this figure is an example when compiling with only the optimization level specification compilation option -O, and the right column of this figure is an example when compiling with the #pragma _loop_unroll directive.

  As can be seen from the example of the machine language program 102 shown in the middle and lower part of the left column of this figure, software pipelining optimization in which the prolog part and the epilog part are removed is applied. Therefore, 3 instructions (2 cycles) in the kernel part are executed 101 times, and it takes a total of 207 cycles.

  On the other hand, as can be seen from the example of the machine language program 102 shown in the middle and lower part of the right column, software pipelining optimization is performed as in the left side, and the prolog part and epilog part are deleted. In addition, in the machine language program 102 in the right column, since the number of loops is halved by the loop unrolling optimization, 6 instructions (2 cycles) of the kernel part are executed 52 times, and executed in total 110 cycles. And the speed has been improved.

Next, a method of using loop unrolling optimization more effectively by generating a pair memory access instruction (ldp / stp) will be described.

  In the loop unrolling optimization, the current iteration and the next iteration are executed at the same time. Therefore, the following data load / store of the continuous region may be generated.

ld r1, (r4) ;;
ld r2, (r4,4) ;;

  If the data to be accessed is always arranged with 8-byte alignment, the following pair memory access instruction (ldp instruction) can be generated.

  ldp r1: r2, (r4 +) ;;

  FIG. 48 is a diagram illustrating an example in which loop unrolling optimization is more effectively used by generating a pair memory access instruction (ldp / stp). Here, software pipelining optimization is applied.

  In the example in the right column of this figure, as can be seen from the example of the machine language program 102 shown in the middle and lower sections, the number of loops is halved by the loop unrolling optimization. Also, by using the #pragma_align_local_pointer directive, the load variables (store pair) instructions are generated by specifying the pointer variables pa and pb as 8-byte aligned addresses.

  As a result of these optimizations, in the example in the left column, 5 instructions and 3 cycles in the kernel part are executed 101 times, and the total is 308 cycles, but in the example in the right column, 7 instructions and 3 cycles in the kernel part are halved. It is executed 51 times, and it is executed in a total of 158 cycles, and the speed is improved.

  Next, (2) optimization related to guaranteeing the number of loop iterations by the loop unrolling unit 123 will be described.

  If the compiler 100 cannot specify the number of loops in the description of the program, each optimization of loop speedup cannot be performed effectively.

  Therefore, the user can optimize the loop speedup such as software pipelining more effectively by providing information on the number of loops with the #pragma directive shown below.

#Pragma directive
#pragma _min_iteration = NUM
#pragma _iteration_even
#pragma _iteration_odd

  In FIG. 46, when the pragma command “# pragma_min_iteration = NUM” is detected by the analysis unit 110 (steps S120 and S121), the loop unrolling unit 123 determines that one loop process immediately after is the lowest. The loop unrolling optimization is performed on the assumption that NUM is repeated (step S125). For example, for example, when the guaranteed minimum number of repetitions is equal to or greater than the number of expansions by loop unrolling, the loop unrolling unit 123 performs loop unrolling of the loop processing. This improves speed and reduces size.

  Further, when the pragma command “#pragma_iteration_even” is detected by the analysis unit 110 (steps S120 and S121), the loop unrolling unit 123 repeats an even number of loop processes immediately after the loop processing. As a premise, loop unrolling optimization is performed (step S126). As a result, the execution speed is improved.

  Further, when the pragma command “#pragma_iteration_odd” is detected by the analysis unit 110 (steps S120 and S121), the loop unrolling unit 123 repeats an odd number of loop processes immediately after it. As a premise, loop unrolling optimization is performed (step S126). As a result, the execution speed is improved.

  Note that when a value of 1 or more is specified by the #pragma_min_iteration command, there is an effect that an escape code generated for the case where the loop does not pass once can be removed. Also, when loop unrolling optimization is expected for a loop whose number of iterations is unknown, if it is decided whether the loop is an even number of times or an odd number of times, by using the _iteration_even / # pragma _iteration_odd directive, Since loop unrolling optimization can be applied, an improvement in execution speed can be expected.

  FIG. 49 is a diagram illustrating an example of optimization by the #pragma_min_iteration command. Here, the effect of using the #pragma_min_iteration directive in a loop where the number of iterations is unknown is shown. However, the value of the argument end is set to 100 for cycle comparison.

  In the left column of this figure, as can be seen from the example of the machine language program 102 shown in the lower middle part, since the number of loops is unknown, the cmple / br instruction (for jumping over the loop body when the loop is never executed) Escape code) is generated. Since a loop instruction cannot be generated, a loop is generated with an addition instruction, a comparison instruction, and a jump instruction. As for the number of cycles, the loop part is repeated 100 times of 4 cycles of 7 instructions, and the total number is 405 cycles.

  On the other hand, in the right column of this figure, as can be seen from the example of the source program 101 shown in the upper middle part, the number of repetitions is unknown, but it is specified by the #pragma_min_iteration command that it is repeated at least four times. Thereby, since it is not necessary to consider the case where the number of loops is 0, the loop unrolling unit 123 does not need to generate an escape code.

  In consideration of the minimum number of loops, the loop unrolling unit 123 can generate a loop instruction. For example, since the guaranteed minimum number of repetitions (4) is equal to or greater than the number of expansions by loop unrolling (3 cycles in this example), the loop unrolling unit 123 performs loop unrolling.

  Furthermore, in this example, further software pipelining optimization is possible. This is because the minimum number of loop iterations (4) guaranteed is equal to or greater than the number of iterations overlapped by software pipelining, so that the software pipelining unit 122 performs optimization by software pipelining.

  As can be seen from the example of the machine language program 102 shown in the middle and lower part of the right column, the number of cycles is 101 times of 5 instructions and 3 cycles in the loop part, and the total number of cycles is 308 cycles. It has been realized.

  50 and 51 are diagrams showing an example of optimization by the # pragma_iteration_even / # pragma_iteration_odd command. FIG. 50 is a diagram illustrating an example of the source program 101 (left column) when the number of loops is unknown and an example of the machine language program 102 generated from the source program 101 (right column). As can be seen from this figure, when the actual number of loops is unknown, loop unrolling optimization cannot be applied. This is because the codes generated by the loop unrolling optimization differ between the case where the number of loops is an even number and the case where the number of loops is an odd number.

  However, as shown in FIG. 51, even in the case of a loop whose number of iterations is unknown, loop unrolling optimization can be applied by designating whether the loop is an even number or an odd number.

  In the left column of this figure, the loop unrolling optimization is performed by the loop unrolling unit 123 because the number of loops is specified by the #pragma _iteration_even directive, and is shown in the middle and lower part of the left column. As can be seen from the example of the machine language program 102, a code for an even number of times is generated.

  Also, in the right column of this figure, since the number of loops is an odd number is specified by the #pragma_iteration_odd directive, loop unrolling optimization by the loop unrolling unit 123 is performed, As can be seen from the example of the machine language program 102 shown in FIG. As can be seen from the example in the right column, the generated code for the even number of times shown in the left column and the initialization unit / loop unit are almost the same, and the code for executing the last one loop in the post-processing unit Has been generated.

  In this way, even if the number of loops is unknown, the loop unrolling unit 123 can perform the loop unrolling optimization by guaranteeing whether it is an even number or an odd number. Speed is improved.

[If conversion unit 124]
Next, the operation of the if conversion unit 124 and its significance will be described.

  Normally, when an if structure of a C language program is compiled, a branch instruction (br instruction) is generated. On the other hand, if conversion refers to rewriting the if structure of a C language program to only conditional execution instructions without using branch instructions. As a result, the execution order is fixed (becomes sequential execution), so that the disturbance of the pipeline can be avoided and the execution speed can be improved. The conditional execution instruction is an instruction that is executed only when the condition (predicate) included in the instruction matches the state (condition flag) of the processor 1.

  The if conversion reduces the execution time in the worst case of the if structure, but the execution time in the best case becomes equal to the worst execution time (after reduction). Therefore, there are cases where the if conversion should or should not be applied depending on the characteristics of the if structure (the occurrence frequency of each of the conditions and whether or not the condition is satisfied and the number of execution cycles of each path).

  For this reason, the user can instruct whether or not it is applicable with a compile option or #pragma directive.

・ Compile options
-fno-if-conversion
#Pragma directive
#pragma _if_conversion
#pragma _no_if_conversion

  If the option and the pragma command overlap or contradict each other, the pragma command takes precedence.

  FIG. 52 is a flowchart showing the operation of the if conversion unit 124. If the option “-fno-if-conversion” is detected by the analysis unit 110 (steps S130 and S131), the if conversion unit 124 determines if for all the if structure statements in the target source program 101. Conversion is not performed (step S132). If this option is not detected, the if conversion unit 124 can perform the if conversion, and the if structure sentence when the worst case time is an if structure sentence shorter than that before the if conversion. Is converted.

  Also, when the pragma command “#pragma_if_conversion” is detected by the analysis unit 110 (steps S130 and S131), the if conversion unit 124 sets one if structure statement immediately after it regardless of the option designation. If possible, if conversion is performed (step S133). This improves the speed.

  Also, when the pragma command “#pragma_no_if_conversion” is detected by the analysis unit 110 (steps S130 and S131), the if conversion unit 124 sets one if structure statement immediately after it regardless of the option designation. In contrast, if conversion is not performed (step S134). This improves the speed.

  FIG. 53 is a diagram illustrating an example of the machine language program 102 when compiled with the #pragma_no_if_conversion command and when compiled with the #pragma_if_conversion command.

  In the left column of this figure, as can be seen from the example of the machine language program 102 in the lower middle part, branch instructions are generated by suppressing if conversion (the number of execution cycles: 5 or 7, code size: 12 bytes) ).

  On the other hand, in the right column of the figure, as can be seen from the example of the machine language program 102 in the lower middle part, the branch instruction is changed to a conditional instruction (an instruction with a predicate) by performing the if conversion by the #pragma instruction. Has been replaced (number of execution cycles: 4, code size: 8 bytes). In this way, by executing the if conversion, an execution speed ratio of 1.25 times and a code size ratio of 67% are achieved.

[Pair instruction generator 125]
Next, the operation of the pair instruction generation unit 125 and its significance will be described. The pair instruction generation unit 125 is roughly divided into (1) optimization related to the setting of alignment of arrays and structures, and (2) optimization related to guarantee of alignment of dummy argument pointers and local pointers.

First, (1) optimization related to setting of alignment of arrays / structures will be described.
The user can specify the alignment of the start address of the array and structure using the following options: By adjusting the alignment, it becomes possible to pair memory access instructions (transfer between two registers and memory with one instruction), and an improvement in execution speed can be expected. On the other hand, when the alignment value is increased, the unused area of data increases, and the data size may increase.

・ Compile options
-falign_char_array = NUM (NUM = 2,4 or 8)
-falign_short_array = NUM (NUM = 4 or 8)
-falign_int_array = NUM (NUM = 8)
-falign_all_array = NUM (NUM = 2,4 or 8)
-falign_struct = NUM (NUM = 2,4 or 8)

  The above options specify, from the top, an array of char type, a short type integer, an int type integer, an array of all three data types, and an alignment of structures. “NUM” indicates the size (bytes) to be aligned.

  FIG. 54 is a flowchart showing the operation of the pair instruction generation unit 125. When any of the above options is detected by the analysis unit 110 (steps S140 and S141), the pair instruction generation unit 125 selects all the arrays of the specified type declared in the target source program 101 or For a structure, an array or structure is arranged in a memory so that the start address is aligned with a specified NUM byte, and for instructions that access the array or structure, pairing (2 (Generation of an instruction for transferring data between one register and a memory in parallel) (step S142). As a result, the execution speed is improved.

  FIG. 55 is a diagram showing assembly code when the sample program is compiled without an option and when it is compiled with the option “-falign-short-array = 4”.

  In the case of no option shown in the left column of this figure, since the alignment is unknown as can be seen from the example of the machine language program 102 shown in the lower middle part, pairing of load instructions (between two registers and memory) Transfer cannot be performed with one instruction) (number of execution cycles: 25, code size: 22).

On the other hand, in the case of the option shown in the right column of the figure, since the array is aligned with 4 bytes, as can be seen from the example of the machine language program 102 shown in the middle and lower rows, pairing by the optimization unit 120 is performed. Is realized (number of execution cycles: 15, code size: 18). As described above, the execution speed ratio of 1.67 times and the code size ratio of 82% are achieved by specifying the alignment.

  Next, (2) optimization related to guaranteeing alignment of the dummy argument pointer / local pointer by the pair instruction generation unit 125 will be described.

  The user can perform pairing of memory access instructions by the optimization unit 120 by guaranteeing the alignment of the data pointed to by the pointer variable of the function argument and the alignment of the data pointed to by the local pointer variable using the following pragma directive Therefore, improvement in execution speed can be expected.

#Pragma directive
#pragma _align_parm_pointer = NUM variable name [, variable name,…]
#pragma _align_local_pointer = NUM variable name [, variable name,…]

  “NUM” represents the size to be aligned (2, 4 or 8 bytes). If the data pointed to by the pointer variable guaranteed by the #pragma directive is not aligned to the specified byte boundary, the normal operation of the program is not guaranteed.

  54, when the analysis unit 110 detects the pragma command “# pragma_align_parm_pointer = NUM variable name [, variable name,...]” (Steps S140 and S141), the pair instruction generation unit 125 displays “variable name”. It is assumed that the data pointed to by the pointer variable of the argument indicated by “is aligned to the NUM byte at the time of argument passing, and the instruction for accessing the array is paired if possible (step S143). As a result, the execution speed is improved.

When the analysis unit 110 detects the pragma command “# pragma_align_local_pointer = NUM variable name [, variable name,...]” (Steps S140 and S141), the pair instruction generation unit 125 sets the “variable name”. It is assumed that the data pointed to by the indicated local pointer variable is always aligned with NUM bytes inside the function, and instructions that access the array are paired if possible (step S144). As a result, the execution speed is improved.

  FIG. 56 is a diagram illustrating an example of optimization by the pragma command “# pragma_align_parm_pointer = NUM variable name [, variable name,...]”.

  As shown in the left column of this figure, when #pragma _align_parm_pointer is not given, the alignment of the data pointed to by the pointer variable src is unknown, so as can be seen from the example of the machine language program 102 shown in the lower middle part, Data is loaded independently (160 execution cycles, code size: 24 bytes).

  On the other hand, as shown in the right column of this figure, when the #pragma directive is given, the data is aligned on a 4-byte boundary. (Number of execution cycles: 107, code size: 18 bytes). Thus, by specifying the alignment, an execution speed ratio of 1.50 times and a code size ratio of 43% are achieved.

  FIG. 57 is a diagram showing an example of optimization by the pragma command “# pragma_align_local_pointer = NUM variable name [, variable name,...]”.

  As shown in the left column of this figure, if #pragma _align_local_pointer is not given, the alignment of the data pointed to by pointer variables from and to is unknown, so as can be seen from the example of the machine language program 102 shown in the middle and lower rows The array elements are loaded independently (number of execution cycles: 72, code size: 30).

  On the other hand, as shown in the right column of this figure, by giving #pragma _align_parm_pointer, the data pointed to by pointer variables from and to is a 4-byte boundary, as can be seen from the example of the machine language program 102 shown in the middle and lower row. It is possible to perform pairing of memory reading using the fact that they are aligned with each other. (Number of execution cycles: 56, code size: 22). Thus, by specifying the alignment, an execution speed ratio of 1.32 times and a code size ratio of 73% are achieved.

  According to the compiler of the present invention, it is possible to specify ON / OFF and its degree for each type of optimization by the compiler, to turn optimization on / off in units such as variables and loop processing in the program, etc. Fine control is possible, and it is particularly useful for developing media processing applications that require precise optimization tuning.

1 Processor 10 Instruction Control Unit 20 Decoding Unit 30 Register File 31 Program Status Register (PSR)
32 Condition flag register (CFR)
33 Program counter (PC)
34 PC save register (IPC)
35 PSR save register (IPSR)
40 arithmetic units 41 to 43 arithmetic logic / comparison arithmetic unit 44 multiply-add arithmetic unit 45 barrel shifter 46 divider 47 converter 50 I / F unit 60 instruction memory unit 70 data memory unit 80 extension register unit 90 I / O interface unit 100 compiler DESCRIPTION OF SYMBOLS 101 Source program 102 Machine language program 110 Analysis part 120 Optimization part 121 Global area allocation part 122 Software pipelining part 123 Loop unrolling part 124 If conversion part 125 Pair instruction generation part 130 Output part

Claims (14)

A system comprising a target processor and a compiler device that translates a source program into a machine language program for the target processor,
The compiler apparatus includes:
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition means detects an instruction in the source program for guaranteeing that the number of repetitions of a specific loop process is a set of values greater than or equal to a specified value,
The optimization unit suppresses generation of an escape code required when the number of iterations is zero when the guaranteed set of values is a set of one or more values. A system comprising a target processor and a compiler device that translates a source program into a machine language program for the target processor,
The compiler apparatus includes:
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition means detects an instruction in the source program for guaranteeing that the number of repetitions of a specific loop process is a set of values greater than or equal to a specified value,
The optimization means performs optimization by loop unrolling when the guaranteed set of values is a set of values greater than or equal to the number of expansions by loop unrolling. A system comprising a target processor and a compiler device that translates a source program into a machine language program for the target processor,
The compiler apparatus includes:
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition means detects an instruction in the source program for guaranteeing that the number of repetitions of a specific loop process is a set of values greater than or equal to a specified value,
The optimization unit performs optimization by loop unrolling according to whether the set of guaranteed values is a set of only even values or a set of only odd values. A system comprising a target processor and a compiler device that translates a source program into a machine language program for the target processor,
The compiler apparatus includes:
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition means detects an instruction for guaranteeing that data indicated by a pointer variable indicated by a specific variable name is a value of an alignment in the source program,
The optimization unit assumes that the data indicated by the pointer variable that is the target of the instruction detected by the instruction acquisition unit is arranged in the memory area with the guaranteed alignment value, and performs the optimization. System characterized by applying.   The system of claim 4, wherein the pointer variable is an argument.   The system of claim 4, wherein the pointer variable is a local variable.   The said optimization means produces | generates the pair instruction | indication which transfers two or more data simultaneously about the memory access instruction | indication which accesses the said data arrange | positioned in the memory area. The system described in. A compiler device that translates a source program into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition unit detects an instruction for guaranteeing a minimum value of the number of repetitions of a specific loop process in the source program,
The optimizing unit suppresses generation of an escape code necessary when the guaranteed minimum value is 1 or more and the number of repetitions is zero. A compiler device that translates a source program into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition unit detects an instruction for guaranteeing a minimum value of the number of repetitions of a specific loop process in the source program,
The compiler device, wherein the optimization means performs optimization by loop unrolling when the guaranteed minimum value is a value equal to or greater than the number of expansions by loop unrolling. A compiler device that translates a source program into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition means detects an instruction for ensuring that the number of repetitions of a specific loop process is an odd value or a set of even values in the source program,
The compiler apparatus according to claim 1, wherein the optimization unit performs optimization by loop unrolling according to whether the guaranteed set of values is a set of only even values or a set of only odd values. A compiler device that translates a source program into a machine language program,
An instruction acquisition means for acquiring an instruction to optimize the machine language program to be generated;
An optimization unit that performs optimization by generating a machine language instruction sequence according to the acquired instruction,
The instruction acquisition means detects an instruction for guaranteeing that data indicated by a pointer variable indicated by a specific variable name is a value of an alignment in the source program,
The optimization unit assumes that the data indicated by the pointer variable that is the target of the instruction detected by the instruction acquisition unit is arranged in the memory area with the guaranteed alignment value, and performs the optimization. A compiler device characterized by being applied.   The compiler apparatus according to claim 11, wherein the pointer variable is an argument.   The compiler apparatus according to claim 11, wherein the pointer variable is a local variable.   The said optimization means produces | generates the pair instruction | command which transfers two or more data simultaneously about the memory access instruction | indication which accesses the said data arrange | positioned in the memory area. The compiler apparatus described in 1.

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