JPH1028072A - Local oscillation circuit using plural frequency synthesizers - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a local oscillation circuit which can prevent the occurrence of frequency fluctuation by improving the isolation between a plurality of synthesizers and is suitable for TDMA radio equipment. SOLUTION: The synthesizer output S1a from a frequency synthesizer 1A becomes a local oscillation signal S2a through a multiplying circuit 20A which multiplies the output S1a by 3/2. The synthesizer output S1b from another frequency synthesizer 1B becomes another local oscillation signal S2b through a multiplying circuit 20B which multiplies the output S1b by 3/2. An output selection switch 40A alternately selects and outputs the synthesizer outputs S1a and S1b as a local oscillation signal S4a for output at every TDMA time slot upon receiving a switch signal S3a from the control section of radio equipment. The switch signal S3a disconnects the power supply from a local oscillation power source 30A to the multiplying circuits 20 when the circuits 20 generate nonselected local oscillation signals S3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a simple telephone (PH)
The present invention relates to a local oscillation circuit using a multi-frequency synthesizer suitable for a TDMA digital wireless device requiring high-speed frequency switching (channel switching) such as S).

[0002]

2. Description of the Related Art A conventional local oscillation circuit using a multi-frequency synthesizer is used for superheterodyne frequency conversion of a transmission signal and a reception signal of a digital radio, and a TDMA time slot of a local oscillation signal to be generated is used. It is required to be able to perform high-speed frequency switching every time and to have high frequency stability. Hereinafter, a local oscillation circuit using a multi-frequency synthesizer according to the related art, which is used in the above-described digital radio, will be described with reference to the block diagram of FIG.

The local oscillator circuit shown in FIG. 4 uses two frequency synthesizers 10G and 10H to synthesizer outputs S1g and S1 which are high frequency signals having high frequency stability.
get h. Synthesizer outputs S1g and S1h are buffer-amplified by buffer amplifiers 60A and 60B, respectively, and amplified local oscillation signals S2g and S2.
h is supplied to different selection terminals of the output selection switch 40C. The output selection switch 40C is switched and controlled by a switching signal S3a supplied from the control unit of the digital radio to the switching terminal 50A, and switches one of the local oscillation signals S2g and S2h to the transmission and reception heterodyne of the radio. The local oscillation signal S4c to be distributed and supplied to the frequency converter is used.

The frequency synthesizer 10G divides the frequency of the synthesizer output S1g by the frequency division number corresponding to the frequency setting signal supplied from the control unit, and the frequency stability generated by the crystal oscillator incorporating the frequency division signal is high. A phase locked loop (PL) that generates a phase error signal by comparing with a reference signal
L) 1G, a low-pass filter 2G that generates a frequency control signal by limiting the phase error signal from the PLL 1G to a predetermined loop band, and a voltage control that generates a synthesizer output S1g of a predetermined frequency in response to the frequency control signal. And an oscillator (VCO) 3G. Frequency synthesizer 10H
Is the same as the synthesizer 10G except that the output timing (TDMA time slot) of the synthesizer output S1h is different from that of the synthesizer output S1g. That is, the phase locked loop 1H is 1G, the low-pass filter 2H is 2G, and the voltage controlled oscillator 3H is 3G.
Respectively.

Here, the local oscillator circuit shown in FIG. 4 is provided with two frequency synthesizers 10G and 10H because the TDMA
This is because in the digital radio of the system, the local oscillation signal S4c can be switched within a wide frequency variable band in fine frequency steps and at a high speed. For example, the local oscillation signal S4c has a frequency of 1646.7 MHz to 166
TDMA in 9.5MHz range in 300KHz steps
It is necessary to switch every time slot. For this reason, the radio using the local oscillation circuit transmits the frequency setting signal to the frequency synthesizers 10G and 10H for each TDMA time slot including the transmission time slot of the transmission signal and the reception time slot of the reception signal from the control unit. In addition to supplying alternately, the switching signal S3a is sent to the output selection switch 40C to alternately connect the selection terminals to the corresponding frequency synthesizers 10G and 10H, thereby outputting the local oscillation signal S4c of a predetermined frequency.

However, the frequency synthesizer 10G
When the output terminals of the frequency synthesizers 10H and 10H are directly connected to the selection terminal of the output selection switch 40C, the output terminals of the frequency synthesizers 10G and 10H are coupled to each other via the output selection switch 40C, and the synthesizer outputs S1g and S1h interfere with each other, Is shaken, and a predetermined frequency stability cannot be obtained in the local oscillation signal S4c. Therefore, in the local oscillation circuit of FIG.
A buffer amplifier 60A is disposed between the frequency synthesizer 10G and the output selection switch 40C, and a buffer amplifier 60B is disposed between the frequency synthesizer 10H and the output selection switch 40C, and transmitted through the output selection switch 40C between the frequency synthesizers 10G and 11H. The signal isolation is increased to reduce the signal interference between both synthesizers.

[0007]

In the above-described local oscillator circuit using a plurality of frequency synthesizers according to the prior art, the signal interference due to the output selection switch among the signal interference between the two frequency synthesizers can be reduced by the arrangement of the buffer amplifier. As a result, the mutual coupling of the synthesizer outputs between the buffer amplifiers is newly generated, and it is still necessary to strictly shield the connection circuit to both frequency synthesizers, and the complexity and weight increase of the local oscillation circuit can be avoided. There was no problem.

Further, in the above-mentioned local oscillation circuit, a signal which is not selected as a desired local oscillation signal leaks from the output selection switch and is supplied to the transmission and reception heterodyne frequency converters of the digital radio. there were. If the frequency of the signal from the frequency synthesizer that is not selected matches the frequency of the received signal, intermediate frequency signal, or image signal of the heterodyne frequency converter, the reception performance of the received signal deteriorates due to intermodulation distortion or the like. This can cause problems.

[0009]

According to the present invention, a local oscillator circuit using a multiple frequency synthesizer according to the present invention comprises a set TDM.
A plurality of frequency synthesizers each generating a first high-frequency signal having a frequency corresponding to the A time slot, and the first high-frequency signal generated by the connected frequency synthesizer connected to each of the frequency synthesizers. A multiplying circuit for multiplying a second high-frequency signal having a frequency proportional to the frequency of the one high-frequency signal;
An output selection switch for selecting and outputting corresponding to each of the A time slots, and a local oscillation circuit power supply for cutting off power supply to the multiplier circuit that generates the second high frequency signal that is not selected and output.

One of the local oscillator circuits using the multi-frequency synthesizer is that each of the multiplying circuits includes a frequency divider that divides the first high frequency signal by two, and an output of the frequency divider. And a three-fold multiplier.

[0011] The local oscillator circuit using the plurality of frequency synthesizers includes a plurality of the frequency synthesizers which alternately generate the first high frequency signal corresponding to each of the set TDMA time slots. The following configuration can be adopted.

A local oscillator circuit using a multi-frequency synthesizer according to the present invention includes a frequency converter for generating a first high-frequency signal having a frequency corresponding to a set TDMA time slot. Doubling circuits are connected to the second high-frequency signal having a frequency proportional to. The output selection switch converts the second high frequency signals from the plurality of multipliers into TDs.
Selective output is performed corresponding to each of the MA time slots. Here, the local power supply circuit cuts off the power supply to the multiplier circuit that generates the second high-frequency signal that is not selectively output.

Since the above-mentioned power-supply interrupted doubler acts as an attenuator, the frequency synthesizer in use (output selected) can be connected to another (power-off) multiplier. Signal interference is less likely to occur, and no harmful signal from the multiplier during power supply interruption is output from the output selection switch. Further, even if a harmful signal is input to the output selection switch from the transmitting and receiving heterodyne frequency converter, the operation of the frequency synthesizer is not performed because the multiplier has an isolation effect on the backward signal. There is no fear of stabilization.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a local oscillator circuit using a multi-frequency synthesizer according to the present invention.

The local oscillation circuit shown in FIG. 1 is a heterodyne frequency converter for converting a reception signal of a digital radio into a reception intermediate frequency signal by a heterodyne frequency converter (down converter). This is a circuit that generates a transmission local oscillation signal to be converted into a transmission signal by an (up-converter). This local oscillator circuit has two frequency synthesizers 1
Synthesizer outputs S1a and S1b, which are high frequency signals with high frequency stability, are obtained from 0A and 10B.
The multiplier circuits 20A and 20B output the synthesizer output S
1a and S1b are multiplied by a high-frequency signal having a frequency proportional to the respective frequencies, that is, the synthesizer outputs S1a and S1b are multiplied by 3/2 to generate a local oscillation signal S1b.
2a and S2b.

The multiplier circuits 20A and 20B are:
An active circuit, a local oscillation power supply (local oscillation circuit power supply) 30A
Is receiving power from Local oscillation signals S2a and S2b are supplied to different selection terminals of output selection switch 40A, respectively. Here, the local oscillation signal S2
a and 2b also have a frequency of 1646.7 MHz to 1669.5 MHz, similarly to the local oscillation signal S4c in FIG.
This is a signal that switches the range of z for each TDMA time slot in 300 KHz steps. Accordingly, the frequency range of the synthesizer outputs S1a and S1b generated by the frequency synthesizers 10A and 10B is 1097.8.
MHz to 1113.0 MHz.

The output selection switch 40A is controlled to be switched by a switching signal S3a supplied from a control unit of the digital radio to the switching terminal 50A, and transmits one of the local oscillation signals S2a and S2b for transmission and reception of the radio. Oscillating signal S4a to be supplied to the heterodyne frequency converter for use. Here, the local power supply 30A is
Under the control of the switching signal S3a, the local oscillation signal S2a not selected and output from the output selection switch 40A.
And S2b, the power supply to the multiplier circuit 20A or 20B is cut off. When the power supply is stopped, the multiplier circuits 20A and 20B form an attenuation circuit for the synthesizer outputs S1a and S1b and the local oscillation signals S2a and S2b.

The frequency synthesizer 10A divides the synthesizer output S1a by a frequency division number corresponding to the frequency setting signal supplied from the control unit, and has a high frequency stability generated by a crystal oscillator incorporating the frequency division signal. A phase locked loop (PL) that generates a phase error signal by comparing with a reference signal
L) 1A, a low-pass filter 2A that generates a frequency control signal by limiting the phase error signal from the PLL 1A to a predetermined loop band, and a voltage control that generates a synthesizer output S1a having a predetermined frequency in response to the frequency control signal. And an oscillator (VCO) 3A. Frequency synthesizer 10B
Is the same as the synthesizer 10A except that the output timing (TDMA time slot) of the synthesizer output S1b is different from that of the synthesizer output S1a. That is, the phase-locked loop 1B is 1A, the low-pass filter 2B is 2A, and the voltage-controlled oscillator 3B is 3A.
Respectively.

The multiplier circuits 20A and 20B respectively divide the synthesizer outputs S1a and S1b by two.
It comprises frequency dividers 4A and 4B and three multipliers 5A and 5B for multiplying the outputs of the two frequency dividers 4A and 4B by three, respectively. 2 frequency dividers 4A and 4B and 3 multipliers 5
Each of A and 5B can use a transistor saturation amplifier, and selectively outputs a 2nd frequency and a 3rd harmonic from distortion signals output from the saturation amplifier.

The local power supply 30A is connected to the multiplier circuit 20.
A stabilized power supply 7 for generating a bias voltage supplied to A and 20B, and a power switch 6A for switching the supply of the bias voltage generated by the stabilized power supply 7 to the doubling circuit 20A or 2B. The power switch 6A switches the supply of the bias voltage to the doubler circuit 20A or 2B under the control of the switching signal S3a. The power switch 6A and the output selection switch 40A use transistor switches that can operate at high speed.

FIG. 2 is a waveform diagram for explaining the operation of the local oscillator circuit using a plurality of synthesizers of FIG.

The digital radio using the local oscillator circuit of FIG. 1 described above has four consecutive transmission time slots T
1, T2, T3, and T4 and four consecutive reception time slots R1, R2, R3, and R4 by one TDMA-T
The transmission / reception timing for the DD frame is set. One time slot is 625 μS, 1 TDMA-52
Two frames are 5 mS. The switching terminal 50 of the local oscillator circuit receives a switching signal S3 from the control unit of the radio device, which switches between H level and L level for each time slot.
Receive a. When the switching signal S3a is at the H level, only the multiplier circuit 20A is supplied with power from the local oscillator power supply 30A and is turned on.
The local oscillation signal S2a where A occurs is output select switch 40
A is selected and output as the local oscillation signal S4a.
When the switching signal S3a is at the L level, only the multiplier circuit 20B is supplied with power from the local power supply 30B to be turned on, and the local oscillation signal S2b generated by the multiplier circuit 20B is supplied to the output selection switch 40A. The signal is selected and output as the local oscillation signal S4a.

As described above, the frequency synthesizer 10A
Synthesizer output S1a from time slot T1,
In T3, R1 and R3, the frequency synthesizer 1
The synthesizer output S1b from 0B is the time slot T
2, T4, R2, and R4 are used as local oscillation signals S4a. During use of the frequency synthesizer 10A, the frequency synthesizer 10B performs a frequency switching operation to another frequency, and during use of the frequency synthesizer 10B, the frequency synthesizer 10A performs a frequency switching operation to another frequency.

The local oscillation circuit of FIG. 1 will be described with a specific frequency example. Assuming that the set frequency of the local oscillation signal S4a in the time slot T1 is 1646.7 MHz, the frequency synthesizer 10A uses a PLL circuit to generate a frequency of 1097.8 MHz. Synthesizer output S1a
Is generated. Synthesizer output S1a is 2 by 2 divider 4A.
The signal is divided into 548.9 MHz signals. This signal becomes a local oscillation signal S2a having a frequency of 1646.7 MHz, which is tripled by the tripler circuit 5A. Frequency synthesizer 10B
The multiplier circuit 20B operates in the same manner as described above. When the frequency of 1669.5 MHz is set in the time slot T3, the control unit outputs the synthesizer output S1a of the frequency synthesizer 10A to 11 while the frequency synthesizer 10 is used in the time slot T2.
The frequency is switched to 13 MHz.

As described above, the local oscillator circuit using a plurality of synthesizers shown in FIG. 1 uses the two frequency synthesizers 10A and 10B alternately for each time slot even when the desired frequency of the local oscillation signal S4a differs for each TDMA time slot. By using the switching, the local oscillation signal S4a of the desired frequency can be output. This local oscillation circuit includes frequency synthesizers 10A and 10B and an output selection switch 40A.
0A and 20B, and the unused one of the doubling circuits 10A and 10B operates as an attenuation circuit.
There is an effect that signal interference between the A-side circuit and the 10B-side circuit is further reduced.

FIG. 3 is a block diagram showing another embodiment of a local oscillator circuit using a multi-frequency synthesizer according to the present invention. This local oscillation circuit has four systems of a frequency synthesizer and a doubling circuit connected thereto. Therefore, the frequency switching speed of the local oscillation signal S4b output from the local oscillation circuit is about twice that of the local oscillation circuit in FIG.

The frequency synthesizers 10C and 10 shown in FIG.
D, 10E, and 10F have the same configuration and perform the same operation as the frequency synthesizer 10A or 10B in FIG. In addition, synthesizers 10C, 10D, 10E
And a doubler circuit 20C connected to 10F, respectively.
20D, 20E and 20F are also the same as those shown in FIG.
It has the same configuration as A or 20B and performs the same operation. The output selection switch 41A selects one of the local oscillation signal S2c from the multiplier circuit 20C and the local oscillation signal S2d from the multiplier circuit 20D as the local oscillation signal S41a, and the output selection switch 41B selects the local oscillation signal from the multiplier circuit 20E. One of the oscillation signal S2e and the local oscillation signal S2f from the multiplier 20F is selected as the local oscillation signal S41b. The output selection switch 40B selects one of the local oscillation signal S41a and the local oscillation signal S41b as the local oscillation signal S4b.

Output selection switches 41A, 41B and 4
0B is controlled by a switching signal S3b received by the switching terminal 50B from the control unit. The switching signal S3b needs to correspond to four switching states by the output selection switches 41A, 41B and 40B. For this reason, the output selection switches 41A, 41
A signal line may be wired to each of B and 40B, and a switching signal S3b having a different pattern may be sent to each of the output selection switches 41A, 41B and 40B. Further, the control unit sends a 2-bit switching signal S3b of the same pattern to all of the output selection switches 41A, 41B and 40B, and the output selection switches 41A, 41B.
B and 40B may decode the switching signal S3b to determine their own switching. Local power 3
Since the power switch 6A of 0A also has four switching states, the power supply to the doubler circuit and the power supply cutoff are controlled in the same manner as the switching of the output selection switch.

Since the local oscillation circuit shown in FIG. 3 has four local oscillation signal generation circuits, one local oscillation signal generation circuit, for example, a frequency synthesizer 10C and a multiplication circuit 2
In the system of 0C, the output selection switch 40B switches to 4TDMA.
The local oscillation signal S4b may be output once in a time slot. Therefore, one local oscillation signal generation circuit can use 3TDMA time slots for frequency switching, and this local oscillation circuit is characterized by a high ability to respond to high-speed frequency switching. When a higher-speed frequency switching is required, it is possible to cope with any high-speed frequency switching by preparing more local oscillation signal generation circuits.

[0031]

As described above, the local oscillator circuit using the multi-frequency synthesizer according to the present invention is connected to each of the plurality of frequency synthesizers for generating the first high-frequency signal, and converts the first high-frequency signal into this signal. A multiplying circuit for multiplying a second high-frequency signal having a frequency proportional to the frequency of the first high-frequency signal, and the second high-frequency signals from the plurality of multiplying circuits corresponding to each of the TDMA time slots And a local oscillation circuit power supply for shutting off the power supply to the multiplier circuit which generates the second high frequency signal which is not selected and output, so that an isolator between the plurality of frequency synthesizers is provided. And the fluctuation of the frequency of the first high-frequency signal, that is, the second high-frequency signal output from the output selection switch. There is an effect that it is possible to reduce the frequency fluctuation of the wave signal.

Further, this local oscillation circuit has an effect that the second high-frequency signal having good frequency stability can be obtained without using any number of buffer circuits after the frequency synthesizer.

Further, in this local oscillation circuit, the second
Since the power supply to the multiplier circuit that does not selectively output a high frequency signal from the output selection switch is interrupted, the power-supplied multiplier circuit acts as an attenuator, and the first high frequency signal from the unused frequency synthesizer is used. Leakage can be prevented, and generation of spurious signals other than the desired second high-frequency signal can be reduced. As a result, strict shielding is not required for each frequency synthesizer and its connection circuit, so that the configuration of the local oscillation circuit is simplified and the weight and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a local oscillator circuit using a multiple frequency synthesizer according to the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the local oscillator circuit using the multi-frequency synthesizer according to the present invention.

FIG. 4 is a block diagram showing a local oscillator circuit using a multi-frequency synthesizer according to the related art.

[Explanation of symbols]

 1A, 1B Phase locked loop (PLL) 2A, 2B Low-pass filter 3A, 3B Voltage controlled oscillator (VCO) 4A, 4B Divider (× 1/2) 5A, 5B 3 Multiplier (× 3) 6A , 6B power switch 7 stabilized power supply 10A to 10F frequency synthesizer 20A to 20F multiplication circuit 30A, 30B local oscillator power supply 40A, 40B, 41A, 41B output selection switch 50A, 50B switching terminal

Claims (3)

[Claims] 1. A plurality of frequency synthesizers each generating a first high-frequency signal having a frequency corresponding to a set TDMA time slot, and the frequency synthesizers connected to and connected to each of the frequency synthesizers. A multiplying circuit for multiplying the first high-frequency signal by a second high-frequency signal having a frequency proportional to the frequency of the first high-frequency signal; and converting the second high-frequency signals from the plurality of multiplying circuits to the TDMA signal. An output selection switch for selecting and outputting a time slot corresponding to each of the time slots; and a local oscillation circuit power supply for cutting off power supply to the multiplier circuit that generates the second high frequency signal that is not selected and output. A local oscillator circuit using a multi-frequency synthesizer. 2. Each of the multipliers includes a divide-by-2 frequency divider that divides the first high frequency signal by two, and a divide-by-multiplier that multiplies the output of the divider by three. 2. The local oscillator circuit according to claim 1, wherein the local oscillator circuit uses a multi-frequency synthesizer. 3. The frequency synthesizer according to claim 1, wherein said plurality of frequency synthesizers comprise two frequency synthesizers which alternately generate said first high frequency signal respectively corresponding to each of said set TDMA time slots. 3. A local oscillation circuit using a multi-frequency synthesizer according to claim 2.