JPH10275918A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the turn off breakdown without degrading the operational characteristics of element by a method wherein, when the title semiconductor device is applied with an over voltage in turning off, the structure absorbing the energy given by the over voltage as the main current is integrated. SOLUTION: Within an over voltage protective region 10, a cathode electrode 2 is connected to an auxiliary electrode 20 as well as an anode electrode 3 is connected to another auxiliary electrode 30 so as to lower the impurity concentration than that in a P layer in contact with the auxiliary electrode 20 as well as an n buffer layer 6 otherwise an n layer 11 in the shallowed diffusion depth from the surface of the anode electrode 3 is formed. Since this n layer 11 is depleted more easily than the n buffer layer 6, the punch through phenomenon occurs most rapidly in the over voltage protective region 10 so that the breakdown strength in the region 10 may be set up lower than that in a main element region 9 for absorbing the energy given when the semiconductor is applied with the over voltage in turning off thereby enabling the permanent breakdown of an element to be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to SIT, SI thyristor, GTO thyristor, IGBT, MCT, EST
And the like having a overvoltage protection region.

[0002]

2. Description of the Related Art FIG. 8 is a cross-sectional view of a semiconductor device in which an overvoltage detection function is added to a generally well-known SI thyristor, wherein reference numeral 1 denotes a gate electrode, 2 denotes a cathode electrode, Is the anode electrode, 4 is the p base layer, 5
Is a p emitter layer, 6 is an n buffer layer, 7 is an n base layer,
Reference numeral 9 denotes a main element region, 110 denotes an overvoltage detection region, and 11 denotes an n layer. The impurity concentration is lower than that of the buffer layer 6 and the diffusion depth from the anode surface is shallower. By doing so, the n layer 11 is more likely to be depleted than the n buffer layer 6, and the withstand voltage of the overvoltage detection region 110 can be made lower than the withstand voltage of the main element region 9, so that when an overvoltage is applied to the element, it is instantaneous. An avalanche current or a punch-through current is generated and detected as a gate current. In this example, the n buffer layer 6 facing the p base layer 4
The n-layer 11 is formed at a portion of the overvoltage detection region 1
10 is added.

FIG. 9 is a sectional view of an IGBT with a built-in overvoltage protection function.
-93-27 / SPC-93-49. In this conventional example, reference numeral 10 denotes an overvoltage protection region. By forming a p-layer 15 shallower than the p-base layer 4, avalanche occurs at a voltage lower than the withstand voltage of the main element region 9, and the energy of the overvoltage is reduced. It converts it to current and adds a protection function. In addition, 20 and 30
Is an auxiliary electrode, 20 is connected to the cathode electrode 2,
Reference numeral 30 is connected to the anode electrode 3.

[0004]

When a semiconductor device is applied to a PWM type inverter circuit or a voltage resonance circuit, an element may generate a surge at the time of turn-off operation due to an unexpected trouble on the circuit or inductance of a circuit wiring or the like. There was a danger of turn-off destruction due to overvoltage. If the element has a high withstand voltage by increasing the thickness of the n-base layer in order to secure a sufficient withstand voltage, the on-voltage (on-resistance) increases.
Turn-on loss and turn-off loss also increase.

In the conventional semiconductor device shown in FIG. 8, when an overvoltage is applied, energy based on the overvoltage is absorbed as a gate current to prevent element destruction. If it becomes large, there is a risk of breaking the gate circuit. In the conventional method, it is possible to add a device for detecting a gate current to the gate circuit, and to provide a means for immediately activating the protection device when an overvoltage is detected to prevent destruction. It is not preferable because the weight and volume increase. The present invention has been made in view of the above points, and aims at solving these problems, preventing turn-off breakdown without deteriorating the operation characteristics of the element, and achieving sufficient overvoltage breakdown. An object of the present invention is to provide a semiconductor device having a withstand voltage.

[0006]

Means for attaining the object is to integrate a structure for absorbing energy based on the overvoltage as a main current when an overvoltage is applied during a turn-off operation.

More specifically, a base made of a first one-conductivity-type semiconductor layer and a first anti-conductivity-type semiconductor layer provided in the vicinity of the first main electrode and the control electrode. An emitter layer comprising a second conductive type semiconductor layer having a second main electrode at a position facing the first semiconductor layer via the base layer and the first semiconductor layer; In a semiconductor device having a buffer layer made of a second anti-conductivity type semiconductor layer provided therebetween, an auxiliary electrode connected to the first main electrode, and a third electrode in the base layer in contact with the auxiliary electrode. A first conductivity type semiconductor layer, at least one of the buffer layers facing the third one conductivity type semiconductor layer;
A third anti-conductivity type semiconductor layer having a low impurity concentration or a shallow depth, and a second anti-conductivity type semiconductor layer provided at a position facing the third anti-conductivity type semiconductor layer via the emitter layer. The second auxiliary electrode is connected to the second main electrode.

According to a second aspect of the present invention, the overvoltage protection region is formed by increasing the impurity concentration or increasing the depth of at least one region of the emitter layer. In this case, it can be realized regardless of the presence or absence of the buffer layer.

According to a third aspect of the present invention, the overvoltage protection region is formed with a high impurity concentration or a large depth in at least one region of the buffer layer.

According to a fourth aspect of the present invention, the third one conductivity type semiconductor layer in the overvoltage protection region is selectively formed.

According to a fifth aspect of the present invention, an isolation region is provided between the overvoltage protection region and the main element region.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional structural view of an embodiment according to claim 1 of the present invention. In the drawing, a region indicated by reference numeral 10 is a region having an overvoltage protection function, and is hereinafter referred to as an overvoltage protection region. The reference numerals in FIG.
Those having the same reference numerals as those in FIG. 9 have the same configurations and functions.

The overvoltage protection region 10 includes an auxiliary electrode 20 connected to the cathode electrode 2, an auxiliary electrode 30 connected to the anode electrode 3, a p-layer 15 in contact with the auxiliary electrode 20, and an n-buffer. An n layer 11 having a lower impurity concentration than the layer 6 or a shallower diffusion depth from the anode surface. By doing so, since the n-layer 11 is more likely to be depleted than the n-buffer layer 6, punch-through occurs most quickly in the overvoltage protection region 10. As a result, the withstand voltage of the overvoltage protection region 10 can be set lower than that of the main element region 9, and when an overvoltage is applied, the energy is absorbed as a current so that the element is not permanently destroyed. can do. That is, as compared with an element not having the overvoltage protection region 10, the breakdown voltage resistance against overvoltage is significantly improved. In this case, the withstand voltage of the entire device is determined by the withstand voltage of the overvoltage protection region 10. This value may be a voltage required from the application circuit, and the impurity concentration and diffusion depth of n layer 11 are determined so as to satisfy the set conditions.

The element structure is significantly different from the conventional example shown in FIG. 8 in that a p-layer 15 in contact with the auxiliary electrode 20 is formed. That is, when an overvoltage is applied to the element, the current flowing in the overvoltage protection region 10 is in contact with the auxiliary electrode 20 connected to the cathode electrode 2, so that the current flows from the gate electrode 1 to the outside of the element as in the conventional example. The current does not flow to the gate circuit but flows from the cathode electrode 2 to the main current path. Overvoltage can be due to accidental trouble, and its magnitude may not be predictable,
Even if an overvoltage exceeding expected is applied, if the current flows through the main current path, it is possible to request that the gate circuit be made as small as possible.

Next, the difference from the conventional example shown in FIG.
In the case of FIG. 9, the protection function is added by devising the structure of the p base layer.
The difference is that the joint structure on the side (the anode electrode 3 side) is devised. In order to convert the energy of the applied overvoltage into a current, the punch-through effect can be used to increase the breakdown strength compared to the avalanche effect as in the conventional example shown in FIG.

Although only one n-layer 11 is present in FIG. 1, it goes without saying that the present invention can be implemented in exactly the same manner when there are a plurality of n-layers. The auxiliary electrodes 20 and 30 are connected to the cathode electrode 2 and the anode electrode 3, respectively, but are not limited by the connection method at all.
Any method may be used. As a specific method, for example, a method of connecting by patterning aluminum or the like on the element surface, a method of connecting by wire bonding, or a metal thermal buffer plate generally widely used in a pressure contact type element for overvoltage protection. For example, there is a method of connecting the area 10 so as to be in contact therewith.

When the impurity concentration of the n-layer 11 is reduced or miniaturized, an electrostatic induction effect acts on the n-layer 11. That is, even when the voltage increase rate during the turn-off operation is extremely high, it is possible to obtain an overvoltage protection region that functions properly. Further, the manufacturing method of this embodiment may be a method configured by a combination of existing general semiconductor processes. That is, for example, in the formation of the n-layer 11, a diffusion source for forming the n-buffer 6 is formed in a region other than the overvoltage protection region 10 using a photolithography technique, heat-treated, and formed by lateral diffusion. Should be taken. If it is desired to more precisely define the impurity concentration and the diffusion depth of the n-layer 11, an ion implantation technique may be further used. In forming the p-layer 15, a p-layer may be formed only in the overvoltage protection region 10 using a photolithography technique, and the depth may be adjusted by heat treatment.

FIG. 2 is a cross-sectional view of one embodiment of the present invention, in which the p-layer 12 in the overvoltage protection region 10 has a higher impurity concentration than the p-emitter layer 5 and diffuses from the anode surface. The depth is formed deep. As a result, when a reverse voltage is applied to the element, the depletion layer spreading in the n-buffer layer 6 easily reaches the p-layer 12 faster than reaches the p-emitter layer 5, and the overvoltage protection region 10
Will result in the fastest punch-through. As a result, the withstand voltage of the overvoltage protection region 10 can be set lower than that of the main element region 9. FIG. 2 shows a p-layer 1
Although only one exists, the present invention can be implemented in exactly the same manner when there are a plurality of them.
Further, the structure shown in FIG. 2 has a structure having the n-buffer layer 6, but a structure without the n-buffer layer 6 can be implemented according to exactly the same principle. Note that the manufacturing method of this embodiment can also be configured by a combination of existing semiconductor processes.

The overvoltage protection region 10 in the first and second aspects is designed so that the junction structure on the anode electrode 3 side is designed so that the punch-through phenomenon occurs at a voltage slightly lower than the element withstand voltage. It is desirable to apply to an element whose element withstand voltage is determined by the punch-through phenomenon. The reason is that, when applied to an element whose element withstand voltage is determined by the avalanche phenomenon, the temperature dependence of the punch-through phenomenon and the avalanche phenomenon is opposite, so that the optimum design becomes slightly difficult.

In the above description, the overvoltage protection region is realized by using the punch-through phenomenon. Claim 3 realizes the overvoltage protection region by using avalanche breakdown. FIG. 3 is a sectional structural view of an embodiment according to claim 3, wherein the n-layer 13 in the overvoltage protection region 10 has a higher impurity concentration than the n-buffer layer 6 and has a deeper diffusion depth from the anode surface. ing. As a result, when a reverse voltage is applied to the element, the electric field intensity in the overvoltage protection region 10 is higher than the electric field intensity in the other regions, so that the avalanche breakdown is most likely to occur in the overvoltage protection region 10. That is, the withstand voltage of the overvoltage protection region 10 can be set lower than that of the main element region 9. FIG. 3 shows the n-layer 1
Although only one is present, the present invention can be implemented in exactly the same manner when there are a plurality of these.
In the structure according to the third aspect of the present invention, in consideration of the temperature characteristics, the withstand voltage of the overvoltage protection region 10 is determined by the avalanche phenomenon. Therefore, it is preferable to apply the invention to an element whose element withstand voltage is determined by the avalanche phenomenon. Note that the manufacturing method of this embodiment can also be configured by a combination of existing semiconductor processes.

In any of the first, second and third aspects of the present invention described above, the overvoltage protection region 1
Since it is necessary to set the breakdown voltage of 0 to be lower than that of the main element region 9, it is desirable that the depth of the p layer 15 be equal to or less than the p base layer 4. Alternatively, the shape of the p layer 15 may be as shown in FIG. The structure having the shape shown in FIG. 4 is a sectional structural view of the embodiment according to claim 4,
It is characterized in that the layer 15 is selectively formed. Even if the diffusion depth is the same as that of the p base layer 4, individual p
By adjusting the distance between the layers 16, the withstand voltage of the overvoltage protection region 10 can be appropriately set. FIG.
Can be formed at the same time as the p-base layer 4, so that the number of manufacturing steps does not increase even if the overvoltage protection region 10 is added. Note that the manufacturing method of this embodiment can also be configured by a combination of existing semiconductor processes.

When the main element region 9 is an element using epitaxial growth on the cathode side, such as a buried gate type SI thyristor, the p-layer 16 as shown in FIGS. Also, the overvoltage protection region 10 can be added without increasing the number of manufacturing steps. If the carrier lifetime control is performed extremely strongly on the overvoltage protection region 10, there is a danger that the device will be destroyed when an overvoltage is applied and a current is generated. Therefore, the carrier lifetime control is not performed on the overvoltage protection region 10 as much as possible. It is necessary to optimize the structure by miniaturization or the like. Therefore, the structures shown in FIGS. 5 and 6, which can be made finer than the structure shown in FIG. 4, are suitable for the overvoltage protection region 10. The gist of the present invention does not change even if the p-layer 15 has a structure composed of three or more stages, if necessary.

FIG. 7 is a sectional structural view of an embodiment of the semiconductor device according to claim 5 of the present invention, which is characterized in that an isolation region 8 is provided between the front voltage protection region 10 and the main element region 9. . FIG. 7 shows a specific structure of the isolation region 8 as a SISA (Static Indus) using an electrostatic induction effect.
1 shows an example using a Ction Separating Aria) structure. That is, the SISA structure is p
A plurality of p-type diffusion layers having the same depth as the base layer 4 are arranged at appropriate intervals. In addition to the structure applying this SISA structure, a structure applying LOCOS,
Structure applying high resistance by diffusion layer with low impurity concentration,
Various structures such as a structure in which a deep groove is cut are conceivable. As an extreme example, a structure in which the overvoltage protection region 10 and the main element region 9 are completely mechanically separated from each other and incorporated into one package may be included. Note that the manufacturing method of this embodiment can also be configured by a combination of existing semiconductor processes.

The overvoltage protection region of the present invention has a kind of diode structure, and the device to which the present invention is applied can be said to be a reverse conduction type device in which diodes are arranged in antiparallel between main electrodes of switching devices. In general, the reverse conduction type element has a higher withstand voltage of the diode arranged in antiparallel than the withstand voltage of the main switching element. If it is set low, the diode can also have the overvoltage protection function of the main switching element.

Although the embodiments of the present invention have all been described as being applied to a buried-gate SI thyristor, the present invention is not limited to a buried-gate SI thyristor. It goes without saying that the same holds true for semiconductor devices such as the type SI thyristor, SIT, GTO thyristor, IGBT, MCT, and EST. In addition, the present invention can be similarly applied to a horizontal structure as well as a vertical structure for any semiconductor device. Further, it goes without saying that the n-base layer 7 in the present invention is not limited to the n-type semiconductor but may be a p-type semiconductor or an intrinsic semiconductor as long as the impurity concentration is low. Further, the structure in which the conductivity types of the respective regions in the above embodiments are all reversed can be implemented without changing the gist of the present invention at all.

[0026]

As described above, according to the present invention, it is possible to provide a semiconductor device having a sufficient breakdown strength against an overvoltage such as a surge.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a first embodiment of the present invention.

FIG. 2 is a sectional structural view of a second embodiment of the present invention.

FIG. 3 is a sectional structural view of a third embodiment of the present invention.

FIG. 4 is a sectional structural view of a first embodiment according to claim 4 of the present invention.

FIG. 5 is a sectional structural view of a second embodiment according to claim 4 of the present invention.

FIG. 6 is a sectional structural view of a third embodiment according to claim 4 of the present invention.

FIG. 7 is a sectional structural view of an embodiment according to claim 5 of the present invention.

FIG. 8 is a sectional structural view of an example of the related art.

FIG. 9 is a cross-sectional structural view of an example of the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 gate electrode 2 cathode electrode 3 anode electrode 4 p base layer 5 p emitter layer 6 n buffer layer 7 n base layer 8 isolation region 9 main element region 10 overvoltage protection region 11, 13 n layer 12, 15, 16 p layer 20, 30 auxiliary electrode

Claims (5)

[Claims] A first conductive type semiconductor layer provided near a first main electrode and a control electrode; a base layer made of a first anti-conductive type semiconductor layer; An emitter layer comprising a second conductive type semiconductor layer having a second main electrode at a position facing the semiconductor layer, and a second anti-conductive type provided between the emitter layer and the base layer. In a semiconductor device having a buffer layer composed of a semiconductor layer, an auxiliary electrode connected to the first main electrode, a third one conductivity type semiconductor layer in the base layer in contact with the auxiliary electrode, At least one impurity concentration in the buffer layer facing the conductive type semiconductor layer is reduced or the depth of the third anti-conductive type semiconductor layer is reduced, and the third anti-conductive type semiconductor layer is interposed between the third conductive layer and the emitter layer. A second electrode provided at a position facing the conductive type semiconductor layer; A semiconductor device, comprising: an overvoltage protection region including an auxiliary electrode, wherein the second auxiliary electrode is connected to the second main electrode. 2. The overvoltage protection region is formed by increasing the impurity concentration or increasing the depth of at least one region of the emitter layer regardless of the presence or absence of the buffer layer. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein the overvoltage protection region has a high impurity concentration or a large depth in at least one region of the buffer layer. 4. The semiconductor device according to claim 1, wherein the third one-conductivity-type semiconductor layer in the overvoltage protection region is selectively formed. 5. The semiconductor device according to claim 1, further comprising an isolation region between said overvoltage protection region and said main element region.
Or the semiconductor device according to 4.