JPH10275839A - Method for evaluating reliability of insulating film of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for estimating reliability of an insulating film in a short time and at a low cost by which a wide-ranging statistical distribution properties in consideration of impact, such as declines in reliability caused by processes and reliability properties on the circuit level are obtained. SOLUTION: A constant voltage TDDB test is conducted on a MOS transistor 105 formed on a semiconductor substrate 100, by applying a voltage to a pad region 109. A cumulative failure rate distribution function obtained by the constant voltage TDDB test is converted according to the structure of a given semiconductor device with an arbitrary structure. A cumulative failure rate distribution factor of an insulating film of the semiconductor device of the arbitrary structure is determined by statistically integrating these figures.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method for evaluating the reliability of an insulating film formed on a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with miniaturization of semiconductor devices, reliability of the semiconductor devices has been regarded as important. For example, MO
S (Metal Oxide Semiconductor)
In an (or) type transistor, the reliability life of the gate oxide film determines the life of the semiconductor device itself. Therefore, when manufacturing the semiconductor device, an accurate life evaluation technique is required. In particular, in the process development after the 0.18 μm rule, the thickness of the gate oxide film is extremely thin as 6 nm or less, so that the reliability characteristics of the gate oxide film and the gate oxide film due to damage during a process such as a plasma process are reduced. Techniques for accurately evaluating reliability deterioration are further required.

As a method used for estimating the reliability life of a gate insulating film, a constant voltage TDDB (Time Depth) is used.
dent Dielectric Breakdown
n) Methods using tests are well known. In this constant voltage TDDB test, as shown in FIG. 13, a certain voltage is applied to the insulating film, the current value during the monitoring is monitored, and the time (TBD) at which the insulating film is destroyed with time is detected (FIG. 13). FIG. 14 shows a change in the gate current with a change in the stress application time). In such a test, an acceleration test is usually performed, and for an electric field larger than the electric field applied to the insulating film by applying a power supply voltage to the device, for example, for a 6 nm insulating film, a stress voltage of about 6 to 8 V is usually applied to the insulating film. Applied.

When estimating the life under actual operating conditions, the constant voltage TDDB is used for several types of voltages.
After conducting a test and deriving the dielectric breakdown time at each voltage, these dielectric breakdown times are logarithmically plotted against, for example, the stress voltage, and extrapolated from a straight line connecting them to obtain the actual operating voltage (Va). Of the dielectric breakdown life (Ta) of FIG.

[0005]

However, the above-mentioned dielectric breakdown time is essentially a parameter having a statistical distribution. Further, in an insulating film in an actual LSI,
Process variations during manufacturing, that is, variations in structure, process damage, etc., occur, and it is necessary to consider these. Furthermore, since the acceleration characteristics with respect to the stress voltage and stress temperature are functions of the area of the insulating film, the statistical distribution characteristics of the actual insulating film area and structure and the life of the insulating film under actual operating conditions in LSI are derived. To do so, it is necessary to evaluate a very large number of samples manufactured by a process equivalent to that of an actual LSI, which requires a great deal of time and cost.

As a means for expressing such a statistical property of the life of the insulating film, there is a concept of assuming a defect existing at a density according to a Poisson distribution in the surface of the insulating film. However, the expression of the statistical properties of the lifetime of the insulating film due to such a constant Poisson distribution defect is very effective for expressing the characteristics of the insulating film immediately after formation, but the actual L
It is impossible to indicate the lifetime of an insulating film that has been subjected to various structures and various process damages accompanying the various structures in the SI.

In particular, in a process for forming a fine device, for example, in a plasma process such as dry etching, damage to the gate insulating film is increased due to the increase in density of the plasma. Deterioration of yield is a problem. It is known that the yield deterioration of the gate insulating film due to such a process depends on the layout of the gate electrode wiring, and further, the coefficient of the insulating film reliability distribution characteristic changes depending on the plasma damage. Therefore, it is necessary to evaluate the life in consideration of the deterioration of the insulating film characteristics in the process.

[0008] Further, with the increase in device density and area, the need to evaluate the statistical distribution characteristics of the insulating film reliability over a wider range has increased.

In view of the above-mentioned problems, the present invention provides a method for evaluating the reliability of an insulating film in a short time and at low cost. The objective is to obtain a statistical distribution characteristic over a wide range and a reliability characteristic at a circuit level.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention combines the reliability evaluation results using a plurality of types of TEG patterns to reduce the evaluation with a minimum number of samples to reduce the actual circuit as a whole. The evaluation method to derive highly accurate reliability characteristics of the insulating film at the same time and the reliability evaluation test of many TEG patterns are performed at the same time, and the breakdown is efficiently detected by the emission microscope. Thereby, evaluation can be performed in a short time.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, the present invention will be described in detail with reference to the drawings. 1 and 2 are structural diagrams of a MOS transistor used in the method for evaluating a semiconductor device according to the first embodiment of the present invention, and FIG. 3 is a schematic diagram of a system for evaluating a statistical distribution characteristic of a gate insulating film lifetime. .

In FIG. 1, reference numerals indicate the following members. 1 (a) and 2 (a) are sectional views, and FIG.
(B) and FIG. 2 (b) show plan views.

Reference numeral 100 denotes a p-type semiconductor substrate; 101, an isolation insulating film; 102, a gate oxide film formed on the p-type semiconductor substrate 100; 103, a gate electrode formed on the gate oxide film 102; Shows an n-type impurity region formed on the type semiconductor substrate 100, and shows a semiconductor substrate 100, a gate oxide film 102, a gate electrode 103, a source,
The n-type impurity region 104 serving as a drain region allows M
An OS transistor 105 is formed. The metal wiring 108 is connected to the gate electrode 103 of the MOS transistor.
3 can be applied with a voltage.

In FIG. 2, the metal wiring 110 is
On the p-type semiconductor region 100, all the gate electrodes of the plurality of MOS transistor groups 111 formed simultaneously with the MOS transistor 105 in FIG.
By the pad region 112, the MOS transistor group 11
A voltage can be simultaneously applied to all the gate electrodes of the MOS transistor group 111. Here, all the single MOS transistors constituting the MOS transistor group 111 have the same constant value as the MOS transistor 105. It has a structure.

In FIG. 3, reference numeral 113 denotes a wafer stage; 114, a temperature control system for adjusting the temperature of the wafer stage 113; 115, a voltage source; 116, an ammeter;
Is a probe for applying a voltage to the gate electrode,
It is connected to the pad region 109 (in the case of FIG. 1) or the pad region 112 (in the case of FIG. 2). Reference numeral 118 denotes a probe for grounding the semiconductor substrate 100, and 119 denotes a control system for judging when the gate oxide film has been broken and stopping the voltage application.

First, using the evaluation system shown in FIG.
After connecting the probe 117 to the pad region 109, the MO
A constant voltage is applied to the gate electrode of S transistor 105 from voltage source 115. The electric field applied to the gate oxide film is
For example, it is about 11 to 13 MV / cm. At this time, the gate current flowing through the gate oxide film is monitored using an ammeter 116, and the time TBD during which the gate oxide film is
Is measured. At this time, as a method of determining the breakdown, for example, in the voltage application time dependency characteristic of the current density flowing when a constant voltage is applied to the gate oxide film shown in FIG. 14, the current density is sharp (for example, one digit or more within one second) Can be defined as the destruction time. Similarly, the above MOS
A plurality of MOS transistors (e.g., 20
Point), the above breakdown time TBD
Statistical distribution characteristic F1 (t) (FIG. 4A) can be obtained. Next, after connecting the probe 117 to the pad region 112, the same voltage as the above-described stress voltage is applied from the voltage source 115 to all the gate electrodes of the MOS transistor group 111, and the breakdown time TBD is evaluated. . Subsequently, by performing the same measurement on a plurality of MOS transistor groups (for example, 20 points) having the same structure as the MOS transistor group 109 formed under the same preparation conditions, the statistical distribution characteristic F2 of the breakdown time TBD is obtained. (T) (FIG. 4B) can be obtained. The above F1 (t) and F2 (t) will be referred to as a cumulative fault probability distribution function. Subsequently, conversion is performed on the statistical distribution characteristics F1 (t) and F2 (t) of the insulation time based on the following equations. In this way, the above cumulative fault probability distribution function can be converted according to the structure of the tested semiconductor.

[0017]

(Equation 1)

[0018]

(Equation 2)

Here, N, N1, and N2 are the number of transistors included in the circuit to be evaluated, the semiconductor device shown in FIG. 1, and the semiconductor device shown in FIG. 2, respectively.
= 5, N1 = 1, N2 = 25. That is, in this embodiment, conversion is performed according to the ratio of the number of transistors. For example, when about 20 evaluations are performed, F1 (t) and F2 (t) as actual measurement data each have a range of about 5 to 95%, and the F (T) is about 23 to 100%, (Equation 2)
Will have a range of about 1-45.1% each. These show statistical distribution characteristics of failures caused by oxide film destruction in the entire circuit including five MOS transistors. Therefore, by plotting both in a single graph, it is possible to obtain the statistical distribution characteristic of a very wide range of circuit faults of 1 to 100% from the evaluation of a very small number of samples of about 40 points in total. Yes (Figure 5).

In this embodiment, the statistical distribution characteristics of circuit faults in a very wide range of 1 to 100% can be obtained with a very small number of measurement points of 60 points in total.

In this embodiment, MOS transistor 105 and MOS transistor group 109
In each case, 20 points are measured, but by performing more evaluations, a more accurate cumulative failure probability distribution characteristic can be obtained. In the present embodiment, the MOS transistor (N1 = 1) and the MOS transistor
The cumulative failure probability distribution characteristic of the circuit of N = 5 is obtained using the two types of evaluation patterns of the transistor group (N2 = 25). By performing measurement using a larger number of types of evaluation patterns, A higher range of distribution characteristics can be obtained. For example, when 20 points are measured for an evaluation pattern of N3 = 100, F3 (t) has a range of about 0.05 to 3%. Therefore, F
By combining the three distribution characteristics 1 (t), F2 (t), and F3 (t), it is possible to obtain characteristics in the range of about 0.05 to 100%.

(Embodiment 2) FIG. 6 shows a structure of a semiconductor device according to Embodiment 2 of the present invention, and FIG. 7 shows a schematic diagram of an insulating film life evaluation system.

In FIG. 6, reference numeral 102 denotes a gate insulating film formed on a p-type semiconductor substrate;
2 shows a gate electrode formed on a semiconductor substrate, a gate insulating film 102, and a gate electrode 103;
A capacitor 120 is formed. Further, the gate electrode 103 is connected to the high-resistance wiring region 121. For example, as shown in FIG. 6, a high-resistance wiring region 121 can be realized by long running a polycrystalline silicon wiring having a width of about 0.2 μm. On the p-type semiconductor substrate, the MOS transistor 120 and the high-resistance wiring region 1
A plurality of 21 combinations are formed. Metal wiring 12
2 is connected to the gate electrodes of the plurality of MOS capacitors formed on the p-type semiconductor substrate via the high-resistance wiring region, and is connected to the plurality of MOS capacitors 120 via the high-resistance wiring region by the pad region 123. Can be simultaneously applied to all the gate electrodes. Here, the interval between the plurality of MOS capacitors formed on the semiconductor substrate is designed to be 2 μm or more.

In the insulating film life evaluation system shown in FIG. 8 using a semiconductor device (FIG. 6) comprising a plurality of MOS capacitors and a high resistance wiring region, reference numeral 113 denotes a wafer stage, and 114 denotes a temperature of the wafer stage 113. A temperature control system, 115 is a voltage source, 116 is an ammeter, 117 is a probe for applying a voltage to the gate electrode, and is connected to the pad region 123. Reference numeral 118 denotes a probe for grounding the semiconductor substrate 100, and reference numeral 118 denotes a monitor. Reference numeral 124 denotes an imaging device, for example, 100
With a double lens and a CCD having 1024 × 1024 pixels of 50 μm square, weak light emission generated when a current flows through the insulating film of the MOS capacitor can be detected with a spatial resolution of about 0.5 μm.

In this system for evaluating the life of an insulating film, first, the probe 117 is connected to the pad region 123, and then a voltage is applied from the voltage source 115 to all the gate electrodes 103 of the MOS capacitor via the high-resistance wiring region 121. At this time, the current (I) flowing through the gate insulating film is:
In the equivalent circuit shown in FIG.
It is determined by the FN characteristic of (C) and the resistance value R of the high-resistance wiring region 121. For example, if the voltage (V) applied to the pad region 123 is 9 V, the thickness of each MOS capacitor is 6 nm, the area is 2 μm ² , and the resistance value R is 10 kΩ, the current I is about 2 nA. At this time,
The voltage drop in the high resistance wiring area (10 kΩ) is 2 μV
Therefore, it can be considered that the voltage V applied to the pad region 110 is applied to the gate electrode. With the start of the voltage application, an emission image associated with the gate current flowing through the gate oxide film 102 is monitored using the imaging device 124. The obtained luminescence image is obtained by the luminescence image processing device 125.
At each time t, the light emission amount in a region corresponding to the position (x, y) of each gate insulating film of the semiconductor device (FIG. 6) is counted and converted into matrix data P (t, x, y). At this time, the distance between the MOS capacitors of the semiconductor device is 2 μm or more, and the light emission amount of each MOS capacitor can be sufficiently resolved even with a spatial resolution of about 0.5 μm of the imaging device 124. The obtained light emission amount data P (t,
x, y) are sent to the control system computer 126 to determine whether the insulating film has been destroyed.

When an FN current flows through the gate insulating film,
When a current flows through the broken insulating film, a light emission phenomenon is observed in any case. However, in general, the amount of light emitted after the breakdown of the insulating film is one digit or more larger than that before the breakdown. For example, in a semiconductor device including a single MOS capacitor and a high-resistance wiring region shown in FIG. 9A, a change in the amount of light emission when a constant voltage is continuously applied to the gate insulating film is shown in FIG. As shown in b), it fluctuates rapidly before and after the breakdown of the insulating film. Therefore, in the control system computer 126, the time tBD when P (t, x, y) sharply increases
By recording the MO at position (x, y).
The breakdown of the oxide film of the S capacitor and the breakdown time tBD can be derived.

In this embodiment, a large number of M
A reliability test of the OS capacitor can be performed.

In the present embodiment, the processing of the light emission image is performed by the processing of the light emission amount in each MOS capacitor. However, the total light emission amount from the entire semiconductor evaluation device shown in FIG. By evaluating the change in the number of emitted light, the cumulative number of breakdowns of the insulating film at each time can be obtained. That is, in the present embodiment, the value of the current flowing through the insulating film after dielectric breakdown is determined by the resistance value of the high-resistance wiring. For example, when a resistance value of 10 kΩ is used, 0.9 V is applied when 9 V is applied.
mA, and the variation in each MOS capacitor is negligible. Therefore, the total light emission amount to be counted is proportional to the total number of broken insulating films. Therefore, by dividing the total light emission amount at each time by the light emission amount after destruction per unit MOS capacitor, it is possible to derive the cumulative destruction number of the oxide film of the MOS capacitor.

In the present embodiment, the detection of the light emission image accompanying the breakdown of the insulating film is performed from the front side of the wafer.
For example, the same effect can be obtained when a semiconductor device is packaged and a light emission image is detected from the back surface. In particular, this method is effective when a thick metal layer exists on the gate insulating film and it is difficult to detect a light-emitting image from the surface due to the breakdown of the insulating film.

(Embodiment 3) FIG. 10 is a structural view of a MOS capacitor according to Embodiment 3 of the present invention, FIG. 3 is a schematic diagram of a gate insulating film reliability evaluation system, and FIG. 3 is a flowchart illustrating an insulating film reliability evaluation.

In FIG. 10, reference numerals indicate the following members. Reference numeral 102 denotes a gate insulating film (area S) formed on a p-type semiconductor substrate; 103, a gate electrode formed on the gate insulating film 102;
02, MOS capacitor 1 by gate electrode 103
30, 131, and 132 are formed respectively. MO
The gate electrodes of the S capacitors 130, 131, and 132 are connected to metal wires having pad regions 127, 128, and 129, respectively. The MOS capacitor 13
The metal antenna wiring 133,
134 is connected. Generally, when dry etching of metal antenna wiring, insulation film reliability is deteriorated.
The antenna ratio (= side wall area of metal antenna wiring / insulating film area) is used as the parameter. Here, M
Assuming that the antenna ratios of the OS capacitors 130, 131, and 132 are R1, R2, and R3, respectively, R1 <R2 <R3
Holds.

In FIG. 3, reference numeral 113 denotes a wafer stage,
114 is a temperature control system for adjusting the temperature of the wafer stage 113, 115 is a voltage source, 116 is an ammeter, 117 is a probe for applying a voltage to the gate electrode, and connected to the pad area 127 or 128, 129. ing. Reference numeral 118 denotes a probe for grounding the semiconductor substrate 100, and 119 denotes a control system for judging when the gate oxide film has been broken and stopping the voltage application.

First, using the evaluation system shown in FIG.
After connecting the probe 117 to the pad region 109, the MO
A constant voltage is applied to the gate electrode of S transistor 105 from voltage source 115. The electric field applied to the gate oxide film is
For example, it is about 11 to 13 MV / cm. At this time, the gate current flowing through the gate oxide film is monitored using the ammeter 116, and the time TBD during which the gate oxide film is broken is measured.

In step 200 of the flowchart for evaluating the reliability of the insulating film of the MOS transistor included in the circuit shown in FIG.
By analyzing the wiring layout, an antenna ratio is derived for each MOS transistor. Next, in step 201, the sampling antenna ratio is determined from the range of the antenna ratio obtained in step 200 according to the frequency. Here, R1, R2,
R3 is sampled at three points, and M
For each of the OS transistors, the antenna ratio is approximated to the sampled antenna ratio, and the total area S (R1), S (R2), and S (R3) of the gate insulating film of the MOS transistor at each sampling antenna ratio.
Get. In step 203, using the antenna ratio dependence evaluation TEG shown in FIG.
Cumulative fault distribution function F1 of the insulating film at 1, R2, R3
(T), F2 (t) and F3 (t) are derived (FIG. 1).
2). Next, the area value S of the insulating film with respect to each sampled antenna ratio obtained in step 201
Using (R1), S (R2) and S (R3), the cumulative fault distribution function for the antenna ratio is converted by the following equation (step 204).

[0035]

(Equation 3)

[0036]

(Equation 4)

[0037]

(Equation 5)

Further, in step 205, the cumulative fault distribution function G1 (t) obtained for each antenna ratio,
By calculating from G2 (t) and G3 (t) according to the following equation, a failure distribution characteristic H (t) of the insulating film with respect to a desired circuit pattern can be obtained.

[0039]

(Equation 6)

According to the present embodiment, it is possible to derive a highly accurate failure distribution characteristic for the insulating film of a desired circuit from the deterioration data of the reliability characteristic of the insulating film of the TEG pattern in the wiring dry etching step.

In this embodiment, sampling is performed at three points with respect to the antenna ratio. However, by increasing the number of sampling points, a more accurate circuit failure distribution characteristic can be obtained.

In the present embodiment, a method for evaluating the life of a semiconductor device in consideration of the amount of deterioration of the reliability of a gate insulating film during dry etching of a wiring pattern is shown.
The same evaluation was performed on the reliability of the gate insulating film at the time of dry etching of the IA hole, and the VIA was evaluated.
It is possible to evaluate the failure distribution characteristics of a circuit in consideration of the damage caused by hole dry etching.

[0043]

As described above, according to the present invention, by combining the reliability evaluation results using a plurality of types of TEG patterns, the evaluation with a small number of samples enables the highly accurate formation of the insulating film in the entire actual circuit. An evaluation method for deriving reliability characteristics and reliability evaluation tests for a large number of TEG patterns are performed at the same time, and destruction is detected efficiently by an emission microscope. An evaluation device can be realized.

[Brief description of the drawings]

FIG. 1 is a structural diagram of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a structural diagram of a semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a schematic diagram of an evaluation system according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an example of a cumulative failure probability distribution function;

FIG. 5 is a diagram showing a conversion result of a cumulative failure probability distribution function;

FIG. 6 is a plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an equivalent circuit according to a second embodiment of the present invention.

FIG. 8 is a schematic diagram of an evaluation system according to a second embodiment of the present invention.

FIG. 9 is a structural diagram of a semiconductor device according to a second embodiment of the present invention;

FIG. 10 is a plan view of a semiconductor device according to a third embodiment of the present invention.

FIG. 11 is a process diagram of an evaluation method according to a third embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of a cumulative failure probability distribution function.

FIG. 13 is a schematic view of an insulating film reliability evaluation method.

FIG. 14 is a schematic diagram showing current-voltage characteristics at the time of insulating film reliability evaluation.

FIG. 15 is a schematic diagram of a life estimation method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 p-type semiconductor substrate 101 isolation insulating film 102 gate insulating film 103 gate electrode 104 n-type semiconductor region 105 MOS transistor 106 contact 107 interlayer insulating film 108 metal wiring 109 pad region 110 metal wiring 111 MOS transistor group 112 pad region 113 wafer stage 114 Temperature adjustment mechanism 115 Voltage source 116 Current monitor 117 Probe 118 Probe 119 Control system 120 MOS capacitor 121 High resistance wiring area 122 Metal wiring 123 Pad area 124 Imaging device 125 Emission image processing device 126 Control system computer 127 Pad area 128 Pad area 129 Pad Area 130 Metal antenna wiring 131 Metal antenna wiring

Claims (7)

[Claims] A step of performing a constant voltage TDDB test on insulating films of semiconductor devices having different structures; and a step of performing an arbitrary structure given a cumulative failure probability distribution function obtained by the constant voltage TDDB test. Insulating film reliability of a semiconductor device, comprising the steps of: converting the structure according to the structure of the semiconductor device; and statistically integrating them to derive a cumulative failure probability distribution function of the insulating film in the semiconductor device having the arbitrary structure. Evaluation method. 2. A semiconductor device having a different structure includes different numbers of MOS transistors having a certain structure, and a voltage is applied to the gate electrodes of all the MOS transistors from outside the semiconductor device. The method for evaluating the reliability of an insulating film of a semiconductor device according to claim 1, wherein the method comprises: 3. A method of converting a cumulative failure probability distribution function, comprising:
3. The method according to claim 1, wherein the conversion is performed in accordance with a ratio of the number of transistors constituting the semiconductor device. 4. A plurality of Ms formed on the same semiconductor substrate.
Applying a voltage from the pad region to a semiconductor device connected to a single pad region enabling external voltage application to all gate electrodes of the OS capacitor via high-resistance wiring regions, respectively; A method for evaluating the reliability of an insulating film of a semiconductor device, comprising: a step of monitoring a light emission image from the MOS capacitor simultaneously with the application of the voltage; and a step of deriving the number of insulating films broken by processing the light emission image. 5. In a process of processing a light emission image, light emission amounts in regions corresponding to gate insulating films of a plurality of MOS capacitors formed on the same semiconductor substrate are counted, and light emission amounts in the respective regions are counted. 5. The method for evaluating reliability of an insulating film of a semiconductor device according to claim 4, wherein each breakdown is determined by individually analyzing the breakdown. 6. A process for processing a light emission image, wherein a light emission amount from a plurality of MOS capacitor groups formed on the same semiconductor substrate is counted, and a total number of destroyed MOS capacitors in the MOS capacitor group is counted. 6. The method for evaluating reliability of an insulating film of a semiconductor device according to claim 5, wherein the method is derived. 7. A step of deriving an antenna ratio for each MOS transistor constituting the circuit by analyzing a wiring layout of a circuit to be evaluated, a step of sampling the antenna ratio, and a step of sampling the antenna ratio. Deriving a cumulative fault distribution function of the insulating film at each antenna ratio using a MOS capacitor having a wiring pattern of the antenna ratio for the sampled antenna ratio, and an area of the insulating film for each sampled antenna ratio Converting the cumulative fault distribution function with respect to the antenna ratio using the values, and calculating the cumulative fault distribution function obtained for each antenna ratio to obtain a fault distribution characteristic of the insulating film with respect to a desired circuit pattern. And a method of evaluating the reliability of an insulating film of a semiconductor device.