JPH1027491A - Method for measuring writing threshold value of nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of threshold value measuring times by measuring a threshold of a transistor while exponentially increasing a cumulative value of a voltage application time between a gate/a drain at every threshold measurement. SOLUTION: A pulse with a fixed time width t0 and prescribed voltages 12V, 5.5V is used for a memory cell becoming the measurement object of the threshold Vt of the transistor as the voltage between the gate/drain, and the cumulative value of the number of pulses at every threshold Vt measurement is increased exponentially. Concretely, after the number of pulses '1' is added, first threshold measurement is performed (cumulative write-in time = T0 ), and further, after the number of pulses '1' is added, second threshold measurement is performed (cumulative write-in time = 2.t0 ). Further, after the number of pulse '2' is added, third threshold measurement is performed (cumulative write-in time = 4.t0 ), and successively, after the number of pulse '4' is added, fourth threshold measurement is performed (cumulative write-in time = 8.t0 ).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage technique for an electrically erasable and erasable nonvolatile semiconductor memory having a MOS structure, and more particularly to a method for measuring a write threshold value.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory (EEPROM)
In the writing operation, a voltage is simultaneously applied to the drain electrode and the control gate electrode to inject electrons into the floating gate. More specifically, as shown in FIG. 6, hot electrons generated near the drain by applying a control gate voltage VG higher than the drain voltage VD are injected into the floating gate electrode. At this time, the voltage application is given as a pulse signal having a fixed time width, and the writing operation is terminated when the voltage reaches a predetermined threshold voltage. When a large number of memory cells are arranged, this operation is performed for each bit.

[0003]

In a flash memory which is a rewritable non-volatile memory, it is important to keep the threshold voltage at the time of writing as small as possible. This is because the erasing operation is performed by the FN current between the source region and the floating gate electrode by applying the high voltage VS to the source and grounding the control gate as shown in FIG. The variation of the threshold voltage is directly reflected.

In particular, in a flash memory that repeats rewriting, the variation in threshold voltage after writing affects the variation in threshold voltage after erasing. As a result, the threshold voltage after erasing varies, and in an extreme case, a depletion state in which the threshold voltage becomes 0 V or less, that is, excessive erasing, may occur, and the circuit operation may be disabled.

In order to suppress the variation of the threshold voltage after the writing, it has been proposed to terminate the writing when a predetermined threshold voltage is reached. In this case, a pulse having a fixed time width is applied at the time of writing. If the threshold voltage is measured (determined) after each pulse application, the number of measurements increases. Further, there is a problem that the number of measurements of a bit having a low writing speed (a bit for obtaining a predetermined threshold value by applying a voltage for a long time) increases, and the time required for writing further increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of measuring a threshold value for writing data in a nonvolatile memory, which can reduce the number of times of measuring the threshold value.

[0007]

According to the first aspect of the present invention, the threshold value of the transistor is increased exponentially while increasing the cumulative value of the voltage application time between the gate and the drain every time the threshold value is measured. Is measured.

Therefore, as shown in FIG. 5, since the threshold value Vt for the application time (writing time) is exponential, it can be increased at a constant rate in this method. as a result,
When measuring the threshold value of a transistor while increasing the cumulative value of the voltage application time between the gate and the drain for each measurement of the threshold value as a linear function, for example, as shown in FIG. In this method, the number of measurements is reduced to four (the embodiment in the figure), but the number of measurements can be reduced.

As shown in FIG. 5, there are some bits having a high writing speed and some bits having a low writing speed. However, in this method, the threshold voltage can be increased by a constant value regardless of whether the writing speed is a high bit or a low bit. The number of measurements can be reduced for bits having a low writing speed.

As described above, the threshold value can be increased by a constant value irrespective of a bit having a high writing speed and a bit having a low writing speed, and the number of times can be further reduced.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of the flash memory, and FIG. 2 is a sectional view taken along line AA of FIG.

As shown in FIG. 2, P as a semiconductor substrate
In the single-crystal silicon substrate 1, a P-type silicon layer 1a
Is formed with a P-well layer 1b. An N ⁺ type source region (impurity diffusion region) 2 and an N ⁺ type drain region (impurity diffusion region) 3 for each cell are provided in the surface layer portion of the P well layer 1b.
Are formed. Further, in the P-well layer 1b, a band-shaped N ⁺ -type source common line (impurity diffusion region) 4 extends from the source region 2 as shown in FIG. 1, and the source common line 4 extends the source region 2 of each memory cell. Are combined.

As shown in FIG. 2, a floating gate electrode 6 made of polycrystalline silicon is arranged on the single crystal silicon substrate 1 via a thin silicon oxide film (tunnel oxide film) 5 as an insulating film. The floating gate electrode 6 has a rectangular shape and extends so as to pass between the source region 2 and the drain region 3. A strip-shaped control gate electrode 8 is arranged on the floating gate electrode 6 via a silicon oxide film (inter-gate insulating film) 7 as an insulating film. The control gate electrode 8 is made of polycrystalline silicon, and extends in parallel with the common source line 4 as shown in FIG.

Further, as shown in FIG.
A silicon oxide film 9 is disposed on the single crystal silicon substrate 1 including the periphery. A drain wire 11 made of aluminum is arranged on the silicon oxide film 9, and the drain wire 11 is electrically connected to the drain region 3 through a contact hole (opening) 10. In the present embodiment, a drain contact hole 10 common to two transistor cells is provided. Further, as shown in FIG. 1, a source wiring (not shown) is electrically connected to the source common line 4 through contact holes (openings) 12a, 12b, 13a, 13b provided in the silicon oxide film 9. . In the present embodiment, the source contact holes 12a,
12b, 13a and 13b are provided.

FIG. 3 shows a peripheral circuit. X decoder 1
5 and a Y decoder / sense amplifier / write circuit 16. X decoder 15 has word lines 1, 2, 3,.
, N and j are connected to the control gate electrode 8 of each cell. The Y decoder / sense amplifier / write circuit 16 is connected to the drain region 3 of each cell via bit lines 1, 2, 3,..., M and k. The Y decoder / sense amplifier / write circuit 16 has source lines 1, 2, 3,.
m and k are connected to the source region 2 of each cell.

Next, the operation of the flash memory configured as described above will be described. When a write operation is performed on the memory cell 100 (word; n, bit; m) in FIG. 3, a 12 volt pulse (voltage) is applied to the word line n by the X decoder 15 as shown in FIG. Apply Y-decoder
The sense amplifier / write circuit 16 applies a 5.5 volt pulse (voltage) to the bit line m and sets the source line m to the ground potential. The application of the pulse voltage between the gate and the drain is performed synchronously. By this voltage application, a control gate voltage VG higher than the drain voltage VD is applied, and hot electrons generated near the drain are injected into the floating gate electrode 6. As a result, the memory cell 100 (n, m) has the predetermined threshold value Vt.

At the time of writing, a pulse voltage is applied while measuring the threshold value to obtain a desired threshold value Vt. This writing threshold value measuring method will be described.

FIG. 5 shows the write time and the threshold voltage Vt.
The relationship is shown below. Threshold Vt even for the same write time
And the writing time is 0.000, for example.
At one second, there are fast cells (bits) with Vt = 6.4 volts and slow cells (bits) with Vt = 5.5 volts. Also, the writing time is 0.0001 seconds to 0.01
In seconds, the write time dependency (change rate of the threshold) of the increase in the threshold value of the memory is proportional to the power of time, regardless of whether the write time is fast or slow.

Therefore, the threshold value Vt of the transistor is measured while exponentially increasing the cumulative value of the voltage application time between the gate and the drain every time the threshold value is measured. This will be described with reference to FIG. 4. For a memory cell to be measured for Vt, a pulse having a fixed time width to, that is, a fixed time to and a predetermined voltage (1
2 volts, 5.5 volts)
The cumulative value of the number of pulses for each measurement of the threshold is increased exponentially. Specifically, the first threshold value measurement is performed after the pulse number “1” is given (cumulative writing time = to), and the second threshold value measurement is performed after the pulse number “1” is given (cumulative writing time). (Write time = 2 · to), and a third threshold measurement is performed after the pulse number “2” is given (cumulative write time = 4 · to), and after the pulse number “4” is given, A fourth threshold measurement is performed (cumulative writing time = 8 ·
to).

Therefore, although there are some bits having a high writing speed and some bits having a low writing speed, as shown in FIG. 5, the threshold Vt with respect to the application time (writing time) is exponential. The value can be increased by a constant value regardless of a bit having a high speed and a bit having a low speed.

When the threshold value of the transistor is measured while increasing the cumulative value of the voltage application time between the gate and the drain for each measurement of the threshold value Vt as a linear function, as shown in FIG. 4 as a comparative example. In addition, the number of measurements is reduced from eight to four in the present embodiment, and the number of measurements can be reduced. That is, the number of measurements can be reduced as compared with the case where the threshold value is measured for each shot and the threshold value measurement is performed while increasing the cumulative writing time in a linear function. In this manner, the number of times of measuring the threshold voltage in the memory cell can be reduced, and the writing time of the entire memory area can be reduced. Therefore, the threshold voltages after writing can be made uniform and writing can be performed efficiently. Therefore, extremely high-speed writing is possible for writing a product having a large number of bits.

As shown in FIG. 1, in the present embodiment, the memory is provided in the source contact hole 12 every eight bits.
a, 12b, 13a and 13b are formed, and the writing characteristics of the transistor are determined by the capacitance ratio between the floating gate and the control gate, which is called a coupling ratio, but are also affected by other parasitic capacitances. Therefore, the drain D in FIG.
1, D1 ', D1 ", drains D2, D2', D2",
.. Are located at an equivalent distance from the source contact and are equivalent cells, and when writing is performed, bits equivalent to the source contact are selected at the same time. Are written at the same time.
Writing characteristics are uniform, and threshold voltages after writing can be uniformed. Further, since several bits can be simultaneously written at a time, more efficient writing can be performed than writing one bit at a time. Thus, the source contact hole 12
For bits a, 12b, 13a, and 13b, bits at equivalent positions are simultaneously selected at the time of writing, and efficient and uniform Vt
Is realized.

As described above, this embodiment has the following features. (A) Since the threshold value of the transistor is measured while the cumulative value of the voltage application time between the gate and the drain for each measurement of the threshold value is increased exponentially, the threshold voltage can be increased by a constant value. Thus, the number of measurements can be reduced as compared with a method of increasing the cumulative voltage application time in a linear function, and the number of measurements can be further reduced for a bit having a low writing speed.

In the above embodiment, a pulse voltage synchronized with the gate electrode and the drain electrode is applied. However, the present invention is not limited to this. The pulse voltage of this example may be applied only to the drain electrode. Alternatively, the pulse voltage of this example may be applied to the control gate electrode while a predetermined voltage is applied to the drain electrode.

[Brief description of the drawings]

FIG. 1 is a plan view of a flash memory according to an embodiment;

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a circuit diagram showing an electrical configuration of a peripheral circuit.

FIG. 4 is a waveform chart for explaining an applied pulse and the like.

FIG. 5 is a measurement diagram showing a relationship between a writing time and a threshold voltage.

FIG. 6 is a cross-sectional view of a memory for explaining a writing operation.

FIG. 7 is a cross-sectional view of a memory for explaining an erasing operation.

[Explanation of symbols]

1 ... P-type single crystal silicon substrate as semiconductor substrate, 2 ...
Source region, 3 ... drain region, 4 ... source common line, 5
... Silicon oxide film as insulating film, 6 ... Floating gate electrode, 7 ... Silicon oxide film as insulating film, 8 ... Control gate electrode

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tsutomu Kawaguchi 1-1-1, Showa-cho, Kariya-shi, Aichi, Japan

Claims (2)

[Claims] A source region and a drain region for each cell are formed at a distance from each other in a surface layer portion of a semiconductor substrate; a floating gate electrode is disposed on the semiconductor substrate between the two regions via an insulating film; A method for measuring a writing threshold value in a nonvolatile memory in which a control gate electrode is extended over a gate electrode via an insulating film, wherein a cumulative value of a voltage application time between a gate and a drain for each measurement of the threshold value is calculated. , A writing threshold value measuring method for a nonvolatile memory, wherein the threshold value of a transistor is measured while increasing exponentially. 2. The nonvolatile memory according to claim 1, wherein a pulse having a fixed time width is used as a voltage between the gate and the drain, and a cumulative value of the number of pulses for each measurement of the threshold value is increased exponentially. Writing threshold measurement method.