JP2010530596A - Intelligent control of write pulse duration - Google Patents

Abstract

  In order to write to a plurality of nonvolatile memory elements, a plurality of write pulses are applied to control gates (or other terminals) of the nonvolatile memory elements. The write pulse has a constant pulse width and increases in magnitude until the maximum voltage is reached. At that point, the magnitude of the write pulse is stopped increasing and a write pulse is applied between the verification processes to provide different durations of the write pulse length. In one embodiment, for example, after the pulse reaches a maximum value, the pulse width is increased. In other embodiments, after the pulse reaches the maximum value, multiple write pulses are applied between verification processes.

Description

  The present invention relates to a technology for a nonvolatile memory device.

  Semiconductor memories are becoming more commonly used in various electronic devices. For example, non-volatile semiconductor memories are used in mobile phones, digital cameras, personal digital assistants, mobile computers, non-mobile computers, and other devices. Electrically erasable and rewritable read only memory (EEPROM) and flash memory are the most popular nonvolatile semiconductor memories.

  The EEPROM and the flash memory employ a floating gate that is disposed on the channel region in the semiconductor substrate and insulated from the channel region. The floating gate and the channel region are disposed between the source region and the drain region. A control gate that is insulated from the floating gate is provided on the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate to turn on the transistor to allow conduction between its source and drain is controlled by the charge level on the floating gate. Accordingly, writing / erasing can be performed on a memory cell (the memory cell may include one or more transistors) by changing the threshold voltage by changing the amount of charge held in the floating gate. it can.

  Each memory cell can store data (analog or digital). When storing 1-bit digital data (referred to as a binary memory cell), the possible threshold voltage range of the memory cell is divided into two ranges, each range being a logical data “1” and “0”. Assigned. In an example of a NAND flash memory, after the memory cell is erased, the threshold voltage becomes a negative value, which is defined as logic “1”. The threshold voltage after writing is a positive value, which is defined as logic “0”. If the threshold voltage is negative and a read is attempted with 0 volts applied to the control gate, the memory cell is turned on, indicating that a logic 1 is stored. If the threshold voltage is positive and a read attempt is made with 0 volts applied to the control gate, the memory cell will not turn on, indicating that a logic 0 is stored.

  A single memory cell can store multiple levels of information (referred to as a multi-state memory cell). When storing multiple levels of data, the range of possible thresholds is divided into the number of levels of data. For example, when storing four levels of information, there are four threshold voltage ranges, which are assigned to data values “11”, “10”, “01”, and “00”, respectively. In an example of a NAND type memory, the threshold voltage after the erase operation is a negative value and is defined as logic “11”. Positive threshold voltage groups are used for data states of “10”, “01”, and “00”. When eight levels of information (or status) are stored (ie, 3-bit data), the data values “000”, “001”, “010”, “011”, “100”, “101”, “101”, “ There are eight threshold voltage ranges assigned to “110” and “111”. The specific relationship between the data written to the memory cell and the threshold voltage level of the cell is determined by the data encoding scheme employed for the cell. For example, US Pat. No. 6,222,762 and US Patent Application Publication No. 2004/0255090, both of which are incorporated herein by reference in their entirety, describe various data for multi-state flash memory cells. The encoding method is described. In one embodiment, data values are assigned to threshold voltage ranges using Gray code assignment so that only one bit is affected if the threshold voltage of the floating gate is accidentally shifted to its neighboring physical state. . In some embodiments, the data encoding technique may be changed for different wordlines. Data encoding techniques may be changed depending on time. Also, random wordline data bits may be inverted to reduce data pattern sensitivity and to uniform memory cell wear. Various encoding techniques may also be used.

  When writing to a flash memory device such as an EEPROM or NAND flash memory device, the bit line is typically grounded and a write voltage is applied to the control gate. Electrons from the channel are injected into the floating gate. When electrons are accumulated in the floating gate, the floating gate is charged to a negative value, the threshold voltage of the memory cell is increased, and the memory cell is written. More information on writing can be found in US Pat. No. 6,859,397 entitled “Source Side Self Boosting Technique for Non-Volatile Memory” and US Patent Application Publication No. 2005/0024939 entitled “Detecting Over Programmed Memory”. Is disclosed. The contents of both of these documents are hereby incorporated by reference in their entirety.

  Usually, the write voltage applied to the control gate in the write process is applied as a continuous pulse. In many implementations, the magnitude of each successive pulse is increased by a predetermined step size.

  Multi-state memory cells have multiple effective threshold voltage ranges. Therefore, a certain memory cell may need to be written with a higher threshold voltage than a binary memory cell. In order to write to a memory cell with a higher threshold voltage, a larger write pulse is required. Furthermore, as the technology scale becomes finer, it may become difficult to maintain the same coupling ratio. Therefore, a higher voltage write pulse is required to obtain the same write effect. However, the voltage value of the write pulse is practically limited by many factors such as the design of the charge pump mounted on the memory chip, the junction, and the dielectric breakdown of the insulating film.

  Therefore, there is a need to increase the voltage of the write pulse, while there is an upper limit value of the maximum voltage that can be obtained.

  The technique described here relates to an intelligent method for controlling the duration of a write pulse applied to a memory cell. For example, in situations where there are still memory cells where the write signal has reached its maximum voltage but the write has not been completed, an intelligent scheme that controls the duration of the write pulse received by the memory cell is effective. The write operation can be continued. One example of an intelligent scheme for controlling the duration of a write pulse in a memory cell is to use a wider write pulse. In another example, a plurality of consecutive write pulses are used between verification processes. Other intelligent schemes for controlling the duration of the memory cell write pulse may also be used. In addition, an intelligent scheme for controlling the duration of the write pulse can also be used outside the situation described above.

In one embodiment, applying a write signal to the non-volatile storage element is included. The step of applying the write signal to the nonvolatile memory element includes the step of applying the write pulse to the nonvolatile memory element with a constant pulse width before the one or more pulses reach the maximum value, and the one or more pulses After reaching the maximum value, one or more write pulses providing different durations of the write signal length are applied to the non-volatile storage element during the verification process.

  One embodiment applies a write signal as a plurality of pulses to a plurality of non-volatile storage elements, and performs one or more verification processes to determine whether the plurality of non-volatile storage elements are properly written Step. The step of applying the write signal as a plurality of pulses includes the step of applying a pulse with a constant duration while increasing the magnitude before the one or more pulses reach the maximum value. The step of applying the write signal as a plurality of pulses also includes changing the duration of the write signal to a different length during the verification process after one or more pulses reach the maximum value.

  One embodiment includes applying pulses to the non-volatile memory element with a constant pulse width while increasing in magnitude until one or more pulses reach a maximum value. The series of processes includes a step of applying a write pulse to the nonvolatile memory element while increasing the pulse width after one or more pulses reach the maximum value.

  One embodiment includes applying pulses to the non-volatile memory element with a constant pulse width while increasing the magnitude until one or more pulses reach a maximum value. The series of processes also includes a step of applying one or more pulse groups composed of different numbers of write pulses to the nonvolatile memory element after one or more pulses reach the maximum value. Each group is applied between verification processes.

  An example of an implementation includes a plurality of non-volatile storage elements and one or more management circuits that communicate with the non-volatile storage elements. One or more management circuits execute the processing described above.

It is a top view of a NAND string. It is an equivalent circuit diagram of a NAND string. 1 is a block diagram of a nonvolatile memory system. FIG. 3 is a block diagram illustrating one embodiment of a memory array. It is a block diagram which shows one Example of a sense block. It is a figure explaining an example of the set of a threshold voltage division, and the write-in process of a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a figure explaining the write-in process of various threshold voltage classification and a non-volatile memory. It is a table explaining an example of the writing order of a non-volatile memory. It is a flowchart explaining an example of the write-in process of a non-volatile memory. It is a flowchart explaining an example of the write-in process of a non-volatile element. It is a flowchart explaining an example of the process which increases the continuation time of a write voltage. It is a flowchart explaining an example of the process which increases the continuation time of a write voltage. It is a flowchart explaining an example of the process which increases the continuation time of a write voltage. It is a figure explaining the example of a waveform. It is a figure explaining the example of a waveform. It is a figure which shows the table which gives an example of a write signal. It is a figure explaining the example of a waveform. It is a figure explaining the example of a waveform.

  One example of a flash memory system uses a NAND structure and includes a series connection of a plurality of transistors between two select gates. The transistors and select gates connected in series are called NAND strings. FIG. 1 is a plan view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string shown in FIGS. 1 and 2 includes four transistors 100 connected in series sandwiched between a first (or drain side) select gate 120 and a second (or source side) select gate 122. , 102, 104 and 106. Select gate 120 connects the NAND string to the bit line via bit contact 126. Select gate 122 connects the NAND string to source line 128. The selection gate 120 is controlled by applying an appropriate voltage to the selection line SGD. The selection gate 122 is controlled by applying an appropriate voltage to the selection line SGS. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. For example, the transistor 100 includes a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. Yes.

  1 and 2 show four memory cells in a NAND string, it should be noted that the use of four transistors is presented only as an example. A NAND string may have fewer than four or more than four memory cells. For example, some NAND strings may have 8, 16, 32, 64, 128, etc. memory cells. The description herein is not limited to NAND strings having any particular number of memory cells.

  The general architecture of a flash memory system using a NAND structure includes several NAND strings. Each NAND string is connected to a source line by a source select gate controlled by a select line SGS, and is connected to an associated bit line by a drain select gate controlled by a select line SGD. Each bit line and each NAND string connected to the bit line via a bit line contact constitutes a column of the memory cell array. The bit line is shared by a plurality of NAND strings. Typically, the bit line passes over the NAND string in a direction orthogonal to the word line and is connected to one or more sense amplifiers.

  Examples of NAND type flash memories and their associated operation are described in the following US patents / patent applications, which are incorporated herein by reference in their entirety. US Pat. No. 5,570,315, US Pat. No. 5,774,397, US Pat. No. 6,046,935, US Pat. No. 6,456,528, and US Publication No. US 2003/0002348 . The description herein is applicable to other types of flash memory with NAND as well as other types of non-volatile storage elements.

  In addition to NAND flash memory, other types of non-volatile storage devices can also be used. For example, the present invention is basically applicable to a so-called TANOS structure (structure composed of a stack of TaN—Al 2 O 3 —SiN—SiO 2) which is basically a memory cell that traps charges in a nitride layer (instead of a floating gate). Applicable. Another memory cell is in the article by Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device", IEEE ELECTRON DEVICE Letters, EDL-8, No. 3, March 1987, pages 93-95. Explained. A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between the surface of the semiconductive substrate and the conductive control gate over the memory cell channel. The cell is written by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in the restricted region. This accumulated charge then alters the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application”, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pages 497 to 501 A similar cell is described in a split gate configuration in which a polysilicon gate doped to form a portion extends into a portion of a memory cell channel. The two articles are incorporated herein by reference in their entirety. "Nonvolatile Semiconductor Memory Technology" edited by William D. Brown and Joe E. Brewer, incorporated herein by reference, also applies to dielectric charge trapping devices, paragraph 1.2 of IEEE Publication 1998. A writing technique is described. Other types of memory elements can also be used.

  FIG. 3 shows a storage device 210 having a read / write circuit that reads and writes in parallel to a page of a plurality of memory cells (eg, a NAND multi-state flash memory). Storage device 210 may comprise one or more memory dies or chips 212. The memory die 212 includes a (two-dimensional or three-dimensional) array 200 of memory cells, a control circuit 220, and read / write circuits 230A and 230B. In one embodiment, access to the memory array 200 by various peripheral circuits is implemented symmetrically on both sides of the array, thereby reducing the density of access lines and circuits on each side in half. The read / write circuits 230 </ b> A and 230 </ b> B have a plurality of sense blocks 300, and one sense page 300 can read or write one page of memory cells in parallel. Memory array 200 is addressed by a word line through row decoders 240A and 240B and a bit line through column decoders 242A and 242B. In an exemplary embodiment, controller 244 is included in the same memory device 210 (eg, a removable storage card or package), such as one or more memory dies 212. Instructions and data are transferred between the host and controller 244 via line 232, and between the controller and one or more memory dies 212 via line 234.

  The control circuit 220 performs a memory operation on the memory array 200 in cooperation with the read / write circuits 230A and 230B. The control circuit 220 includes a state machine 222, an on-chip address decoder 224, and a power control module 226. The state machine 222 provides chip level control of memory operations. On-chip address decoder 224 provides an address interface between addresses used by the host or memory controller and hardware addresses used by decoders 240A, 240B, 242A, and 242B. The power control module 226 controls the power and voltage supplied to the word lines and bit lines during the memory operation. In one embodiment, the power control module 226 has one or more charge pumps that can produce a voltage greater than the supply power.

  In one embodiment, the control circuit 220, power control circuit 226, decoder circuit 224, state machine circuit 222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A, decoder circuit 240B, read / write circuit 230A, read / write circuit 230B , And / or one or several combinations of the controller 244 may be referred to as one management circuit or a plurality of management circuit groups. One or more management circuits perform the processing described herein.

  FIG. 4 shows an exemplary structure of the memory cell array 200. In one embodiment, the array of memory cells is divided into a number of blocks (eg, blocks 0-1023 and other quantities). A block is a unit of erase, as is common in flash EEPROM systems. That is, each block includes the minimum number of memory cells that are erased together.

  One block comprises a set of NAND strings accessed via bit lines (eg, bit lines BL0-BL69623) and word lines (WL0, WL1, WL2, WL3). FIG. 4 shows four memory cells that are connected in series to form a NAND string. Each NAND string includes four cells, but may have fewer than four or more than four memory cells (eg, depending on the NAND string, 16, 32, (You may have 64, 128 or other numbers of memory cells.) One end of each NAND string is connected to the corresponding bit line via a drain select gate (connected to a select line SGD) The other end is connected to the source line via a source selection gate (connected to the selection line SGS).

  In another embodiment, the bit lines are divided into even bit lines and odd bit lines. In the odd / even bit line architecture, a group of memory cells along the common word line and connected to the odd bit line are written simultaneously. On the other hand, the memory cell group along the common word line and connected to the even bit line is written at a timing different from the writing of the memory cell group connected to the odd bit line.

  Each block is usually divided into a plurality of pages. In one embodiment, a page is a unit of writing. Usually, one or more pages of data are stored in one column of memory cells. For example, one or more pages of data may be stored in memory cells connected to a common word line. A page can store one or more sectors. One sector includes user data and overhead data (also called system data). The overhead data usually includes an error correction code (ECC) calculated from user data of the sector and header information. Some of the controllers (or other components) calculate the ECC when data is being written to the array and also check the ECC when data is being read from the array. Instead, ECC and / or other overhead data may be stored on a different page than the user data to which they relate, or stored in a different block. The sector of user data is usually 512 bytes corresponding to the sector size in the magnetic disk drive. For example, many pages from 8 pages to 32, 64, 128, or more pages form one block. Different sized blocks and arrangements can also be employed.

  FIG. 5 is a block diagram of individual sense blocks 300 divided into a core portion and a common portion 490 called a sense module 480. In one embodiment, separate sense modules 480 may be prepared for each bit line, and one common unit 490 may be prepared for a set of multiple sense modules 480. As an example, one sense block has one common part 490 and eight sense modules 480. Each sense module in the group communicates with a common unit that cooperates via a data bus 472. For further details, see US Patent Application Publication No. 2006/0140007, which is hereby incorporated by reference in its entirety.

  The sense module 480 includes a sense circuit 470 that determines whether the conduction current in the connected bit line is higher or lower than a predetermined threshold level. In some embodiments, the sense module 480 includes a circuit commonly referred to as a sense amplifier. The sense module 480 further includes a bit line latch 482 that is used to set a voltage state on the connected bit line. For example, when a predetermined state is latched in the bit line latch 482, the connected bit line is pulled up (pulled) to a state (for example, Vdd) designating write inhibition.

  The common unit 490 includes a processor 492, a set of data latches 494, and an I / O interface 496 that connects between the set of data latches 494 and the data bus 420. The processor 492 performs the calculation. For example, one of its functions is to identify data stored in sensed memory cells and store the identified data in a set of data latches. A set of data latches 494 is used to store data bits specified by the processor 492 in a read operation. The set of data latches 494 is also used to store data bits taken from the data bus 420 in a write operation. The fetched data bit group represents write data (write data) to be written in the memory. The I / O interface 496 provides an interface between the data latch 494 and the data bus 420.

During read or sense, system operation is under the control of state machine 222, which controls the supply of various control gate voltages to the addressed cell (using power control module 226). .
As each step through the various predetermined control gate voltage steps corresponding to the various memory states provided in the memory, the sense module 480 transitions to one of these voltages and from the sense module 480 to the processor 492 via the bus 472. Output is provided. At that point, the processor 492 identifies the resulting memory state with information about the sense module transition event and the control gate voltage applied via the input line 493 from the state machine. The processor then calculates the binary encoding for the memory state and stores the resulting group of data bits in the data latch 494. In another embodiment of the core portion, the bit line latch 482 has the dual role of a latch that latches the output of the sense module 480 and a bit line latch as described above.

  Of course, some implementations may have multiple processors 492. In one embodiment, each processor 492 has an output line (not shown in FIG. 5), and each output line is wired-ORed together. In some embodiments, the output line is inverted prior to being connected to the wired OR line. This configuration allows a state machine that receives the wired-OR result to determine when all the bits to be written have reached the desired level, thus enabling quick determination in the write verification process that determines when the write process is complete To do. For example, when each bit reaches its desired level, a logic “0” for that bit is sent to the wired OR line (or data “1” is inverted). When all bits output data “0” (or when data “1” is inverted), the state machine knows the completion of the write process. In embodiments where each processor communicates with 8 sense modules, the state machine may need to read the wired OR line 8 times (in some embodiments) or the result of cooperating bit lines. May be added to the processor 492 so that the state machine reads the wired OR line only once.

  The data latch stack 494 has a stack of data latches corresponding to the sense module. In one embodiment, there are three (or four or some other number) data latches per sense module 480. In one embodiment, each latch is 1 bit.

  During the write or verify process, the data to be written is stored in a set of data latches 494 from the data bus 420. During the verification process, the processor 492 monitors the verification memory state for the desired memory state. When the two match, the processor 492 sets the bit line latch 482 to pull up (pull) the bit line to a state in which write inhibition is designated. As a result, even if the write pulse affects the control gate, the cell connected to the bit line can be prevented from being further written. In other embodiments, the processor first loads the bit line latch 482 and the sense circuit sets the inhibit value to it during the verification process.

  In some implementations (although not required) the data latch is implemented as a shift register that converts internally stored parallel data to serial data for the data bus 420 and vice versa. In a preferred embodiment, all data latches corresponding to the read / write blocks of m memory cells are linked together to form a block shift register so that a block of data can be input or output by serial transfer. To do. In particular, each group of data latches in the read / write module constitutes a bank of read / write modules so that data is transferred in sequence to or from the data bus so that the group of data latches is as if the entire read / write block It may be as if it is a part of the shift register.

  More information on read operations and sense amplifiers can be found in the following document: (1) US Patent Application Publication No. 2004/0057287, “Non-Volatile Memory And Method With Reduced Source Line Bias Errors”, published on March 25, 2004, (2) US Patent Application Publication No. 2004/0109357, “Non- Volatile Memory And Method with Improved Sensing ”, published on June 10, 2004, (3) US Patent Application Publication No. 20050169082, (4) US Patent Application Publication No. 2006/0221692,“ Compensating for Coupling During Read Operations of Non-Volatile ”. Memory ", inventor Jean Chen, filed April 5, 2005, and (5) US Patent Application No. 11 / 321,953," Reference Sense Amplifier For Non-Volatile Memory ", Inventors Siu Lung Chan and Raul. -Adrian Cernea, filed December 28, 2005. All of these five patent documents are hereby incorporated by reference in their entirety.

  At the end of a successful write process (including verification), the threshold voltage of the memory cell can be changed within one or more threshold voltage segments of the written memory cell, or of the erased memory cell, as required. It falls within the threshold voltage category. FIG. 6 shows an example of threshold voltage division (or data state) for the memory cell array when each memory cell stores 3-bit data. On the other hand, in other embodiments, data of more than 3 bits per memory cell or less than 3 bits may be stored (for example, data of 4 bits or more per memory cell). .

  In the example of FIG. 6, each memory cell holds 3-bit data. Thus, there are eight valid data states S0-S7. In one embodiment, data state S0 is less than 0 volts and data states S1-S7 are greater than 0 volts. In other embodiments, all eight data states are higher than 0 volts, or other arrangements can be performed. In one embodiment, the threshold voltage segment for S0 is wider than the segment for S1-S7.

  Each data state corresponds to a unique value of 3-bit data stored in the memory cell. In one embodiment, S0 = 111, S1 = 110, S2 = 101, S3 = 100, S4 = 011, S5 = 010, S6 = 001, S7 = 000. Other mappings of data states S0-S7 can also be used. In one embodiment, all bits of data stored in one memory cell are stored in the same logical page. In other embodiments, each bit of data stored in one memory cell corresponds to a different page. Accordingly, one memory cell storing 3-bit data includes data of the first page, the second page, and the third page. In some embodiments, all memory cells connected to the same word line are assumed to store the same three pages of data. In some embodiments, memory cells connected to one word line are classified into different sets of pages (eg, even and odd bit lines).

In some prior art devices, the memory cell is erased to state S0. The memory cell may be written from state S0 to any of states S1-S7. In one embodiment, known as full sequence programming,
A method of directly writing to any of the states S1-S7 written from the erased state S0 can be performed. For example, the memory cell group to be written may be erased first so that the majority of the memory cells in the memory cell group are in the erased state S0. While one memory cell is being written from state S0 to state S1, another memory cell is from state S0 to state S2, from state S0 to state S3, from state S0 to state S4, from state S0 to state S5, and state S0. From state S6 to state S6 and state S0 to state S7. Full sequence programming is illustrated using the seven curved arrows in FIG.

  FIGS. 7A-7I show that for any particular memory cell, after writing to the adjacent memory cell of the previous page, writing to the particular memory cell associated with that particular page causes the floating gate to 10 shows another processing method of writing in the nonvolatile memory element that reduces the coupling phenomenon of FIG. The process of FIGS. 7A-I is three write processing steps. Prior to the first step, the memory cell can be erased to be in the erase threshold section of state S0.

  In the processing of FIGS. 7A-7I, it is assumed that each memory cell stores 3 bits of data and each bit belongs to a different page. The first bit of data (the leftmost bit) is associated with the first page. The middle bit is associated with the second page. The rightmost bit is associated with the third page. The correlation between data and data status is as follows: S0 = 111, S1 = 110, S2 = 101, S3 = 100, S4 = 011, S5 = 010, S6 = 001, S7 = 000. However, in other embodiments, other data coding sequences can be used.

  When writing to the first page (as shown in FIG. 7A), if the bit is set to data “1”, the memory cell remains in the state S0 (threshold voltage section 502). When the bit is set to data “0”, the memory cell is written and the state S4 is set (threshold voltage section 504). After adjacent memory cells are written, the state S4 may become wide as shown in FIG. 7B due to capacitive coupling between adjacent floating gates. Although the state S0 may also be wide, there is a sufficient margin between S0 and S1, and the influence can be ignored. Details on the coupling phenomenon between floating gates are disclosed in US Pat. No. 5,867,429 and US Pat. No. 6,657,891, both of which are incorporated herein by reference in their entirety. It is.

  When writing the second page (see FIG. 7C), if the memory cell is in the state S0 and the bit of the second page is set to data “1”, the memory cell maintains the state S0. In some embodiments, the second page write process may narrow the threshold voltage segment 501 to a new S0. If the memory cell is in state S0 and the data to be written to the second page is “0”, the memory cell is moved to state S0 (threshold voltage section 506). State S2 has a verification point (lowest voltage) of C *. When the memory cell is in the state S4 and the data written to the memory cell is “1”, the memory cell is maintained in the state S4. However, as shown in FIG. 7C, state S4 is narrowed by moving the memory cell from threshold voltage section 504 to threshold voltage section 508 for state S4. The threshold voltage section 508 has a verification point of E * (as compared to E ** of the threshold voltage section 504). If the memory cell is in state S4 and the data to be written to the second page is “0”, the threshold voltage of the memory cell is moved to state S6 (threshold voltage section 510) having a verification point of G *.

  After adjacent memory cells are written, states S2, S4, S6 are widened by coupling between adjacent floating gates, as shown in threshold voltage sections 506, 208, 510 of FIG. 7D. Sometimes state S0 also becomes wider.

  7E, 7F, 7G and 7H show the writing of the third page. Although one figure may be used to represent writing, the process is shown in four figures for clarity. After the second page is written, each memory cell is in one of states S0, S2, S4, S6. FIG. 7E shows the memory cell in state S0 being written to the third page. FIG. 7F shows the memory cell in state S2 being written to the third page. FIG. 7G shows the memory cell in state S4 where writing to the third page is performed. FIG. 7H shows the memory cell in state S6 where the third page is written. FIG. 7I shows the threshold voltage division after the processing of FIGS. 7E, 7F, 7G, and 7H is performed (simultaneously or continuously) on the memory cell group.

  When the memory cell is in the state S0 and the third page data is “1”, the memory cell maintains the state S0. When the data on the third page is “0”, the threshold voltage of the memory cell is raised to a state S1 having a B verification point (see FIG. 7E).

  When the memory cell is in the state S2 and the data written to the third page is “1”, the memory cell is maintained in the state S2 (see FIG. 7F). However, for some writes, the threshold section 506 can be narrowed to a new state S2 with a C volt verification point. If the data written to the third page is "0", the memory cell is written to state S3 having a D volt verification point.

  When the memory cell is in the state S4 and the data written to the third page is “1”, the memory cell is maintained in the state S4 (see FIG. 7G). However, for some writes, the threshold section 508 can be narrowed to a new state S4 with E verification points. If the memory cell is in state S4 and the data written to the third page is “0”, the threshold voltage of the memory cell is raised to state S5 having an F verification point.

  When the memory cell is in the state S6 and the data written to the third page is “1”, the memory cell is maintained in the state S6 (see FIG. 7H). However, for some writes, the threshold section 510 can be narrowed to a new state S6 with G verification points. When the data of the third page is “0”, the data is written to the state S7 having the verification point where the threshold voltage of the memory cell is H. When the writing of the third page is completed, the memory cell is in any one of the eight states shown in FIG. 7I.

  FIG. 8 is a diagram showing an example of the order of writing to a page or pages of a set or a plurality of memory cells. This table represents the write order for the four word lines (WL0, WL1, WL2, and WL3) in FIG. However, this table is also applicable to more or fewer word lines. A first page of memory cells connected to WL0 is written, followed by a first page of memory cells connected to WL1, followed by a second page of memory cells connected to WL0, followed by The first page of the memory cell connected to WL2 is written, the second page of the memory cell connected to WL1 is written, and so on.

  FIG. 9 is a flowchart for explaining the write processing of the memory cell connected to the selected word line. In one implementation of the process of FIG. 9, the memory cells are pre-written to maintain uniform degradation of the memory cells (step 550). In one embodiment, the memory cells are pre-written to state 7, random patterns, and other patterns. Some implementations do not require pre-writing.

  In step 552, the memory cells are erased (in blocks or other units) prior to writing. In one embodiment, the memory is maintained by grounding the word line of the selected block while the source and bit lines are floating and raising the p-well to an erase voltage (eg, 20 volts) for a sufficient amount of time. The cell is erased. Due to capacitive coupling, unselected word lines, bit lines, selected lines, and sources also rise to a voltage that is a significant fraction of the erase voltage. Therefore, a strong electric field is applied to the tunnel oxide layer of the selected memory cell, and electrons of the floating gate are emitted to the substrate side mainly by the Fowler-Nordheim tunnel effect, and the data of the selected memory cell is erased. . As electrons move from the floating gate to the p-well region, the threshold voltage of the selected cell decreases. Erasing can be performed on the entire memory array, separate blocks, or other units of cells. In one embodiment, after the memory cells are erased, all erased memory cells are in state S0 (see FIG. 6).

  In step 554, soft writing is performed to narrow the erase threshold voltage segment of the erased memory cell. Some memory cells may be in an erased state that is lower than necessary as a result of the erase process. By soft writing, the threshold voltage of the erased memory cell can be moved closer to the erase verification level. For example, as shown in FIG. 6, step 554 may include narrowing the threshold voltage segment associated with state S0. In step 556, the memory cells of the block are written as described herein. The process of FIG. 9 can be executed by an instruction of a state machine using the various circuits described above. In other embodiments, it may be executed by an instruction from a controller using the various circuits described above. After execution of the process of FIG. 9, the memory cells in the block can be read.

FIG. 10 is a flowchart showing a process for executing writing to the memory cells connected to the common word line. The process of FIG. 10 may be performed one or more times in step 556 of FIG. For example, the process of FIG. 10 can be used to perform the full sequence programming of FIG. 6, in which case the process of FIG. 10 can be performed once for each word line. In one embodiment, the writing process is performed sequentially starting from the word line located closest to the source line and moving toward the bit line side. The process of FIG. 10 can also be used to write to a page of wordline data for the write process of FIGS. 7A-I. In this case, the processing of FIG. 10 can be performed three times for each word line.
Other variations can also be used.

  Usually, the write voltage applied to the control gate in the write process is applied as a continuous pulse. There are a plurality of verification pulses for enabling the verification process between the write pulses. In many implementations, the magnitude of each successive pulse is increased by a predetermined step size. In step 608, the write voltage (Vpgm) is initialized to an initial value (eg, other suitable value such as a voltage up to 12 volts) and the write counter PC maintained by the state machine 222 is initialized to 1. Is done. In step 608, a write pulse of the write signal Vpgm is applied to the selected word line (word line selected for writing). The unselected word lines receive one or more boosted voltages (for example, voltages up to 8 volts) by executing a conventionally known boosting method. When a memory cell is written, the corresponding bit line is grounded. On the other hand, when the memory cell maintains the current data state, the corresponding bit line is connected to VDD in order to inhibit writing. Further information regarding the boosting scheme is described in US Pat. No. 6,859,397 and US patent application Ser. No. 11 / 555,850. The contents of both of these documents are hereby incorporated by reference in their entirety.

  In step 612, the data state of the selected memory cell is verified using an appropriate set of target levels. If it is detected that the threshold voltage of the selected memory cell has reached an appropriate target level, the memory cell is increased, for example, by increasing the bit line voltage of the memory cell during subsequent write pulses. Excluded from subsequent writes. In step 614, it is checked whether all memory cells have reached the target threshold voltage. If it has reached, all the selected memory cells have been written and the target state has been verified, so the write process is complete and successful. In step 616, a “pass” status is notified. Note that in some implementations of step 614, it is checked whether at least a predetermined number of memory cells have been verified to be properly written. This predetermined number may be less than the total number of memory cells, and thus the write process may be completed before all the memory cells reach an appropriate verification level. Memory cells that have not been successfully written can be corrected by error correction in the read process.

  If it is determined in step 614 that all the memory cells have not reached the target threshold voltage, the write process continues. In step 618, the write counter PC is checked against the write limit value (PL). An example of the write limit value is 20. However, other values can be used in various implementations. If the write counter PC is not less than the write limit value, it is determined in step 630 whether the number of memory cells that have not been successfully written is equal to or less than a predetermined number. If the number of memory cells that failed to be written is equal to or less than the predetermined number, in step 632, a flag indicating that the writing process has passed is set, and a passing status is notified. In many cases, memory cells that fail to be written can be corrected using error correction in the read process. However, if the number of memory cells that have failed to be written is greater than the predetermined number, a flag indicating that the writing process has failed is set in step 634 and a failure status is notified.

  If it is determined in step 618 that the write counter PC is less than the write limit value, then in step 620 the system determines whether the write voltage has reached its maximum value (referred to as the maximum write voltage). . For example, in some memory systems, a charge pump is used to generate a write voltage from a supply voltage. The charge pump may have a maximum voltage value or the system may limit the maximum voltage value that can be applied to the word line. If the write voltage applied to the selected word line has not reached the maximum write voltage, the magnitude of the next Vpgm pulse is increased by a step size (eg, a step size of 0.2-0.4 volts). The write counter PC is incremented in step 622. In one embodiment, the pulse width is not changed in step 622. After step 622, the process loops back to step 610 and the next Vpgm pulse is applied.

  If it is determined in step 620 that the magnitude of the write voltage has reached the maximum write voltage (or exceeds the maximum write voltage), a verification process is performed to vary the duration of the write signal Vpgm. One or more write pulses are applied in between (step 624). For example, by using a write pulse with a wider pulse width or using a plurality of write pulses, the amount of write voltage applied to the selected memory cell during the verification process (eg, during the repetition of step 612) can be reduced. Will be increased. When using multiple write pulses to increase the amount of write voltage applied to the selected memory cell, the system may not perform verification processing between multiple pulses belonging to one pulse group. . More precisely, one or more verification processes are performed prior to the multi-pulse group (repetition prior to step 612), and one or more verification processes are performed following the multi-pulse group (following step 612). Can be done after (iteration). In either case of using a pulse having a wide pulse width or a case of using a plurality of write pulses, the magnitude of the write pulse can be made equal to or less than the maximum write voltage.

One aim of step 624 is to highly control the increase in the threshold voltage of the memory cell being written. In some embodiments using as a write signal a series of pulses that increase the magnitude of each of the pulses at a given step size, on average, the threshold voltage of the memory cell being written is a step size depending on each pulse. Increase with. Once the magnitude of the write pulse reaches the maximum write voltage, the pulse width of the pulse is increased (instead of increasing the pulse magnitude) in order to maintain the threshold voltage rise rate of the memory cell being written. be able to. Alternatively, a plurality of write pulses can be applied in order to obtain the same effect as increasing the pulse width. In any case, the duration of the write voltage applied to the selected memory cell during the verification process increases. In some embodiments, step 624 is used to keep the rate of increase of the threshold voltage the same as the rate of increase before reaching the maximum write voltage.
On the other hand, in other embodiments, an attempt is made to control the rate of increase of the threshold voltage using other measures.

  Step 624 also performs the operation of incrementing the program counter. After step 624, one or more verification processes are performed at step 612 and the process of FIG. 10 continues.

  Step 612 in FIG. 10 includes one or more verification processes. In general, during the verification process and the read process, the selected word line is connected to a voltage to determine whether the threshold voltage of the associated memory cell has reached those levels, and the voltage Levels are specified in each read and verify process (see, eg, B, C, D, E, F, G, and H in FIG. 7I). After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell is turned on according to the voltage applied to the word line. If a conduction current greater than a predetermined value is measured, the memory cell is turned on and it is estimated that the voltage applied to the word line is greater than the threshold voltage of the memory cell. If a conduction current greater than a predetermined value is not measured, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell.

  There are many ways to measure the conduction current of a memory cell in a read or verify process. As an example, the conduction current of the memory cell may be measured by the discharge rate or the charge rate of the conduction current to the dedicated capacitor of the sense amplifier. As another example, the conduction current of a selected memory cell may be configured to discharge (or not discharge) the corresponding bit line of a NAND string that includes the memory cell. In order to check whether the bit line has been discharged, after a certain period of time, the voltage of the bit line is measured.

  11A-C are flowcharts describing various embodiments for increasing the duration of a write signal. That is, each flowchart of FIGS. 11A to 11C shows an example of processing executed as part of step 624 in FIG.

  The embodiment of FIG. 11A includes using a wider pulse after reaching the maximum write voltage. In step 702 of FIG. 11A, the pulse width of the next write pulse is increased based on the constant. The constant can be the absolute value or ratio of the previous pulse width. For example, the pulse width can be increased to X times the previous pulse width or Y% of the previous pulse width. Step 702 includes applying a write pulse with a new wide pulse width. In one embodiment, the write voltage is applied at a magnitude of (or near) the maximum write voltage. In other embodiments, other sizes can be used. The process of FIG. 11A can be performed during the period of step 624 repeated in each loop of the process of FIG. 10 after Vpgm reaches the maximum write voltage. In one embodiment, step 702 may comprise setting up a charge pump.

  FIG. 12 is a diagram illustrating an example of a write signal according to the embodiment of FIG. 11A. The write pulses 802, 804, 806, 808, 810, 812, 814, 816, 818, and 820 are pulse groups each having a fixed pulse width and a size that increases with a fixed step size. The magnitude of the pulse 820 is the maximum write voltage. Returning to FIG. 10, before applying the pulse 820, step 620 will always exist before step 622, so the pulse magnitude increases with the step size (and the pulse width remains constant). . After the pulse 820 is applied and the verification process is performed, the step 620 increases the pulse width by performing the step 624 (step 702), and the magnitude of each pulse becomes a constant value of the maximum write voltage. Maintained. As shown in FIG. 12, pulse 822 has a wider pulse width than pulse 820, pulse 824 has a wider pulse width than pulse 822, and pulse 826 has a wider pulse width than pulse 824. The pulse 828 has a wider pulse width than the pulse 826. All the magnitudes of the pulses 822, 824, 826, and 828 are the magnitude of the maximum write voltage. In one embodiment, not all pulses that reach the maximum write voltage need have a larger pulse width.

  As described above, one or more verification pulses exist between write pulses. For example, seven magnitude verification pulses of B, C, D, E, F, G and H volts (see FIG. 7I) may be used. These verification pulses are not shown in FIG. 12 for ease of viewing the drawing. However, in FIG. 13, three write pulses 810, 812, and 814, in which there are seven verification pulses (and therefore seven verification processes) between pulses 810 and 812 and between pulses 812 and 814, are illustrated. Yes.

  FIG. 14 is a table showing another example of the write signal for the embodiment of FIG. 11A. The table shows examples of the magnitude and pulse width of the write signal. The table of FIG. 14 represents the average threshold voltage (Vth) of the memory cell group that is written from the erased state. As shown in FIG. 14, before reaching the maximum write voltage of 23.25 volts, the magnitude of the write pulse is increased with a fixed step size of 0.25 volts, which is a constant 10.00 (us). As a result, the average threshold voltage increases by 0.25 volts. After reaching the maximum write voltage of 23.25 volts, the write pulse magnitude is maintained at 23.25 volts. However, the pulse width of the write voltage increases so that the average threshold voltage continues to increase by 0.25 volts.

  Note that in one embodiment, pulse # 1 in FIG. 14 is not the first applied pulse. For example, when writing reaches a steady state with a pulse of 17.00 volts, there may be a pulse applied before this (# 1 pulse).

  FIG. 11B is another embodiment of the implementation of step 624 in FIG. In step 710, one or more customizable parameters are stored. These parameters indicate the pulse width size of the pulse used after reaching the maximum write voltage. For example, the one or more customizable parameters may include a parameter that indicates a step size when the pulse width is increased, and a parameter that indicates an increase rate of the pulse width. In other embodiments, a parameter may be stored for each pulse applied after reaching the maximum write voltage. Each parameter indicates the pulse width of each pulse. Step 710 in FIG. 11B is illustrated with a dotted line to indicate that step 710 may be performed at a different time than the other steps in FIG. 11B. As an example, customizable parameters may be set at the manufacturing or testing stage. As another embodiment, the user can set the parameters using the host device without choosing the time.

  In step 712, the system reads parameters associated with the next write pulse to be applied. In step 714, the next write pulse is applied with the pulse width set based on the parameter read in step 712. In one embodiment, a step of setting a charge pump circuit for adjusting the pulse width may be provided. The process of FIG. 11B includes using pulses of the same magnitude. For example, the magnitude of all pulses applied after reaching the maximum write voltage can be made equal to the maximum write voltage.

  FIG. 11C is another embodiment of the implementation form of step 624 in FIG. 10, in which a plurality of write pulses are applied between the verification processes in order to obtain the same effect as widening the pulse width. In step 720, the system determines the number of iterations of the write loop of FIG. 10 that has been performed by reaching the maximum write voltage. In step 722, one or more write pulses are applied based on the number of iterations determined in step 720. For example, after the maximum write voltage, the system applies a set of two write pulses at the maximum write voltage, followed by a set of three write pulses at the maximum write voltage, followed by four write pulses. For example, the set is applied at the maximum writing voltage. In step 722, additional write pulses are applied to achieve the desired technique of increasing the duration of the write voltage during the verification process. There is one or more verification process sets between each set of write pulses. Within the set of write pulses, the write pulse is applied without performing the verification process. In one embodiment, the determination of how many write pulses to apply is made by incrementing the number of pulses in each iteration of the write loop of FIG. 10 after reaching the maximum write voltage. In other embodiments, customizable parameters (see FIG. 11B) can be used to specify how many write pulses are used.

  FIG. 15 is a diagram illustrating a graphical display of an example of a write signal according to the embodiment of FIG. 11C. Write pulses 850, 852, 854, 856, 858, 860, 862, 864, 866, and 868 are pulses having a fixed pulse width and a magnitude that increases with a fixed step size. The magnitude of the pulse 868 is the maximum write voltage. Returning to FIG. 10, before applying pulse 868, step 620 will always be present before step 622, so the pulse magnitude increases with the step size (and the pulse width remains constant). . After pulse 868 is applied and the verification process is performed, step 620 implements step 624 so that the system configures itself to apply two pulses 870 and 872. Pulses 870 and 872 are both maximum write voltages and have the same pulse width as the previous pulse (but other pulse widths and magnitudes may be used). Next, when step 624 is executed, the system Sets itself to apply three pulses 874, 876 and 878. Then, when step 624 is executed, the system sets itself to apply four pulses 880, 882, 884 and 886. Such processing is performed.

  Verification processing is performed between a plurality of sets of write pulses (for example, 870 and 872 represent one set, and 874, 875, and 878 represent a plurality of sets), and verification processing is performed within one set of write pulses. I will not. Therefore, in this embodiment, the duration of an effective write signal can be made longer by using multiple write pulses between verification processes. For example, one or more verification processes are performed between the write pulse 868 and the write pulse 870. For example, in FIG. 16, seven verification processes are performed between the write pulse 868 and the write pulse 870 (in response to the seven verification pulses). No verification process is performed between the write pulse 870 and the write pulse 872. One or more verification processes are performed between the write pulse 872 and the write pulse 874. For example, in FIG. 16, seven verification processes are performed between the write pulse 872 and the write pulse 874 (in response to the seven verification pulses). No verification process is performed between the write pulses 874, 876 and 878. The verification process is also performed between each of the write pulses 850, 852, 854, 856, 858, 860, 862, 864, 866, and 868.

  In the alternative embodiment of the pulse signal of FIGS. 11C and 15, each of the set of pulses (eg, one set at 870 and 872 and one set at 874, 875, 878) is the combined duration of the pulses in the set. The magnitude of the pulse can be set so that the duration and magnitude give the target amount of writing. In one embodiment, the number of pulses in the set and the size of the pulses in the set can be determined from user-configurable parameters (see FIG. 11B) and / or It is also possible to set the writing amount to be constant in a set of (the above-mentioned writing amount may be the same as that of each pulse 850-868).

The above detailed description of the present invention is merely illustrative. The above detailed description of the present invention is not limited to the scope disclosed in detail. The technology disclosed in this specification can be variously modified and changed. The embodiments described above are selected in order to better explain the principle of the present invention and its specific application examples, and those skilled in the art will make various modifications to the present invention based on specific examples. obtain. The technical scope of the present invention is defined by the appended claims.

Claims (25)

Applying a write signal to the non-volatile storage element, comprising:
Applying a plurality of write pulses to the nonvolatile memory element with a constant pulse width before one or more pulses reach a maximum value;
Applying one or more write pulses that provide different durations of the length of the write signal to the nonvolatile memory element during a verification process after the one or more pulses reach a maximum value;
A writing method for a nonvolatile memory device, comprising:   The method of claim 1, wherein the plurality of write pulses having the constant pulse width are applied in increasing magnitude. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying one or more write pulses having different pulse widths. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying one or more write pulses of increasing pulse width. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying one or more write pulses whose pulse width varies at a constant value. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying one or more write pulses whose pulse width varies with a variable value. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying one or more write pulses whose pulse widths increase at a constant value. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying one or more write pulses whose pulse width increases with a variable value. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying one or more write pulses having the maximum value and increasing pulse width. With multiple customizable pulse width parameters
Applying one or more write pulses to the non-volatile storage element that provides different durations of the write signal length increases the pulse width based on the customizable pulse width parameter being retained. The method of claim 1, comprising applying one or more write pulses. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
2. The method of claim 1 comprising applying a plurality of pulses between verification processes. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
2. The method of claim 1, comprising applying a plurality of pulses of the maximum value between verification processes. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
The method of claim 1, comprising applying a pulse group of different numbers of write pulses to the non-volatile memory element between verification processes. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
Measuring how many times the write-verify period has been executed in the current time period;
Applying the plurality of write pulses to the non-volatile memory element based on the result of the measuring step. Applying the write signal comprises:
(A) applying a pulse to a control gate of the nonvolatile memory element;
(B) performing one or more verification processes on the nonvolatile memory element;
(C) determining whether a maximum voltage value is used for the write signal;
(D) repeating steps (a)-(c) with larger pulses if the maximum voltage value is not already used for the write signal;
(E) repeating steps (a)-(c) with one or more pulses having a longer duration if the maximum voltage value is used for the write signal;
The method of claim 1 comprising: A non-volatile memory element;
One or more management circuits in communication with the non-volatile storage element;
The one or more management circuits apply a plurality of write pulses to the nonvolatile memory element with a constant pulse width before the one or more pulses reach a maximum value, and the one or more pulses have a maximum value. Applying one or more write pulses to the non-volatile memory element during a verification process to provide one or more write pulses that provide different durations of the write signal after reaching A nonvolatile memory device system for performing writing.   17. The nonvolatile memory system according to claim 16, wherein the plurality of write pulses having the constant pulse width are applied with an increased size by the one or more management circuits. Providing different durations of the length of the write signal, applying one or more write pulses to the non-volatile storage element;
17. The nonvolatile memory device system according to claim 16, wherein the one or more management circuits apply one or more write pulses having different pulse widths. Applying one or more write pulses that provide different durations of the write signal to the non-volatile storage element;
17. The nonvolatile memory system according to claim 16, wherein the one or more management circuits apply one or more write pulses whose pulse width increases. Applying one or more write pulses that provide different durations of the write signal to the non-volatile storage element;
17. The nonvolatile memory device system according to claim 16, wherein the one or more management circuits apply one or more write pulses whose pulse width changes at a constant value. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
17. The nonvolatile memory system according to claim 16, further comprising a step of applying one or more write pulses in which the one or more management circuits increase in pulse width at a constant value. Applying one or more write pulses to the non-volatile memory element that provide different durations of the write signal length;
17. The nonvolatile memory system according to claim 16, further comprising the step of applying one or more write pulses in which the one or more management circuits have the maximum value and the pulse width increases. Applying one or more write pulses that provide different durations of the write signal to the non-volatile storage element;
17. The nonvolatile memory device system according to claim 16, wherein the one or more management circuits apply a plurality of pulses between verification processes. Applying one or more write pulses that provide different durations of the write signal to the non-volatile storage element;
17. The nonvolatile memory system according to claim 16, wherein the one or more management circuits apply the plurality of pulses having the maximum value between verification processes.   17. The nonvolatile memory device system according to claim 16, wherein the nonvolatile memory element is a flash memory device.

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