JPH10269790A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a voltage margin of a sense amplifier from decreasing due to cell data in the neighborhood of a memory cell reading data or a position on a chip. SOLUTION: A plurality of main body cell arrays 21, a dummy cell array 22, a bias circuit 16, a row decoder 18, sense amplifiers 23 constituting a data detection circuit and a reference voltage circuit 24 are provided in one block of a memory circuit. A d.c. bias voltage PR generated at the bias circuit 16 is supplied to the main body cell arrays 21 and dummy cell array 22. The sense amplifiers 23 constituting the data detection circuit supply a predetermined bias voltages SAIN to column lines in the main body cell arrays 21 when data are read out, thereby detecting data. The reference voltage circuit 24 supplies a predetermined bias voltage REFIN to the dummy cell array 22, there by generating a comparison reference voltage VREF which it to be used when the sense amplifiers 23 detect data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a method for detecting data in a read-only semiconductor memory device of a virtual ground system.

[0002]

2. Description of the Related Art FIG. 6 shows a main part of a semiconductor memory device of this kind. In FIG. 6, when memory cells 1 to 5 are sequentially selected, each signal is set as follows.

For example, when memory cell 1 is selected, decode signal X1 is set to logic "1", its inverted signal / X1 is set to logic "0", and other decode signals X2 to X4 are set to logic "0". Is done. Also, the decode signal X2
To X4 are set to logic "1". Further, decode signal Y1 is set to logic "0", and inverted signal / Y1 is set to logic "1". Decode signal b1 is set to logic "1", and inverted signal / b1 is set to logic "0". Each of the other decode signals b2 to b5 is set to logic "0", and each inverted signal / b of these decode signals b2 to b5 is set.
2 to / b5 are set to logic "1". In this state, when row line WL1 is set to logic "1", for example, 5V, and the remaining row lines are set to logic "0", data is read from memory cell 1.

In this state, when signal Y1 changes to logic "1" and signal / Y1 changes to logic "0", memory cell 2 is selected. With this memory cell 2 selected, the signal b
When 1 changes to logic "0" and its inverted signal / b1 changes to logic "1", signal b2 changes to logic "1" and its inverted signal / b2 changes to logic "0", the memory cell 3 is selected. When the signal Y1 changes to logic "0" and the inverted signal / Y1 changes to logic "1" while the memory cell 3 is selected, the memory cell 4 is selected. In a state where the memory cell 4 is selected, the decode signal X1 changes to logic "0" and the inverted signal / X1 changes to logic "1", and the decode signal X1 changes to "1".
When 2 changes to logic "1" and its inverted signal / X2 changes to logic "0", the memory cell 5 is selected.

Next, a detailed operation when selecting the memory cell 1 will be described. As described above, when memory cell 1 is selected, decode signal X1 is set to logic "1", its inverted signal / X1 is set to logic "0", and the other decode signals X2 to X4 are set to logic "0", respectively. Decode signal X2
To X4 are set to logic "1". Further, decode signal Y1 is set to logic "0", and inverted signal / Y1 is set to logic "1". Decode signal b1 is set to logic "1", inverted signal / b1 is set to logic "0", and other decode signals b2 to b5 are set to logic "0". Each inverted signal / b of these decode signals b2 to b5
2 to / b5 are set to logic "1".

In this state, when the row decoder 71 sets the row line WL1 to logic "1", for example, 5V, and sets the remaining row lines to logic "0", the transistor t1
Is turned on, and the transistor t2 is turned off. Further, since the transistor t3 is on, the transistor t3
The column line C2 is supplied with the ground potential via the transistor t1. That is, one end of the memory cell 1 connected to the column line C2 is connected to the transistor t3 and the transistor t1.
And to the ground potential. Further, since the transistor t6 is turned off and the transistor t7 is turned on, the column line C1, that is, the other end of the memory cell 1 is connected to the transistor t7.
Is connected to the data detection circuit 72 via the. The logic "0" and the logic "1" are stored in the memory cell depending on the level of the threshold voltage. When the threshold voltage is high, even if a row line becomes logic "1" and a memory cell is selected, the memory cell is not turned on. If the threshold voltage is low, the selected memory cell is turned on. .

Now, the memory cells located between the column lines C1 and C2 are connected to the row lines WL2 to WLn because the row lines WL2 to WLn are in a non-selected state with the logic "0". The memory cell that is turned off. When the threshold voltage of the memory cell is high, the memory cell 1 is off even if the row line WL1 is at logic "1". Since the transistor t4 is also off, the column line C1 is charged by a load transistor (not shown) provided in the data detection circuit 72, and the charged state is detected by the data detection circuit 72. It is determined that the stored data is logic “1”.

On the other hand, when the threshold voltage of the memory cell is low, since the memory cell 1 is on, the column line C1 is discharged toward the ground potential through the memory cell 1, the transistor t3, and the transistor t1, This discharge state is detected by the data detection circuit 72, and for example, it is determined that the data stored in the memory cell 1 is logic "0".

The difference between the selection of memory cell 2 and the selection of memory cell 1 as described above is that signals Y1 and / Y
There is only one logic level. Therefore, the transistor t
4 turns on and the transistor t3 turns off. Therefore, when the threshold voltage of the memory cell 2 is high, the column line C1 is electrically separated from the column line C3, and the charged state is detected by the data detection circuit 72.

On the other hand, when the threshold voltage of the memory cell is low, the column line C1 is discharged toward the ground potential through the transistor t4, the memory cell 2, and the transistor t1,
This discharge state is detected by the data detection circuit 72. When the signal b2 is set to logic "1" and the column line C4 or the column line C5 is connected to the data detection circuit 72, the data of the memory cell 3 or 4 is read.

By the way, in the semiconductor memory device having the above configuration, a memory cell having a low threshold voltage is turned on even when data is not read when the row line becomes logic "1". For example, when the memory cell 4 is selected and the threshold voltage of the memory cell 4 is high, the memory cell 4 is turned off. However, if the threshold voltage of the memory cell 5 adjacent to the memory cell 4 is low, the memory cell 5 turns on. For example, in FIG. 6, when the threshold voltages of the memory cell 5 and all the memory cells connected to the row line WL1 arranged on the right side of the memory cell 5 are low, all of these memory cells are turned on. Therefore, the column line C5 and all the column lines located on the right side of the column line C5 are connected through the memory cells in the ON state.

Now, assuming that these column lines are at the ground potential, when the load transistor in the data detection circuit 72 charges the column line C5 through the transistor t8, it is located to the right of the column line C5 through the memory cell 5. All column lines are charged. Therefore, the data of the memory cell 4 cannot be read until the charging of these column lines is completed,
Data reading speed becomes slow. Therefore, the column lines in the non-selected state are charged to a predetermined potential by the bias circuit 73.

When memory cell 1 is selected, signals b2 to b5 are logic "0" and their inverted signals / b2 to / b5.
Is a logic "1", the transistors t17 to t20 to which these signals are input to the gates are turned on, and the column line connected thereto is charged to a predetermined potential by the bias circuit 73. The signals / X2 to / X4 are also logic "1".
Therefore, the transistors t11 to t13 to which these signals are input to the gates are turned on, and the column lines connected thereto are charged to a predetermined potential by the bias circuit 73. Further, since one of the signals Y1 and / Y1 becomes logic "1", for example, the column line C6 is also connected to the column line C7, and of the two transistors to which the signals Y1 and / Y1 are supplied, respectively. It is connected to the bias circuit 73 through one of the ON-states, and the column line in the non-selected state is charged with a predetermined potential and waits for selection. In this way, the charging of the column line selected by the data detection circuit is not delayed.

When data stored in the memory cell is detected by the data detection circuit 72, a reference voltage for comparison is generated using a dummy cell for reference.

FIG. 7 shows a configuration of one block of a memory circuit in a conventional semiconductor memory device. In addition to the main body cell array 74, a dummy cell array 75 provided with a plurality of reference dummy cells is provided.
The main body cell array 74 is supplied with a column line charging DC bias voltage PR generated by the bias circuit 73.
The bias voltage REFIN generated by the reference voltage circuit REF is supplied to the dummy cell array 75. The reference voltage circuit REF generates a voltage having a value corresponding to the amount of current flowing from the bias voltage REFIN through the dummy cell array 75 as the reference voltage VREF. This reference voltage V
REF is supplied to a plurality of sense amplifiers S / A constituting the data detection circuit 72, respectively. The plurality of sense amplifiers S / A apply a voltage based on the sense amplifier input voltage SAIN whose level changes according to the read data from the main body cell array 74 to the reference voltage VREF.
Data is detected by comparing with each. Then, a plurality of blocks as shown in FIG. 7 are formed on the chip to form a memory circuit.

In the conventional semiconductor memory device, the reference dummy cell array is arranged at a position far away from the main body cell array, and the value of the reference voltage VREF is influenced by the DC bias voltage PR generated by the bias circuit 73. , And its value is fixed.

FIG. 8 shows the dummy cell array 7 in FIG.
5 and its peripheral circuits. 8, transistors t41 and t42 correspond to transistors t1 and the like in FIG.
43 and t44 are the transistors corresponding to the transistors t3 and t5, etc., the transistors t45 and t46 are the transistors corresponding to the transistors t4 and t14, the transistor t47 is the transistor corresponding to the transistor t8 and the like, and the other transistors are dummy cells. Is composed. In the figure, the number "0" given to the transistor indicates that the stored data is "0", the transistor has a low threshold voltage, and Vcc (5 V) is supplied to the gate. Then, it is turned on. Similarly, the number "1" attached to the transistor indicates that the stored data is "1". The transistor has a high threshold voltage, and even if Vcc (5 V) is supplied to the gate. It turns off without turning on. Further, in the figure, the dummy cells with circles are reference dummy cells, and a current flows from the bias voltage REFIN to the ground potential Vss via the dummy cells. The reference voltage circuit REF in FIG. 7 generates a voltage having a value corresponding to the amount of current flowing from the bias voltage REFIN through the dummy cell as the reference voltage VREF.
This voltage VREF is not affected by the DC bias voltage PR, and its value is fixed.

[0018]

By the way, even in the same chip, the power supply voltage supplied due to the influence of the wiring resistance is larger in the block far from the power supply pad than in the block close to the power supply pad. And the value of the DC bias voltage PR generated by the bias circuit also decreases. Then, the following inconvenience occurs.

FIG. 9 is a diagram for explaining a data read operation when the selected cell in the main body cell array is the "1" cell. Other cells around the selected cell are set to the data storage state as shown. Suppose you have At this time, the column line C21 located on the right side of the selected cell is charged by the sense amplifier input voltage SAIN of the sense amplifier S / A. At this time, if this block is located far away from the power supply pad and the voltage PR is lower than the voltage SAIN,
As shown by the dashed arrow a in the figure, the voltage PR from the voltage SAIN to the voltage PR through a plurality of memory cells of logic "0" data.
, And the level of the voltage SAIN decreases. That is, in a block far away from the power supply pad, the potential corresponding to the logic "1" input to the sense amplifier S / A at the time of reading "1" becomes low.
The operating voltage margin of the sense amplifier S / A at the time of reading "1" is reduced. At the time of this reading, the floating node is charged with a voltage equal to the voltage PR as indicated by a broken line arrow b in the figure by means not shown.

On the other hand, FIG. 10 illustrates a data read operation when the selected cell in the main body cell array is a "0" cell, and other cells around the selected cell are set to the data storage state as shown. It is assumed that it is. At this time, the sense amplifier input voltage SAIN of the sense amplifier S / A is discharged to the ground potential Vss via the selected cell. At this time, if this block is located close to the power supply pad and the voltage PR is higher than the voltage SAIN, a dashed arrow a in FIG.
As shown by, a current flows from the voltage PR to the voltage SAIN through a plurality of memory cells of logic “0” data, and the level of the voltage SAIN rises. In other words, in a block near the power supply pad, the potential corresponding to the logic "0" input to the sense amplifier S / A at the time of reading "0" rises, and thus the sense amplifier S / A at the time of "0" reading. Operating voltage margin becomes low. In this case as well, the floating node is charged with a voltage equal to the voltage PR as indicated by a broken arrow b in the figure by means not shown.

As described above, in the conventional semiconductor memory device, the value of the reference voltage VREF generated using the dummy cell for reference is fixed, but the value of the DC bias voltage PR generated by the bias circuit is fixed. Since the value is affected by the power supply voltage and the read potential (SAIN) from the memory cell is affected by the DC bias voltage PR, there is a problem that the operating voltage margin of the sense amplifier is reduced depending on the position on the chip. I do.

The present invention has been made in consideration of the above circumstances, and has as its object to reduce the operating voltage margin of a sense amplifier depending on the cell data around a memory cell from which data is read and the position on a chip. It is an object of the present invention to provide a semiconductor memory device which can prevent the occurrence of the problem.

[0023]

According to a first aspect of the present invention, there is provided a semiconductor memory device, wherein a plurality of row lines and a plurality of column lines are respectively connected between two adjacent ones of the plurality of column lines, and a gate is provided. A plurality of memory cells each including a transistor connected to a corresponding one of the plurality of row lines and storing data corresponding to a threshold voltage, and one end of a memory cell from which data is read at the time of reading data are connected. First selecting means for selecting a connected column line and connecting it to the ground potential, and second selecting means for selecting a column line to which the other end of the memory cell from which data is to be read is connected when reading data A data detection circuit for supplying a predetermined DC bias voltage to the column line selected by the second selecting means to detect data when reading data, and generating a predetermined DC bias voltage. A bias circuit that supplies a non-selected column line when data is read, and a DC voltage having a value corresponding to the DC bias voltage generated by the bias circuit, and supplies the data detection circuit as a reference voltage for comparison. And a reference voltage generating circuit for comparison.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the comparison voltage generating circuit is connected in series, and a plurality of dummy cells in which an arbitrary series connection point in the middle is connected to a ground potential; A means for supplying a DC bias voltage generated by the bias circuit to one end of a plurality of serially connected dummy cells; and a means for connecting the other end of the plurality of serially connected dummy cells to generate the comparison reference voltage. And a reference voltage circuit.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the reference voltage circuit includes a load unit connected between a node of the reference voltage for comparison and a node of a power supply voltage. A first MOS transistor having one end connected to the voltage node and the other end connected to the other end of the plurality of serially connected dummy cells; and an input terminal connected to the other end of the first MOS transistor. A first inverter circuit having an output terminal connected to the gate of the first MOS transistor, one end connected to the node of the power supply voltage, and the other end connected to the other end of the plurality of dummy cells connected in series. A second MOS transistor connected;
A second inverter circuit having an input terminal connected to the other end of the second MOS transistor and an output terminal connected to the gate of the second MOS transistor.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the second aspect, a plurality of sets of the series-connected dummy cells are provided by the number of the row lines, and the gates of the plurality of series-connected dummy cells are provided. Each is connected to a corresponding row line.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the second or fourth aspect, each of the plurality of dummy cells stores data corresponding to a low threshold voltage.

According to a sixth aspect of the present invention, a semiconductor memory device includes a power supply pad to which a power supply voltage is supplied, and a memory circuit having a plurality of blocks to which the power supply voltage supplied to the power supply pad is supplied via a power supply wiring. In each of the blocks of the memory circuit, a plurality of row lines and column lines are respectively connected between two adjacent column lines of the plurality of column lines, and a gate is formed of the plurality of row lines. A plurality of memory cells, each of which is connected to a corresponding one of the transistors and stores data corresponding to a threshold voltage, and a column line to which one end of the memory cell from which data is read at the time of reading data is connected. Select and connect to ground potential first
Selection means, a second selection means for selecting a column line to which the other end of the memory cell from which data is read at the time of reading data is connected, and a second selection means at the time of reading data. A data detection circuit that supplies a predetermined DC bias voltage to the column line and detects data, and generates a predetermined DC bias voltage from a power supply voltage supplied through the power supply wiring, and selects a non-selected bias voltage when reading data. A bias circuit that supplies a column line, and a comparison reference voltage generation circuit that generates a DC voltage having a value corresponding to the DC bias voltage generated by the bias circuit and supplies the DC voltage to the data detection circuit as a comparison reference voltage Is provided.

A semiconductor memory device according to claim 7 is the semiconductor memory device according to claim 6, wherein the comparison voltage generating circuit is connected in series, and a plurality of dummy cells in which an arbitrary series connection point in the middle is connected to ground potential. A means for supplying a DC bias voltage generated by the bias circuit to one end of a plurality of serially connected dummy cells; and a means for connecting the other end of the plurality of serially connected dummy cells to generate the comparison reference voltage. And a reference voltage circuit.

In the semiconductor memory device according to the present invention, the reference voltage circuit may be a load means connected between a node of the reference voltage for comparison and a node of a power supply voltage. A first MOS transistor having one end connected to the voltage node and the other end connected to the other end of the plurality of serially connected dummy cells; and an input terminal connected to the other end of the first MOS transistor. A first inverter circuit having an output terminal connected to the gate of the first MOS transistor, one end connected to the node of the power supply voltage, and the other end connected to the other end of the plurality of dummy cells connected in series. A second MOS transistor connected;
A second inverter circuit having an input terminal connected to the other end of the second MOS transistor and an output terminal connected to the gate of the second MOS transistor.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the seventh aspect, a plurality of sets of the series-connected dummy cells are provided by the number of the row lines, and the gates of the plurality of series-connected dummy cells are provided. Each is connected to a corresponding row line.

According to a tenth aspect of the present invention, there is provided a semiconductor memory device according to the seventh aspect.
Or 9) each of the plurality of dummy cells stores data corresponding to a low threshold voltage.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration inside a chip in a semiconductor memory device according to the present invention. In the figure, reference numerals 11 and 11 denote power supply pads to which a power supply voltage Vcc (for example, 5 V) is supplied from the outside.
Are power supply pads to which a ground voltage Vss (for example, 0 V) is supplied from the outside. Then, the power pad 1
The power supply voltage Vcc supplied to the power supply lines 1 and 11 is
Are supplied to the respective sections of the memory circuit through. Similarly, the ground voltage Vss supplied to the power supply pads 12, 12 is supplied to each part of the memory circuit via power supply wirings 14, 14,.

The memory circuit has a plurality of blocks (8 blocks in this example), and each block has a cell array 15 having memory cells of 4 I / O (the number of data input / output bits is 4). , A bias circuit 16 and a data detection circuit (S / A) 17 are provided. Each of the cell arrays 15 is provided with a plurality of row lines WL1 to WLn and column lines C1, C2, C3,... In addition to a plurality of memory cells.
Are arranged as shown in FIG. That is, each memory cell is connected between two adjacent ones of the plurality of column lines, and the gate of each memory cell is connected to the plurality of row lines WL.
1 to WLn are connected to corresponding ones. Each of these memory cells is constituted by a transistor for storing data in accordance with the state of the threshold voltage. Further, a plurality of reference dummy cells (not shown) are provided in each of the cell arrays 15.

A row decoder 18 is provided between adjacent blocks (indicated by hatching in the figure).

The power supply voltage Vcc on the power supply lines 13, 13, ... and the ground voltage Vss on the power supply lines 14, 14, ... are supplied to the bias circuit 16 and the data detection circuit 7 of each block, respectively.

FIG. 2 is a circuit diagram of the memory circuit shown in FIG.
2 shows a schematic configuration of one block. The cell array 15 includes 4I /
, And a dummy cell array 22 provided with a plurality of reference dummy cells. The DC bias voltage PR generated by the bias circuit 16 is supplied to the four body cell arrays 21, 21,... And the dummy cell array 22.

The data detection circuit 17 is provided with four sense amplifiers (S / A) 23, 23,... When the data is read, these four sense amplifiers 23, 23,... Supply a predetermined bias voltage SAIN to the column lines in the main body cell arrays 21, 21,.

A reference voltage circuit (REF) 24 is connected to the dummy cell array 22. The reference voltage circuit 24 supplies a predetermined bias voltage REFIN to the dummy cell array 22 to generate a comparison reference voltage VREF used when each of the sense amplifiers 23, 23,... Detects data. .

FIG. 3 shows a detailed configuration of the dummy cell array 22 and its peripheral circuits in FIG. In this example, 32 row lines WL1 to WL32 are provided. In the dummy cell array 22, six dummy cells are provided for each row line. Of the six dummy cells provided for each row line, logic "0" data is stored in four adjacent dummy cells DC1 to DC4, and two dummy cells DC1 to DC4 are provided on the main body cell array side. Each of the dummy cells DC5 and DC6 stores logic "1" data.

The transistor t30 in FIG. 3 corresponds to the transistor t6 and the like in FIG. 6, the transistor t31 also corresponds to the transistor t8 and the like, and the transistors t32, t33, and t
Reference numeral 34 also corresponds to the transistors t4, t14, etc., transistors t35, t36, t37 also correspond to the transistors t3, t5, etc., and the transistors t38, t39 also correspond to the transistors t1, t2, etc. ing. The gates of the transistors t30, t31, t38, and t39 are supplied with a signal of the voltage Vcc, and these transistors are turned on.

Here, of the four dummy cells DC1 to DC4 provided for each row line and connected in series,
A series connection point NS of the dummy cells DC2 and DC3 is connected to the ground potential Vss via the transistor t38 which is turned on. On the other side of the dummy cell DC1 from the side of the dummy cell DC2, the DC bias voltage P generated by the bias circuit 16 (shown in FIG. 2) is supplied via the transistor t30 which is turned on.
R is supplied. Further, the bias voltage REFIN generated by the sense amplifier 23 (shown in FIG. 2) is supplied to the dummy cell DC5 side of the dummy cell DC4 via the transistor t31 which is turned on.

Here, as shown in FIG. 1, the DC bias voltage PR generated by the bias circuit 16 in the block located far from the power supply pad 11 on the chip.
Is low, and the value of the DC bias voltage PR generated by the bias circuit 16 in the block close to the power supply pad 11 is high.

Now, in the circuit shown in FIG. 3, if the values of the bias voltage PR and the bias voltage REFIN are equal,
The number of transistors existing on the current path between the bias voltage PR and the series connection point NS of the dummy cells DC2 and DC3, and the number of transistors existing on the current path between the bias voltage REFIN and the series connection point NS Are equal, the value of the reference voltage VREF generated by the reference voltage circuit 24 in FIG. 2 is substantially equal to the bias voltage REFIN.
Is set only by the value of

On the other hand, in a block in which the value of the DC bias voltage PR generated by the bias circuit 16 is low, the memory cell is selected because the charging voltage PR for charging the column line prior to reading data from the memory cell is also low. The bias voltage REFIN output from the sense amplifier 23
Will decrease under the influence of the charging voltage of this column line.

However, as shown in FIG.
Is also supplied to the dummy cell array, and this voltage PR
Is the path of the transistor t30 and the dummy cells DC1 and DC2, or the transistor t30 and the transistor t3
2. The voltage REFIN is supplied to the series connection point NS via the path of the dummy cell DC2, and the voltage of the transistor t3
1, the path of the dummy cells DC4 and DC3, or the transistor t31, the transistor t33, and the dummy cell DC3
And the two voltages are supplied to the series connection point NS via the same number of transistors in series.
Are matched. Therefore, the voltage REFIN is affected by the voltage PR, and the lower the voltage PR, the lower the voltage REFIN. Conversely, the higher the voltage PR, the higher the voltage REFIN.

FIG. 4 shows the configuration of the reference voltage circuit 24 and one sense amplifier 23 in FIG. In the sense amplifier 23, P channel transistors 41, 42, N
The channel transistors 43 and 44 constitute a current mirror type differential amplifier. The above transistors 41, 4
2 are connected to the node of the power supply voltage Vcc. The drains of the transistors 43 and 44 are connected to the drains of the transistors 41 and 42, respectively. The sources of the transistors 43 and 44 are connected to the node of the ground voltage Vss. The gates of the transistors 43 and 44 are connected to each other, and the common gate is connected to the drain of the transistor 44.

The gate of the transistor 41 serves as one input node of the differential amplifier, and a source and a drain of a P-channel transistor 46 serving as a load transistor are inserted between the node 45 and the node of the power supply voltage Vcc. I have. The gate of this transistor 46 is connected to its drain. A source and a drain of the N-channel transistor 47 are inserted between the node 45 and the node of the voltage SAIN (body cell array). The input terminal of the inverter 48 is connected to the drain (the voltage SAIN side) of the transistor 47, and the output terminal of the inverter 48 is connected to the gate of the transistor 47. Between the node of the power supply voltage Vcc and the node of the voltage SAIN, a portion between the source and the drain of the N-channel transistor 49 is inserted. The input terminal of the inverter 50 is connected to the drain (voltage SAIN side) of the transistor 49, and the output terminal of the inverter 50 is connected to the gate of the transistor 49.

Further, the output of the differential amplifier is amplified by an amplifier composed of three inverters connected in series, so that read data SAOUT is obtained.

The reference voltage circuit 24 includes a P-channel transistor 52 having a source and a drain inserted between a node 51 serving as the other input node of the differential amplifier and a node of the power supply voltage Vcc, and having a load transistor. An N-channel transistor 53 having a source and a drain inserted between the node 51 and the node of the voltage REFIN (dummy cell array), and an input terminal connected to the drain (voltage REFIN side) of the transistor 53 and an output An inverter 54 having a terminal connected to the gate of the transistor 53; a node of the power supply voltage Vcc;
An N-channel transistor 55 having a source and a drain inserted between it and the FIN node, an input terminal connected to the drain (voltage REFIN side) of the transistor 55, and an output terminal connected to the gate of the transistor 55 And an inverter 56.

In the circuit thus constructed, the value of the voltage SAIN is determined by the transistor 49 and the inverter 50.
This is set by a feedback circuit consisting of That is, immediately after the power supply voltage Vcc is applied, the voltage SAI
Since N is 0, the output signal of the inverter 50 becomes "1" level, and the transistor 49 is turned on. Therefore, after the power supply voltage Vcc is applied, the voltage SAIN rises, and thereafter, the voltage SAIN is set to a value according to the current capability of the transistor 49, that is, the element size.

When data is read, the voltage SAIN is discharged via the selected cell or the value is maintained without being discharged. Voltage SA via selected cell
When IN is discharged, the voltage VDAT at node 45 also drops. If voltage SAIN is not discharged, node 4
The voltage VDAT of 5 is maintained as it is.

On the other hand, in the reference voltage circuit 24, the voltage VREFIN is discharged through the dummy cell at the time of data reading, so that the voltage VREFIN decreases, and
The voltage VREF at 1 also drops.

Here, the current capability of the transistor 52 serving as the load transistor of the node 51 in the reference voltage circuit 24 is set to be larger than the current capability of the transistor 46 serving as the load transistor of the node 45 in the sense amplifier 23. Therefore, the voltage VREF becomes an intermediate value between the voltage VDAT at the time of reading “0” and the voltage VDAT at the time of reading “1”, and the read data SAOUT is obtained by comparing the two voltages VREF and VDAT with the differential amplifier. Is obtained.

Here, as described above, the voltage REFIN is affected by the voltage PR in the dummy cell array shown in FIG. 3, and when the voltage PR becomes lower, the voltage REFIN is correspondingly reduced.
Becomes lower, and conversely, as the voltage PR becomes higher, the voltage REFIN also becomes higher. Therefore, the value of the voltage VREF obtained at the node 51 also changes according to the voltage PR. Therefore,
The voltage SAIN fluctuates due to the variation of the charging voltage (voltage PR) of the column lines of the main body cell array in the chip, and the reduction of the voltage margin of the sense amplifier caused by the fluctuation of the voltage VDAT at the node 45 is caused by the value of the voltage VREF. Is changed according to the voltage PR.

FIG. 5 shows an example of a specific circuit of the bias circuit 16 in FIG. This circuit has an N-channel transistor 61 connected to the drain or the node of the power supply voltage Vcc, an input terminal connected to the source of the transistor 61 (a side for obtaining the DC bias voltage PR), and an output terminal connected to the gate of the transistor 61. And an inverter 62 connected to the inverter 62.

In the case of the bias circuit 16 as well, the value of the DC bias voltage PR is basically determined by the current capability of the transistor 61, that is, the element size, but also affects the value of the supplied power supply voltage Vcc. Receive.

[0059]

As described above, according to the present invention,
It is possible to prevent the voltage margin of the sense amplifier from being lowered due to the cell data around the memory cell from which data is read or the position on the chip.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration inside a chip in a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of one block in the memory circuit in FIG. 1;

FIG. 3 is a circuit diagram showing a detailed configuration of a dummy cell array and peripheral circuits in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of a reference voltage circuit and one sense amplifier in FIG. 2;

FIG. 5 is a circuit diagram showing an example of a specific circuit of the bias circuit in FIG. 1;

FIG. 6 is a circuit diagram showing a configuration of a main part of a conventional semiconductor memory device according to the present invention;

FIG. 7 shows one of memory circuits in a conventional semiconductor memory device.
FIG. 2 is a block diagram showing a configuration for blocks.

FIG. 8 is a circuit diagram showing a configuration of a dummy cell array and peripheral circuits in FIG. 7;

FIG. 9 is a circuit diagram for describing a data read operation when a selected cell in a main body cell array is a “1” cell.

FIG. 10 is a circuit diagram illustrating a data read operation when a selected cell in a main body cell array is a “0” cell.

[Explanation of symbols]

 11 power supply pad (for Vcc), 12 power supply pad (for Vss), 13 power supply wiring (for Vcc), 14 power supply wiring (for Vss), 15 cell array, 16 bias circuit, 17 data detection circuit 18 row decoder 21 body cell array 22 dummy cell array 23 sense amplifier (S / A) 24 reference voltage circuit (REF)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yuichi Tatsumi 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Inside (72) Inventor Noriaki Suzuki 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Toshiba Microelectronics Co., Ltd.

Claims (10)

[Claims] 1. A plurality of row lines and column lines, respectively, connected between two adjacent column lines of the plurality of column lines, and a gate connected to a corresponding one of the plurality of row lines; Select a plurality of memory cells, each of which stores data corresponding to the threshold voltage, and a column line to which one end of the memory cell from which data is read when reading data is connected, and connect to the ground potential First selecting means for selecting, when reading data, second selecting means for selecting a column line to which the other end of the memory cell from which data is read is connected, and when reading data, the second selecting means A data detection circuit that supplies a predetermined DC bias voltage to a column line selected by the data detection circuit and detects data, and generates a predetermined DC bias voltage and supplies the data to a non-selected column line when reading data. And a comparison reference voltage generation circuit that generates a DC voltage having a value corresponding to the DC bias voltage generated by the bias circuit and supplies the DC voltage to the data detection circuit as a comparison reference voltage. A semiconductor memory device characterized by the above-mentioned. 2. The comparison voltage generating circuit according to claim 1, wherein the plurality of dummy cells are connected in series, and an arbitrary series connection point in the middle is connected to a ground potential. Means for supplying a DC bias voltage generated by a bias circuit; and a reference voltage circuit connected to the other end of the plurality of dummy cells connected in series and generating the comparison reference voltage. The semiconductor memory device according to claim 1. 3. The reference voltage circuit includes: a load unit connected between a node of the reference voltage for comparison and a node of a power supply voltage; one end connected to the node of the reference voltage for comparison; A first MOS transistor having the other end connected to the other end of the plurality of dummy cells, an input terminal connected to the other end of the first MOS transistor, and an output terminal connected to the gate of the first MOS transistor. A second MOS transistor having one end connected to a node of the power supply voltage and the other end connected to the other end of the plurality of dummy cells connected in series; and an input terminal. Is connected to the other end of the second MOS transistor, and a second inverter circuit having an output terminal connected to the gate of the second MOS transistor. The semiconductor memory device according to Motomeko 2. 4. The method according to claim 1, wherein a plurality of sets of the series-connected dummy cells are provided by the number of the row lines, and the gates of the plurality of series-connected dummy cells are connected to the corresponding row lines, respectively. 3. The semiconductor memory device according to claim 2, wherein: 5. The semiconductor memory device according to claim 2, wherein each of the plurality of dummy cells stores data corresponding to a low threshold voltage. 6. A power supply pad to which a power supply voltage is supplied, and a memory circuit having a plurality of blocks supplied with a power supply voltage supplied to the power supply pad via a power supply wiring. In the block, a plurality of row lines and column lines are respectively connected between two adjacent column lines of the plurality of column lines, and a gate is connected to a corresponding one of the plurality of row lines. Select a plurality of memory cells, each of which stores data corresponding to the threshold voltage, and a column line to which one end of the memory cell from which data is read when reading data is connected, and connect to the ground potential First selecting means for selecting the column line to which the other end of the memory cell from which data is to be read is connected at the time of reading data; and A data detection circuit for supplying a predetermined DC bias voltage to the column line selected by the second selection means to detect data, and generating a predetermined DC bias voltage from a power supply voltage supplied via the power supply wiring A bias circuit that supplies a non-selected column line when reading data; and a DC voltage having a value corresponding to the DC bias voltage generated by the bias circuit, which is supplied to the data detection circuit as a reference voltage for comparison. And a reference voltage generating circuit for comparison. 7. The comparison voltage generation circuit, wherein: a plurality of dummy cells which are connected in series, and an arbitrary series connection point in the middle is connected to a ground potential; Means for supplying a DC bias voltage generated by a bias circuit; and a reference voltage circuit connected to the other end of the plurality of dummy cells connected in series and generating the comparison reference voltage. The semiconductor memory device according to claim 6. 8. The reference voltage circuit, a load means connected between a node of the reference voltage for comparison and a node of a power supply voltage, one end connected to the node of the reference voltage for comparison, and the series connection A first MOS transistor having the other end connected to the other end of the plurality of dummy cells, an input terminal connected to the other end of the first MOS transistor, and an output terminal connected to the gate of the first MOS transistor. A second MOS transistor having one end connected to a node of the power supply voltage and the other end connected to the other end of the plurality of dummy cells connected in series; and an input terminal. Is connected to the other end of the second MOS transistor, and a second inverter circuit having an output terminal connected to the gate of the second MOS transistor. The semiconductor memory device according to Motomeko 7. 9. The method according to claim 1, wherein a plurality of sets of the series-connected dummy cells are provided by the number of the row lines, and a gate of each of the series-connected dummy cells is connected to a corresponding row line. The semiconductor memory device according to claim 7, wherein: 10. The semiconductor memory device according to claim 7, wherein each of the plurality of dummy cells stores data corresponding to a low threshold voltage.