JPH10269024A - Disk array control system and extension unit used for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disk array control system capable of inexpensively and easily extending the disk storage device of HDD or the like and flexibly setting the connection number of the disk storage devices. SOLUTION: This system is provided with a main unit 20 provided with a main control part 30, one or plural individual read/write control parts 35 and one or plural extension unit mounting parts for attachably and detachably mounting the extension units 21 and 22 provided with the one or plural individual read/write control parts 35 for extension. By mounting the extension units 21 and 22 to the extension unit mounting parts, the individual read/write control parts 35 are extended by the unit of the extension unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array control system including a plurality of disk storage devices and an expansion unit used for the control system.

[0002]

2. Description of the Related Art In recent years, with the spread of multimedia, a disk array has been used as a storage device capable of reading and writing audiovisual data having a large data size at a high speed. In a disk array, data to be read / written as a unit is distributed and stored in a plurality of disk storage devices, and data is read / written from / to these disk storage devices in parallel to increase the speed.

As shown in FIG. 15, for example, a disk array is composed of a disk array controller 101 and a hard disk storage device (hereinafter abbreviated as HDD) connected thereto.
Group 102. The HDD group 102 is connected to the disk array controller 101 in units of an HDD array 110 including a plurality of HDDs, and includes H
The DDs 111 to 117 are daisy-chained to the SCSI controller 105 of the disk array controller 101 via the SCSI bus 120, and each HDD row 1 is controlled by the central controller 103 of the disk array controller 101.
Reading and writing of data are performed in parallel with respect to. Here, in the conventional disk array, the disk array controller 101 includes an interface 10 for connecting to an external device such as a central controller 103 and a host computer.
4. It has a structure in which the SCSI controller 105 and the like constituted by an LSI are integrally mounted on an electronic board.

[0004]

By the way, in a disk array, it is convenient to be able to add an HDD when the amount of data to be stored increases, but in the conventional disk array control device 101, it is convenient to add an HDD. There is a disadvantage that the structure is basically impossible. More specifically, in the case of a disk array using a SCSI bus, the number of HDDs connected in the HDD row 110 is generally the maximum number of HDDs connected to one SCSI bus (ie,
Since the number of SCSI buses is less than the SCSI bus width by 1 which is the number allocated to the SCSI control unit 105), the SCSI bus must be expanded to add a new HDD. However, the SCSI controller 1 on the board
Since the number of HDDs 05 is fixed, it is impossible to add a SCSI bus. For the purpose of adding HDDs, other than adding another disk array controller to the CPU expansion bus of the central control unit 103 after all. There is no way.

However, in this case, originally, the SCSI control unit 1
Although it is sufficient to add only the part 05 or its peripheral part, unnecessary parts such as the central control unit 103 including an expensive CPU must be added by tying together, and there is a disadvantage that much waste is caused. Further, since another disk array control device is connected to the expansion bus of the CPU to be added, the overhead for data transfer is increased, and the transfer efficiency of the expansion bus is reduced. There is a problem that the data reading speed, which is an essential feature, is reduced. As another method, it is conceivable to provide a spare SCSI control unit 105 on the board of the disk array control device, but in this method,
Not used when additional HDD is not always necessary
There is a disadvantage that the CSI control unit 105 is wasted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a disk array control system which can easily and inexpensively add a disk storage device such as an HDD and which can flexibly set the number of connected disk storage devices, and an expansion system used for the disk array control system. Unit and to provide.

[0007]

SUMMARY OF THE INVENTION According to the present invention, one or a plurality of disk storage devices for distributing and storing data to be read and written as a unit are connected to each other, and the connected disk storage devices are connected. One or a plurality of individual read / write controllers for controlling reading / writing of data to / from the apparatus are connected to the individual read / write controllers, and data is read / written from / to each disk storage device in parallel. The present invention relates to a disk array control system including a main control unit for instructing the individual read / write control units to perform reading control, wherein the main control unit and one or more individual read / write Attachment of one or more extension units for detachably attaching an extension unit having one or more write control units and one or more individual read / write control units for extension Has a main unit with bets,
The individual read / write control unit can be added for each additional unit by mounting the additional unit to the additional unit mounting unit. In this case, a system is constructed in which the number of individual read / write controllers is expanded from the number provided in the main unit by the number provided in the additional unit by mounting the additional unit in the additional unit mounting section. Will be done.

[0010] According to the above configuration, by mounting the additional unit to the additional unit mounting portion of the main unit, the individual read / write control units can be added in units of the number included in the additional unit. That is, when it is desired to add a disk storage device, it is sufficient to mount expansion units in accordance with the number of disk storage devices, so that a system is flexibly constructed according to the number of disk storage devices without waste as in the related art. be able to.

Further, an extension unit mounting portion for attaching another extension unit to the extension unit is provided, and the another extension unit is connected to the main unit via the extension unit to which the extension unit is attached. be able to. By providing the additional unit mounting section in the additional unit, the additional unit and, consequently, the individual read / write control section are added in a chain, and as a result, the number of the additional unit mounting sections of the main unit can be reduced, and as a result, The main unit can be made compact. More specifically, the extension unit can be formed in a plate shape, and another extension unit is mounted on the extension unit mounting portion provided on the plate surface in a stacked form. Can be.
This makes it possible to increase the number of individual read / write controllers without increasing the size of the apparatus.

Next, a buffer for temporarily storing data to be read or written from a disk storage device connected to each individual read / write control unit is provided for each individual read / write control unit. Can be provided. By temporarily storing data in a buffer and then performing reading and writing, for example, the arrival of sectors to read data from each disk storage device and the arrival of sectors to write data to each disk storage device may vary. Also, by adjusting the output timing of data from the buffer, data can be read and written in parallel and at high speed. In this case, it is possible to provide an additional buffer on the main unit side, but the additional unit is provided with a corresponding buffer together with the individual read / write control unit.
By mounting the additional unit on the main unit in the additional unit mounting section, the buffer can be added together with the individual read / write control section.
There is no waste in the number of additional buffers.

The buffer includes first and second RAMs.
And a data input / output mode for those RAMs, a mode for writing data to the first RAM and reading data from the second RAM, and a mode for reading data from the first RAM and writing data to the second RAM. Switching means for switching between the two. By making the buffer a so-called double buffer composed of two RAMs, for example, while reading data from the disk storage device into the first RAM and transferring it to the outside, another data is transferred in parallel to the first RAM. Read into the second RAM,
So-called pipeline processing can be performed, and the data transfer speed can be improved.

A DMA for transferring data stored in the buffer to the disk storage device and transferring data from the disk storage device to the buffer corresponding to each individual read / write control unit. A controller can be provided. As a result, data transfer between the buffer and the disk storage device can be performed at high speed, and the processing load on the main control unit is reduced, so that the data processing efficiency of the entire system can be improved. In this case, it is possible to provide an additional DMA controller on the main unit side, but a corresponding DMA controller is also provided in the additional unit together with the individual read / write controller, and the additional unit is installed in the additional unit mounting section. By mounting the DMA controller together with the individual read / write control unit by mounting it on the main unit, the number of additional DMA controllers is not wasted.

[0013] Next, the individual read / write control unit determines that the plurality of disk storage devices are SCSI (Small Computer System Int.)
erface) SCS daisy chained by bus
It may be an I interface. In the present invention, the following SCSI standards can be adopted. SCSI-1: The SCSI bus is a parallel bus having a data width of 8 bits (+1 parity bit). The data transfer speed is about 5.0 Mbytes / sec at maximum for synchronous transfer.

SCSI-2: Includes the following three types. (1) Fast-SCSI: The SCSI bus has 8 bits (+
Although it is a parallel bus of 1 parity bit), the data transfer speed is about 10.0 Mbytes / sec at maximum for synchronous transfer. (2) 16-bit Wide-SCSI: The SCSI bus is a parallel bus having a data width of 16 bits (+2 parity bits), and the data transfer speed is up to 20.0 in synchronous transfer.
It is on the order of M bytes / sec. (3) 32-bit Wide-SCSI: The SCSI bus is a parallel bus having a data width of 32 bits (+4 parity bits), and the data transfer speed is up to 40.0 in synchronous transfer.
It is on the order of M bytes / sec.

SCSI-3: The following are included as parallel transfer methods. (1) Ultra-SCSI: Also referred to as Fast20. S
The CSI bus is a parallel bus having a data width of 8 bits (+1 parity bit), and has a maximum data transfer speed of about 20.0 Mbytes / sec for synchronous transfer. (2) Ultra-2: Also referred to as Fast40. SCSI
The bus is a parallel bus having a data width of 8 bits (+1 parity bit) and a maximum data transfer speed of 40.000 for synchronous transfer.
It is about 0 Mbytes / sec. (3) Ultra-3: Also referred to as Fast80. SCSI
The bus is a parallel bus having a data width of 8 bits (+1 parity bit) and a maximum data transfer speed of 80.000 for synchronous transfer.
It is about 0 Mbytes / sec.

In the above three parallel transfer methods of SCSI-3, it is possible to use a data width of 16 bits (+2 parity bits) and a transfer speed doubled. On the other hand, as SCSI-3, FiberChannel, IEEE1394,
A standard of a serial transfer method such as SSA (Serial Storage Architecture) can also be used.

The present invention also provides an extension unit used in the disk array control system. The configuration corresponds to a configuration in which only the additional unit is extracted from the above-described disk array control system.

[0018]

Embodiments of the present invention will be described below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing the overall configuration of a disk array configured using a disk array control system according to one embodiment of the present invention. The disk array 1 includes a disk array control device 3 as a disk array control system of the present invention and a hard disk drive (hereinafter, referred to as H) as a disk storage device.
And a group 4 (abbreviated as DD). HD
The D group 4 includes a plurality of HDD rows 17 each including a plurality of HDDs 10 to 16, and each HDD row 17 is daisy-chain connected to the disk array controller 3 by the SCSI bus 6. A main computer 2 is connected to the disk array 1, and a storage unit (ROM (PRO)) storing software, various data, and the like is stored in the main computer 2.
M, EPROM, flash memory, etc.) 5 and a disk storage device, etc.), an extended control unit corresponding to a LAN control board or the like for transmitting data read from the disk array 1 to a terminal device or the like (not shown). 7 is connected.

FIG. 2 is a block diagram showing an electrical configuration of the disk array control device 3. The disk array controller 3 has a main board 20 and an SCS connected thereto.
I control unit extension board (hereinafter simply referred to as extension board) 2
1 and 22. The main board 20 includes a CPU 30,
A central control unit 33 having a ROM 31 and a RAM 32;
SCSI controller 35 as individual read / write controller, D
MA controller (hereinafter referred to as DMAC) 37, RAM 38 as a buffer, error correction unit 40, R
AM 41, an interface unit (hereinafter abbreviated as I / F unit) 42 connected to the main computer 2, and a DMA
C43, 45 and the like. The SCSI control unit 35 has the HDDs 10 to 16 via the SCSI bus 6.
(FIG. 1) are connected, and are usually composed of LSIs called SCSI controllers.
Plays a role in controlling the reading and writing of data to

Here, in the SCSI standard of the parallel transfer system, a SCSI that can be connected to one SCSI bus is used.
Since the number of compatible devices is limited to the bus bit width of the SCSI bus, the number of HDDs that can be connected to the SCSI control unit 35 depends on the bus bit width of the SCSI bus.
This is up to a number obtained by subtracting 1, which is the allocation of the SI control unit 35. In the present embodiment, a Fast-SCSI bus is used as a SCSI bus for connecting the HDD row 17, and the number of SCSI-compatible devices connected in a daisy chain is eight (that is, the SCSI control unit 35 + the HDD 10
To 16), but it is of course possible to adopt another SCSI standard. For example, 16-bit Wide-SC
For SI, up to 16 units, 32-bit Wide-SCS
In the case of I, up to 32 units can be connected. Note that SC
In order to prevent the occurrence of noise due to signal reflection at the end of the SI bus 6, the terminal HD connected in a daisy chain
A terminal resistor (not shown) called a terminator is attached to D16.

The RAM 38 temporarily stores data read from the HDD or data to be written to the HDD. As shown in FIG.
Two buffer memories (RAM) b composed of AM etc.
It is configured as a double buffer having uf0 and buf1. The RAM 38 is provided with a mode changeover switch 38a as a changeover means. The changeover switch 38a sets a data input / output mode for the RAM 38, a mode for writing data to buf0, a mode for reading data from buf1, and a mode for reading data from buf0. Read bu
The mode is switched between a mode for writing data to f1. This switching control is executed according to an instruction from the CPU 30. This enables so-called pipeline processing in which data is sent from one buffer memory while data is being written to the other buffer memory.
The DMAC 37 is formed of, for example, a dual address type DMA controller, and plays a role of performing data transfer between the RAM 38 and the SCSI control unit 35 by direct memory access according to an instruction from the CPU 30.

The DMAC 45 controls data transfer between the RAM 41 and the RAM 38 in accordance with an instruction from the CPU 30, and the transferred data is transferred through an error correction unit 40, which will be described in detail later. R
The AM 41 is for increasing the data transfer efficiency with other devices connected to the main computer 2 and the extended control unit 7. The I / F unit 42 communicates commands between the disk array control device 3 and the main computer 2 and the RAM 41
It plays a role in mediating the transmission and reception of data between the device and another device connected to the extension control unit 7. The DMAC 43
This is for controlling data transfer between the I / F unit 42 and the RAM 41 according to an instruction from the PU 30. A control program is stored in the ROM 31 of the central control unit 33. The CPU 30 uses the RAM 32 as a work area and gives instructions to the DMACs 37, 43, 45, etc. based on the control program, thereby controlling each HDD of the HDD group 4
It controls the overall operation of the disk array 1 such as access processing to the disk array 1.

Next, the SCSI boards 35, DMACs 37, and RAs are added to the extension boards 21 and 22, respectively.
A plurality of M38 sets (four in this embodiment) are provided, and these are detachably connected to the main board 20 via connectors, which will be described later, respectively.

FIG. 8 schematically shows the appearance of the disk array controller 3. The disk array controller 3
It comprises a main board 20 and additional boards 21 and 22 which are connected to the main board 20 in a stacked manner. The main board 20 has a card edge portion 20a for attaching itself to the board of the main computer 2, a SCSI connector C for connecting the SCSI bus 6, a connector 20b for connecting an extension board 21, and the like. ing. The extension boards 21 and 22 are provided with SCSI bus 6 (SCS
I1 to SCSI8), connectors 21b and 22a for connecting itself to the main board 20 or another extension board, and connectors 21a and 22b for connecting and adding another extension board. Etc. Then, the extension boards 21 and 22 are connected to the main board 20 by the connectors 20b, 21b, and 2 respectively.
The extension boards 21 and 22 are successively connected to the main board 20 by sequentially connecting them in a laminated manner via 1a and 22a. In this embodiment, a set of the main board 20 and the extension board 21 connected thereto constitutes a main unit, and the extension board 22 connected to the extension board 21 constitutes an extension unit.

The data stored in the disk array 1 is to be read and written as a unit (hereinafter, also referred to as original data), divided into a plurality of data blocks, and distributed and stored in each HDD. I have. Then, the speed of data input / output is improved by reading and writing the original data in parallel with the plurality of HDDs in units of the data blocks. In a disk array, in order to improve the reliability of data, the divided data blocks are stored by adding parity data as error correction information described later, and a part of the data on the disk is lost. Even if you do, you can restore the original data.

In the disk array 1, the HD
Some of the plurality of HDDs constituting the D group 4 are dedicated HDDs (correction HDDs) for storing error correction information (parity data in this embodiment) created in advance based on the original data.
D: Parity data is stored in this embodiment, which is referred to as a parity disk). If data blocks cannot be read from any one of the data blocks stored in another HDD, A process of restoring a lost data block from the parity data of the parity disk and a data block from another HDD that has been successfully read is enabled. In this embodiment, the parity disk is the HDD row 17 connected to the SCSI bus 0.

FIG. 3 is a block diagram showing the internal structure of the error correction unit 40. That is, the error correction unit 40 is configured by a bidirectional parallel input / output device, and is the same as the input data holding / output data switching unit 50 connected to the RAM 41 side of FIG. An input data holding / output data switching unit 52 which is constituted by a bidirectional parallel input / output device and is connected to the HDD group 4 via the B bus, and both switching units 50 and 5
And a parity generator 51 provided between the two. When writing data to the HDD group 4, the parity generator 51 performs an exclusive OR operation on the write data to each HDD transferred from the input data holding / output data switching unit 50 via the C bus. While the parity data is generated by
The input data holding / output data switching unit 52 performs an exclusive OR operation on the read data transferred from each HDD transferred via the C bus to perform error correction or generate rebuilt data.

Here, the input data holding / output data switching unit 50 sets the number of input / output bits on the A bus side to N, and sets the maximum connection number of extension boards (21, 22 etc.) to m (N = N in this embodiment).
4, m = 2), the number of input / output bits on the C bus side is set to N × m bits, and the bits of each C bus are assigned to each SCSI controller on the main board 20 and the extension boards 21 and 22, respectively. 35 corresponds one-to-one. And the main board 20
According to an instruction from the CPU 30 of the central control unit 33, the input data holding / output data switching unit 50
Switching is performed according to the connection states of b, 21b, 21a and 22a, 22b (FIG. 8) so that data input / output is performed only to the C bus to which the extension board is connected. When m ≧ 2, when writing data to the HDD group 4, input data from the A bus side is latched in N-bit units, and the latched data is sequentially switched to the corresponding C bus side and output ( For example, in the present embodiment, the output to the C buses 1, 3, 5, 7 and the output to the C buses 2, 4, 6, 8 are alternately switched. Also, when reading data from the HDD group 4, data from the C bus side is N ×
Latch in m-bit units and store the latched data in A
The data is sequentially output to the bus side while being separated in units of N bits (for example, the same as the output from the C buses 1, 2, 3, and 4,
8 is alternately switched).

As a specific method for the CPU 30 to know the connection state of the extension board, for example, a plurality of DIP switches for setting the number of boards are provided, and the combination of the operation state of each DIP switch and the number of boards to be connected are determined. And a method of determining the connection state of the extension board based on the setting state of the dip switch. on the other hand,
The RAM 38, the DMAC 37, the SCSI controller 35, and the like reserve an address to be expanded and expanded, and the CPU 30 scans and recognizes the corresponding address when the power is turned on, etc., so that the number of expansion boards can be known. May be used.

On the other hand, the input data holding / output data switching section 52 has a C bus side input / output bit number of N × m + 1 bits (input data holding / output data switching corresponding to the input / output bits from the parity generator 51). The number of input / output bits on the B bus side is also N × m +
It is one bit. Then, in response to an instruction from the CPU 30, the input data holding / output data switching unit 50 transmits data only to the C bus to which the extension board is connected, according to the connection state of the connectors 20b, 21b, 21a and 22a, 22b. Switch so that input and output are performed. B0 of the B bus is the SCS of the main board 20.
This is for mediating data with the parity disk connected to the I control unit 35.

Here, when the number of connected expansion boards increases, the number of input / output bits on the C bus side also changes accordingly. This means that the number of data bits to be parity-operated changes. The following two methods are conceivable as methods for dealing with this. One is a method in which a large number of inputs of a circuit for obtaining an exclusive OR in anticipation of mounting of an additional board is taken from the beginning. In this case, a pull-up resistor R is attached to an input terminal of an EXCLUSIVE-OR circuit (hereinafter, referred to as an EX-OR circuit) 206 for performing an exclusive OR operation as shown in FIG. A high level is always input to the input terminal. As another method, the number of inputs of the exclusive-OR is kept constant regardless of the number of disks, and the exclusive-OR operation uses the intermediate result as a buffer memory provided separately. A method of sequentially performing the processing while storing the information in the storage area can be exemplified.
FIG. 14 shows a circuit example for implementing this.

FIG. 14 is a block diagram showing an example of the internal structure of the error correction circuit 201 which is a main part of the parity generator 51. The error correction circuit 201 includes a selector 202 connected to the C bus side of the input data holding / output data switching unit 50, a selector 203 connected to the C bus side of the input data holding / output data switching unit 52, an exclusive operation , An EXCLUSIVE-OR circuit (hereinafter referred to as an EX-OR circuit) 206, a selector 207, three-state buffers 208 and 209, and the like.
01 is connected to an error correction buffer 200.

The error correction buffer 200 is for storing an intermediate result of the parity operation, and is provided via the error correction data bus 210 to the error correction circuit 20.
1 and outputs an intermediate result (or a final result) stored in the error correction circuit 201 to the error correction circuit 201 itself. The error correction circuit 201 compares the intermediate result from the error correction buffer 200 with the bus 21.
An error correction operation is performed on data from 1 (hereinafter, data or signals flowing through the bus may be indicated by the same reference numerals as the bus), and the result is returned to the error correction buffer 200. In this case, the memory in the error correction buffer 200 writes a new value immediately after performing the read, that is, a so-called READ MODIFY WRITE.
It can be seen that it is working. Here, at the start of the error correction operation, a mechanism for so-called initialization for invalidating the operation result stored in the error correction buffer 200 at the start is required. In this case, in the present embodiment, a method is adopted in which only the first input data in the error correction circuit 201 is stored in the error correction buffer 200 as it is without performing the error correction operation, thereby performing initialization. The main component is a selector 207 (described later) in the error correction circuit 201 as described later.
Do

The EX-OR circuit 206 receives data 211 from the main computer 2 selected by the selector 202 and feedback data (parity data) 214 from the error correction buffer 200 in the write mode.
In the read and rebuild modes, the selector 203
The data 211 from each HDD row 17 and the feedback data (restored data) 214 from the error correction buffer 200 selected in the steps (1) and (2) are input, and the exclusive use of the data 211 and 214 in each mode is performed. A parity operation (that is, an error correction operation) is performed by taking a logical sum, and the result is stored in an error correction buffer 2.
Output to 00. The selector 207 described above is provided in the middle of the input path from the error correction buffer 200 to the EX-OR circuit 206. The selector 207 invalidates the feedback of the previous operation result stored in the error correction buffer 200 at the start of the parity operation, and substitutes the EX-OR circuit 20
6 serves as an arithmetic unit initial operation control means for outputting the data input first to the error correction buffer 200 as it is. For example, when even parity is adopted, the selector 207 receives an instruction from the CPU 30 at the start of the parity operation, and thereby selects the EX-O.
The input data 215 to the error correction buffer 200 side to the R circuit 206 is fixed to 0. In the EX-OR operation,
When one input is 0, the other data is output as it is.

The data calculated by the EX-OR circuit 206 is distributed to the error correction buffer 200. The error correction buffer 200 is for storing an intermediate result of the parity operation as described above, and its input is received from the EX-OR circuit 206 and its output is
Selector 207 and three-state buffers 208 and 2
09. Three-state buffer 208
Is enabled by an instruction from the CPU 30 and outputs the restored data 214 to the A bus side via the bus 217 in the read mode. Also, the three-state buffer 209 is enabled according to an instruction from the CPU 30, and the parity data 214 in the write mode.
In the rebuild mode, the restored data 214 is output to the B bus via the bus 216. It is also possible to simultaneously rebuild the data and output (ie, read) the rebuilt data to the outside. In this case, both the three-state buffers 208 and 209 are enabled. The rebuild data is output to the B bus side for writing and to the A bus side for reading.

The operation of the error correction circuit 201 will be described below. First, the operation of reading data from the disk array, that is, the operation in the read mode will be described. The CPU 30 processes the data in the order in which the data can be read from the HDD of each SCSI bus in accordance with the following procedure. First, the selector 203 is instructed to select the bus from which data has been read, and the selector 207 is instructed to select “0”. As a result, the data on the bus is transferred to the error correction buffer 20.
0 is stored. Then, the CPU 30 selects the next readable bus, and thereafter repeats this processing. However, in the second and subsequent data transfers, the selector 207 is instructed to select the data bus 214. As a result, the EX-OR circuit 206 has the error correction buffer 2
00 will be transferred. The error correction circuit 201 shown in FIG.
It is assumed that only four of the B bus 0 to the B bus 3 are connected to the selector 203.

Assuming that the exclusive OR operation is performed in the order of B bus 0, B bus 1, and B bus 2, at the end of the second data transfer, the data of B bus 0 and the data of B bus 1 are mutually exclusive. The result of the logical OR operation (that is, the intermediate operation result) is stored in the error correction buffer 200, and by executing the third data transfer, the exclusive OR of the intermediate operation result and the data of the B bus 2 is obtained. Calculation is EX-OR circuit 2
06. This calculation result is the same as the data on the B bus 3 according to the principle of the parity calculation.
Therefore, at the time of the third data transfer, the data on the B bus 3 is restored in the error correction buffer 200. Then, when the three-state buffer 208 is driven to perform the fourth transfer, the restored data 214 (data of the B bus 3) flows from the bus 217.

Next, the operation for writing data to the disk array, that is, the operation in the write mode will be described. First, the CPU 30 selects data to be stored on the B bus 1 from data from the main computer by the selector 202 and reads out the data on the bus 211. Here, since the selector 207 selects “0” only at the time of the first data transfer in the same manner as described above, this data is stored in the error correction buffer 200 as it is. Further, the CPU 30 reads data to be stored in the B bus 2. As a result, the data on the B bus 1 and the B data by the EX-OR circuit 206 are stored in the error correction buffer 200.
The result of the exclusive OR operation with the data on the bus 2 is stored.

Further, data 211 to be stored in the B bus 3 is read from the main computer 2 by the CPU 30, and an exclusive OR operation of the data 211 and the feedback data 214 is performed by the EX-OR circuit 206. The result is written back to the error correction buffer 200. This is the exclusive OR of the data of the B bus 1, the B bus 2 and the B bus 3, that is, the parity data. Then, the three-state buffer 209 stores
The parity data 214 is transferred to the bus 21 according to the instruction of the PU 30.
6 and output.

Finally, the rebuild operation will be described. Here, a case where the HDD of the B bus 3 is replaced will be described as an example. First, the CPU 30 reads the data-read SCSI
The following processing is performed in order from the bus. First, the selector 203
Selects the bus (referred to as B bus 1), and the selector 20
7 selects "0". After this, the data of the bus is stored in the error correction buffer 200.
The CPU 30 performs the processing of the next SCSI bus similarly. However, after the second time, the selector 207
To select the feedback data 214.

As in the case of the read mode, the B bus 0
(Parity disk), the exclusive OR operation is performed in the order of the B bus 1 and the B bus 2}, and when the third data transfer is performed, the output of the EX-OR circuit 206 becomes B Data that previously existed on bus 3 (restored data)
Becomes The restored data is stored in an error correction buffer 200.
And is output through the bus 216 in the fourth transfer. Here, whether or not to output the data to the main computer 2 is instructed by the CPU 30 depending on whether or not there is a read request from the main computer 2 during the rebuild operation. When there is a read request from the main computer 2, the three-state buffer 2
When 08 is driven, the data is output to the main computer 2 via the bus 217. On the other hand, when there is no read request from the main computer 2, only the rebuild process is performed, and no data is output to the main computer 2 at this time.

Note that the CPU 30 controls each selector 202,
203, 207 and three-state buffers 208, 2
Instead of providing a signal directly to 09, a signal may be provided via the mode instruction port 220.

The operation of reading / writing data from / to the disk array 1 will be described below. First, the main computer 2
Alternatively, regarding the data write operation from the extension control unit 7 to the disk array control device 3, the main computer 2 or the extension control unit 7 transmits a data write request to the DMAC 43 through the I / F unit 42. The DMAC 43 is an I / F unit 42
Writes data in the RAM 41 in response to a request from
In the present embodiment, for convenience of explanation, the bus connecting the main computer 2, the I / F unit 42, the RAM 41, and the error correction unit 40 has 32 bits (8 bits × 4).
It is assumed that one bus shown in the figure has 8 bits.

The data written in the RAM 41 is DM
Read by the AC 45 and the error correction unit 40
Is input to FIG. 3 shows the details. That is, the data input to the error correction unit 40 is latched by the input data holding / output data switching unit 50. here,
When the extension board 22 is mounted on the main board 20,
That is, as shown in FIG.
The number of SCSI buses 6 is 8 (SCSI1 to SCSI
8) +1 (SCSI bus 0: parity disk), as shown in FIG.
Of the C bus 1 to 4 at the rising edge of the clock A
Is output to the C buses 5 to 8 at the rising edge of the clock C. The clock is generated from the clock 5 shown in FIG.
0a.

The parity generator 51 has C buses 1 to
8 and outputs the result to the C bus 0. The data on the C buses 0 to 8 are input to the input data holding / output data switching unit 52 and can be output to an arbitrary B bus. In the present embodiment, for convenience of explanation, data on the C buses 0 to 8 are shown to be output to the B buses 0 to 8. Due to the characteristics of the disk array, ie, distributed storage of data, the data on the C bus is effective on the C bus only when all the data blocks of the original data are aligned, that is, in FIG. Therefore, data is written to the RAM 38 at the falling edge of the clock D.

On the other hand, in FIG. 2, when only the extension board 21 is connected to the main board 20, that is, when the system configuration is 4 + 1, as shown in FIG. Latch (clock A) at the rising edge of the clock, and write to RAM 38 at the falling edge of the next clock (clock B). The data written in the RAM 38 is read by the DAMC 37,
The data is transferred to the HDD group 4 through the SI control unit 35 and written to the corresponding HDD. FIG. 4 (b)
The output of the B bus 5 to the B bus 8 is not output because the extension board 22 is not connected.

Next, the operation of reading data will be described with reference to FIG. That is, the SCSI control unit 3
5, the data read from the HDD group 4 via the DM
The data is written to the RAM 38 by the AC 37. Meanwhile, DM
The AC 45 writes data from the RAM 38 onto the B bus. The written data is latched by the input data holding / output data switching unit 52 and output on the C bus. The parity data calculated at the time of writing is output on the C bus 0 to which the parity disk is connected. Then, the parity generator 51 calculates the value on the C bus 0 and C
The presence or absence of a parity error is checked by comparing the data of the buses 1 to 8 with the exclusive OR value. If there is a parity error, the data of the disk having the error is restored (rebuilt) from the data of another disk including the parity disk. If the reading of the data of all the systems is normal, the rebuild data is not generated. In this embodiment, the B bus 0
It is assumed that there is parity data above, but if the system for writing parity data is changed at the time of writing, it is necessary to match the system at the time of reading.

The value of the C bus is also input to the input data holding / output data switching unit 50. As shown in FIG. 6A, when the system configuration is 8 + 1, the data of the C buses 1 to 4 are supplied to the A bus at the rise of the clock A, and the data of the C bus 5 to 8 are supplied to the A bus at the rise of the clock C. Data is output. On the other hand, as shown in FIG.
In the case of the system configuration of 1, the data of the C buses 1 to 4 are output on the A bus at the rising edge of the next clock.

Next, a description will be given of an operation in a case where an HDD on a certain bus fails and data cannot be read, and the failed data is restored (rebuilt) from the parity data and data of another system. For example, B bus 8 (SCS
When the HDD on the I bus 8) fails, the data on the B buses 0 to 7 read from the HDD is latched by the input data holding / output data switching unit 52 as shown in FIG. The data on the C buses 1 to 7 are output as they are, as in the read operation. However, the data on the C bus 8 is subjected to an exclusive OR operation on the data on the C buses 0 to 7 by the parity generator 51, so that the rebuild data is obtained. Is restored on the C bus R. This is output as data on the C bus 8 onto the A bus.

Next, a description will be given of the operation when replacing the HDD on the failed SCSI bus and restoring data. That is, as shown in FIG. 7, in this case as well, the data on the C buses 0 to 7 is
Performs the exclusive OR operation, the restored data is output on the C bus R. Here, the data is once input to the input data holding / output data switching unit 50 and then output to the C bus 8, and the data is output to the B bus 8 at substantially the same timing. As shown in FIG.
In a 1-bit system, data can be restored by writing the restored data to the RAM 38 at the falling edge of the clock D.

In the embodiment described above, only the two boards of the extension boards 21 and 22 are mounted on the main board 20. However, a configuration in which no extension board is connected to the main board 20, or only one board Form to connect,
Further, as in the case of connecting three or more boards, the number of additional boards connected to the main board 20 can be increased or decreased according to the required number of HDDs constituting the disk array 1. Here, if at least one SCSI connector C is provided, the main board 20 daisy chain-connects a plurality of HDDs to one SCSI bus by using one SCSI bus.
It is possible to construct a disk array with these HDDs as each lane of the array. In this case, the main board 20
Are the main units referred to in the present invention as extension boards 21 and 22.
Constitutes an additional unit.

In the above embodiment, only one SCSI connector C is provided on the main board 20 as shown in FIG. 8, but five SCSI connectors C are provided on the main board 20 as shown in FIG. It is also possible to provide. in this case,
The main board 20 is the main unit, and the extension boards 21, 22,.
... can be regarded as an extension unit. FIG.
As shown in (1), the configuration may be such that five SCSI connectors C are provided on the extension board 21 without providing the SCSI connectors C on the main board 20. Further, a configuration is also possible in which a plurality of connectors 20b (FIG. 8) are provided on the main board 20, and additional boards 21, 22 # are respectively added to them in parallel. In this case, from the extension boards 21 and 22
The connector 21b or 22b may be omitted.

Next, in the above embodiment, the RAM 38 has a double buffer configuration. However, if it is desired to configure the RAM 38 inexpensively, a simple single buffer configuration may be used. In this case, the read / write processing and the improvement of the rebuild speed by the pipeline processing cannot be expected, but the effect of the improvement of the processing speed by the hardware such as the parity calculation means and the rebuild path is similarly achieved.

There is also a method of using a dual port memory as shown in FIG. 12 instead of using the RAM 38 as a double buffer. In this case, the RAM 64 has two input / output buses 64a and 64b, and these buses 64a and 64b.
RAM 64e provided in common with 4b and its RA
M64e, two input / output buses 64a, 64b
And a bus switch 64c as switching means for selectively connecting any one of the above. An arbiter 64d is connected to the bus switch 64c, and a read / write signal for instructing input and output of data to and from the buses 64a and 64b is input to the arbiter 64d.

The arbiter 64d has a bus switch 64c so that the RAM 64e is connected to one of the buses 64a and 64b to which the read / write signal has arrived earlier.
Is switched. In this case, the arbiter 64d returns a BUSY signal (or a WAIT signal) to the second-arriving bus, and switches the bus switch 64c to the second-arriving bus as soon as access to the first-arriving bus is completed. This allows
For example, if the access speeds of the buses 64a and 64b are the same, both buses 64a and 64b access the RAM 64e alternately. If the response speed of the RAM 64e is sufficiently fast, it is possible to respond to the access speed request of the buses 64a and 64b on both sides even if the waiting time is included. As a result, the writing of data to the RAM 64 and the data from the RAM 64 , And can be executed in parallel apparently. Incidentally, as a dual port memory, two input / output buses 64
Both a and 64b are random access types, one is random access, the other is sequential access (for example, VRAM), and both are sequential access (for example, FIFO). Is also good.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an example of a disk array configured using the desk array control system of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of the disk array control device.

FIG. 3 is a block diagram showing an operation during data writing.

FIG. 4 is a timing chart thereof.

FIG. 5 is a block diagram showing an operation at the time of data reading.

FIG. 6 is a timing chart thereof.

FIG. 7 is a block diagram showing an operation at the time of reading data and generating rebuilt data when there is a failed HDD;

FIG. 8 is an external view showing an example of a disk array control device.

FIG. 9 is an external view showing a modified example thereof.

FIG. 10 is an external view showing another modified example.

FIG. 11 is a block diagram showing an example in which a buffer is configured by a dual port memory.

FIG. 12 is a conceptual diagram showing a modified example of a buffer.

FIG. 13 is a block diagram showing a main part of a configuration example of a parity generator.

FIG. 14 is a block diagram showing a main part of another configuration example.

FIG. 15 is a block diagram of a conventional disk array device.

[Explanation of symbols]

Reference Signs List 1 disk array 4 hard disk group 10-16 hard disk storage device (disk storage device) 20 main board (main unit) 21 SCSI control unit expansion board (main unit, expansion unit) 22 SCSI control unit expansion board (expansion unit) 20b, 21a , 21b, 22a, 22b Connector (expansion unit mounting section) 30 CPU (main control section) 35 SCSI control section (individual read / write control section) 37 DMA controller 38 RAM (buffer)

Claims (11)

[Claims] A plurality of disk storage devices for storing data to be read and written as a group in a distributed manner are respectively connected to a plurality of disk storage devices, and a plurality of disk storage devices for reading and writing data to and from the connected disk storage devices, respectively. The individual read / write control unit is connected to the individual read / write control unit, and the individual read / write control unit is configured to read / write the data in parallel with respect to each of the disk storage devices. A disk array control system comprising: a main control unit that instructs the unit to perform the reading control; the main control unit; one or more individual read / write control units; A main unit including one or a plurality of additional unit mounting units for detachably mounting an additional unit having one or more embedded control units. By mounting the extension unit to knit mounting portion, the disk array control system, characterized in that the individual reading and writing control unit is capable expansion in the expansion unit basis. 2. The disk array control system according to claim 1, wherein said additional unit is mounted on said additional unit mounting section. 3. The extension unit is provided with an extension unit mounting portion for mounting another extension unit, and the another extension unit is connected to the main unit via the extension unit to which the extension unit is mounted. 3. A connection according to claim 1 or claim 2.
3. The disk array control system according to 1. 4. The extension unit is formed in a plate shape, and the extension unit mounting portion provided on the plate surface is
4. The disk array control system according to claim 3, wherein said another extension unit is mounted in a stacked form. 5. A method for temporarily storing data read from the disk storage device connected to the individual read / write control unit or data written to the disk storage device corresponding to each of the individual read / write control units. A buffer for storing is provided, and the extension unit is also provided with the buffer corresponding to the individual read / write control unit, and the extension unit is attached to the main unit at the extension unit attachment unit. 5. The disk array control system according to claim 1, wherein the buffer is added together with the individual read / write control unit. 6. The buffer according to claim 1, wherein said buffer is a first and a second RAM.
And a data input / output mode for those RAMs, a mode for writing data to the first RAM and reading data from the second RAM, and a mode for reading data from the first RAM and reading data to the second RAM. 6. The disk array control system according to claim 5, further comprising switching means for switching between a writing mode and a writing mode. 7. Transferring data stored in the buffer to the disk storage device and transferring data from the disk storage device to the buffer corresponding to each of the individual read / write control units. DMA controller is provided for the extension unit, and the DMA controller corresponding to the individual read / write control unit is also provided in the extension unit, and the extension unit is connected to the main unit in the extension unit mounting unit. By mounting, the individual reading and
7. The disk array control system according to claim 5, wherein the DMA controller is additionally provided together with the write control unit. 8. The disk array control system according to claim 1, wherein said individual read / write control unit is a SCSI interface in which a plurality of said disk storage devices are daisy-chain connected by a SCSI bus. . 9. A plurality of individual read / write units each connected to a disk storage device that stores data to be read / written in a distributed manner and that controls reading of data to / from the connected disk storage device. The write control unit and the individual read / write control units are connected, and the individual read / write control units are connected to the respective disk storage devices so that the data is read / written in parallel. An additional unit used in a disk array control system including a main control unit that instructs the reading control, wherein the main control unit, one or more individual read / write control units, A main unit having a plurality of additional unit mounting sections is configured to be detachable from the additional unit mounting section, and an individual read / write control section for expansion is provided.
A plurality of individual read / write control units that are mounted on the expansion unit mounting unit and are installed in the main unit by the number of units mounted on the main unit. 10. Corresponding to each of said individual read / write controllers, data read from said disk storage device connected to said individual read / write controller or data written to said disk storage device is temporarily stored. 10. The expansion unit according to claim 9, further comprising a buffer for storing. 11. Transferring data stored in the buffer to the disk storage device and transferring data from the disk storage device to the buffer corresponding to each of the individual read / write control units. The expansion unit according to claim 10, further comprising a DMA controller for the expansion unit.