JPH10260812A - Graphics processor incorporated with memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a CPU to access a graphics processor having an integrated memory built in the same as in the conventional memory. SOLUTION: This processor is provided with a mode setting circuit 600 which sets an arithmetic content in a pixel arithmetic circuit 400 and an address management table 700 that preserves the processing content in the circuit 400 and decides whether an access to memory 500 needs arithmetic processing in the circuit 400. Thus, a CPU 910 maintains to access a main storage 510 like conventional memory when it accesses the storage 510 and also performs pixel arithmetic processing that takes a time in the circuit 400 that is shared by a plotting circuit 30 when the CPU 910 performs plotting processing with software.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic processing apparatus for generating and displaying character and graphic data, and more particularly to a frame buffer for storing pixel data for display.
The present invention relates to a graphic processing device which is configured by an integrated memory system in which a main memory for storing a program and data for operating a CPU is integrated in a memory device, and has a built-in memory in a graphics processor.

[0002]

2. Description of the Related Art A conventional graphic processing apparatus constructed by an integrated memory system is disclosed in Japanese Patent Application Laid-Open No. 4-84192 by providing means for buffering data transferred between a memory and a processor. A method is described in which a memory is prevented from being occupied by an access, and a vacant memory access can be used as a display access.

An LS which incorporates some functions of a conventional graphics controller into an image memory
An example of I is described in "Development of Memory for Three-Dimensional Graphics by Mitsubishi and Sun of the United States" (Nikkei Electronics, Aug. 22, 1994, pp. 15-16).
In this LSI, the functions of the graphics processor are partially separated and incorporated in a frame buffer memory.

[0004]

Conventionally, when a graphics processor and a memory are configured by separate LSIs, the graphics processor and the memory can be freely selected, so that the graphics processor and the memory are required when configuring the graphic processing apparatus. Any combination can be selected by various functions. However, when a graphics processing device is configured using a graphics processor having a built-in memory, and the built-in memory is used as an integrated memory, the combination of the graphics processor and the memory is fixed. In order to realize a drawing function that is not built in the processor, it is necessary to perform processing by software on the CPU. However, generally, it takes a very long time to perform a drawing process by software, which eventually causes a decrease in performance of the entire graphic processing apparatus.

The above-mentioned prior art does not mention a solution to this problem.

A first object of the present invention is to provide a graphic processing apparatus using a graphics processor having a built-in memory and using the built-in memory as an integrated memory.
To reduce the CPU overhead when implementing a drawing function not included in the graphics processor by software on the CPU while maintaining the same access to the main memory as the conventional memory when the CPU accesses the main memory. It is. A second object of the present invention is to provide a graphic processing apparatus which uses a graphics processor having a built-in memory and uses the built-in memory as an integrated memory when the CPU accesses the memory built in the graphics processor. Another object is to reduce the memory access overhead of the CPU according to the type of data to be accessed.

[0007]

In order to achieve the above object, according to the present invention, a display control circuit for controlling display data for each pixel, and at least a calculation result created by an external CPU and the display data are stored. A display control circuit and a memory are mounted on the same semiconductor substrate, and an access procedure for accessing a calculation result and an access procedure for accessing the display data are different when the CPU accesses the memory. It is characterized by:

In order to achieve the above object, according to the present invention, a drawing circuit for performing a pixel generation process, a pixel calculation circuit for performing a pixel calculation process on a pixel generation result of the drawing circuit, and a pixel control circuit are controlled. A pixel calculation control circuit for controlling the display data, a display control circuit for controlling display data for each pixel,
A memory for storing an operation result of the external CPU, the pixel generation result, and the display data, wherein the drawing circuit, the pixel operation circuit, the pixel operation control circuit, the display control circuit, and the memory are mounted on the same semiconductor substrate The CPU and the drawing circuit output control data to the pixel operation control circuit, and the pixel operation control circuit controls the pixel operation circuit based on the control data.

In order to achieve the above object, according to the present invention, there is provided a CPU for executing arithmetic processing, a drawing circuit for executing pixel generation processing, and a pixel for executing pixel calculation processing on a pixel generation result of the drawing circuit. An arithmetic circuit, a pixel arithmetic control circuit for controlling the pixel arithmetic circuit, a display control circuit for controlling display data for each pixel, and a memory for storing arithmetic results, pixel generation results, and display data of the CPU. , CP
U, the drawing circuit, the pixel operation circuit, the pixel operation control circuit, the display control circuit, and the memory are mounted on the same semiconductor substrate,
The CPU and the drawing circuit output control data to the pixel operation control circuit, and the pixel operation control circuit controls the pixel operation circuit based on the control data.

[0010]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an overall configuration diagram of a first embodiment of the present invention. In FIG. 1, 100 is a graphics processor, 200 is a CPU I / F, 300 is a drawing circuit, 31
0 is a display circuit, 320 is an arbitration circuit, 330 is an internal bus,
340 is a transfer path, 400 is a pixel operation circuit, and 410 and 4
11 is a selector, 500 is a memory, 510 is a main memory, 5
20 is drawing data, 530 is a drawing work, 540 is a frame buffer, 600 is a mode setting circuit, 700 is an address management table, 900 is an external bus, 910 is C
PU, 920 is a TV tuner, 930 is CDROM, 9
40 is an I / O controller and 950 is a CRT.

In FIG. 1, a memory 500 includes a main storage 510 including programs, data, and a work area necessary for the operation of the CPU 910, an original texture pattern for performing texture mapping, a display list of the drawing circuit 300, and the like. , A drawing work 530 including a work area for operating the drawing circuit 300, and a frame buffer 540 for storing display data to be displayed on the CRT 950. C
When the PU 910 reads and accesses the main memory 510, the CPU
Reference numeral 910 outputs an address to be accessed to the CPU I / F 200.

The CPU I / F 200 outputs a bus right acquisition request to the arbitration circuit 320 and, after receiving the bus right of the internal bus 330 from the arbitration circuit 320,
0, an address is output to the memory 500 via the transfer path 340, data output from the memory 500 is read via the transfer path 340 and the internal bus 330, and the data is output to the CPU 910. When the CPU 910 accesses the main memory 510 by writing, the CPU 910 outputs an address and data to be accessed to the CPU I / F 200.

The CPU I / F 200 sends the signal from the arbitration circuit 320 to the internal bus 330 in the same manner as in the read access.
After acquiring the bus right, the address and data are output to the memory 500 via the internal bus 330 and the transfer path 340.
When the CPU 910 performs drawing processing by software and writes a graphic pattern to the frame buffer 540, the CPU 9
Step 10 is performed by software until pixel data is generated. Subsequent pixel calculation processing such as Z buffer processing and alpha blending processing is performed by the pixel calculation circuit 400. The setting of the processing content (type of arithmetic operation, type of logical operation, data amount, etc.) performed by the pixel operation circuit 400 is determined by the CPU I / F 20.
0, by registering in the address management table 700 through the mode setting circuit 600. After registering the processing content in the address management table 700, the CPU 910 outputs an address and data to the CPU I / F 200 to perform write access to the frame buffer 540.
The I / F 200 outputs a bus right acquisition request to the arbitration circuit 320. After the bus arbitration, the arbitration circuit 320 executes the CPUI /
The use permission of the internal bus 330 is notified to F200. At the same time, the arbitration circuit 320 notifies the address management table 700 of which circuit has acquired the bus right by the bus right acquisition circuit notification signal 321. When acquiring the bus right from the arbitration circuit 320, the CPU I / F 200 outputs an address and data to the internal bus 330. At this time, the address management table 700 fetches the address output to the internal bus 330, and determines from the fetched address and the bus right acquisition circuit notification signal 321 whether or not the access requires processing in the pixel operation circuit 400. If the address management table 700 determines that the access is to perform processing in the pixel operation circuit 400, the operation content in the pixel operation circuit 400 is output to the pixel operation circuit 400 as the processing content 710, and the switching signal 711 is output to the selector 410, 411,
The address and data output to the internal bus 330 are input to the pixel operation circuit 400, and the operation result of the pixel operation circuit 400 is output to the memory 500. The pixel operation circuit 400 performs a pixel operation process according to the processing content 710, and outputs a processing result to the memory 500. Drawing circuit 3
When 00 accesses the drawing data 520, the drawing circuit 300 outputs a bus right acquisition request to the arbitration circuit 320. After receiving the bus right of the internal bus 330 from the arbitration circuit 320, the drawing circuit 300 outputs an address to the memory 500 via the internal bus 330 and the transfer path 340, and transfers the data output from the memory 500 to the transfer path 340, The data is read via the internal bus 330. When the drawing circuit 300 performs a drawing process and writes a graphic pattern to the frame buffer 540, the drawing circuit 30
0 performs up to creation of pixel data. Subsequent pixel calculation processing such as Z buffer processing and alpha blending processing is performed by the pixel calculation circuit 400. The setting of the processing contents (type of arithmetic operation, type of logical operation, data amount, etc.) performed by the pixel operation circuit 400 is performed by registering the contents in the address management table 700 through the mode setting circuit 600. After registering the processing content in the address management table 700, the drawing circuit 3
00 outputs a bus right acquisition request to the arbitration circuit 320. After the bus arbitration, the arbitration circuit 320 notifies the drawing circuit 300 of permission to use the internal bus 330. Simultaneous arbitration circuit 3
Reference numeral 20 denotes an address management table 700 which indicates which circuit has acquired the bus right by the bus right acquisition circuit notification signal 321.
Notify. When the drawing circuit 300 acquires the bus right from the arbitration circuit 320, it outputs an address and data to the internal bus 330. At this time, the address management table 700 fetches the address output to the internal bus 330, and determines from the fetched address and the bus right acquisition circuit notification signal 321 whether or not the access requires processing in the pixel operation circuit 400. If the address management table 700 determines that the access is to perform processing in the pixel operation circuit 400,
The contents of the operation performed by the pixel operation circuit 400 are output to the pixel operation circuit 400 as processing contents 710, the switching signal 711 is output to the selectors 410 and 411, and the address and data output to the internal bus 330 are transmitted to the pixel operation circuit 400. The operation result of the pixel operation circuit 400 is input to the memory 500. The pixel operation circuit 400 has processing contents 7
The pixel calculation processing is performed according to 10, and the processing result is output to the memory 500. When the display circuit 310 reads the display pixel data from the frame buffer 540, the display circuit 310 outputs a bus right acquisition request to the arbitration circuit 320. After receiving the bus right of the internal bus 330 from the arbitration circuit 320, the display circuit 310 outputs an address to the memory 500 via the internal bus 330 and the transfer path 340,
The data output from the memory 500 is transferred to the transfer path 340,
The data is read via the internal bus 330. Thereafter, the display circuit 310 outputs the display pixel data read into the CRT 950.

As described above, the mode setting circuit 600 for setting the operation contents of the pixel operation circuit 400 and the processing contents of the pixel operation circuit 400 are held, and the access to the memory 500 is performed by the pixel operation circuit 400. By providing the address management table 700 for determining whether or not it is necessary to perform the drawing, the CPU 910 can perform the drawing processing by software while maintaining that the CPU 910 can access the main memory 510 in the same manner as the conventional memory. When performing the pixel processing, which is a simple process but requires a large amount of data and takes a long time in software processing, is performed by the pixel calculation circuit 400 shared with the drawing circuit 300.
It is possible to reduce the overhead of the CPU 910 when realizing a drawing function not included in 00 by software on the CPU 910.

FIG. 2 shows a configuration example of the CPU I / F 200 in FIG. In FIG. 2, 2100 is an address register, 2200 is a comparator, 2300 is an address buffer,
2400 is a data buffer, and 2510 and 2520 are selectors.

In FIG. 2, address register 2100
Holds an address assigned to the mode setting circuit 600 on the memory 500. The comparator 2200 is
The address input from the external bus 900 is compared with the contents of the address register 2100. If the address is equal to the address assigned for the mode setting circuit 600, the selector 25
The switching signal 2210 is output to 10 and 2520, and the address and data input from the external bus 900 are output to the mode setting circuit 600. If the address input from the external bus 900 and the contents of the address register 2100 are different, The address and data input from the external bus 900 are output to the data buffer 2400 and the address buffer 2300, respectively.

FIG. 3 shows the mode setting circuit 600 in FIG.
An example of the configuration will be described. In FIG. 3, 3100 and 3200 are decoders, and 3310 and 3320 are selectors.

In FIG. 3, data input from the CPU I / F 200 or the drawing circuit 300 is
The signal is input to the decoder 3200 via the. CPU
The address input from the I / F 200 or the drawing circuit 300 is sent to the decoder 3100 via the selector 3320.
Is input to The decoder 3100 decodes the input address, and a registration signal for writing new registration contents in the address management table 700, selectors 410 and 41.
A switching signal for switching 1 and an access circuit indicating from which circuit the registered content is output. The decoder 3200 decodes the input data, and outputs an address at which the pixel operation is performed by the pixel operation circuit 400 and processing contents indicating the operation contents at that time.

FIG. 4 shows a configuration example of the address management table 700 in FIG. In FIG. 4, 4100-1,
4100-2 is an address table, 4210, 422
0, 4230, 4240, and 4250 are selectors.

In FIG. 4, when a registration signal is input from the mode setting circuit 600, an address, a process content, and a switching signal which are simultaneously input are selected by an access circuit, and in the case of setting for the CPU I / F 200, an address is selected. In the case of the setting for the drawing circuit 300, the table 4100-1 is written to the address table 4100-2.
The registered contents are searched from the address tables 4100-1 and 4100-2 by the address 322 read from the internal bus 330. Is selected and output as the processing content 710 and the switching signal 711.

FIG. 5 shows a configuration example of the drawing circuit 300 in FIG. In FIG. 5, reference numeral 5100 denotes a fetch circuit;
200 is a pixel creation circuit, and 5300 is an instruction decoder.

In FIG. 5, when accessing the memory 500, the fetch circuit 5100 performs bus right arbitration processing with the arbitration circuit 320 and the internal bus 33 after acquiring the bus right.
Address output to 0 is performed. The instruction decoder 5300 includes:
The display list read from the memory 500 is analyzed, and based on the analysis result, the pixel creation circuit 5200
Outputs parameters for pixel creation. Instruction decoder 53
00 outputs an address to the fetch circuit 5100 when accessing the memory 500. The instruction decoder 5300 outputs an address and data to the mode setting circuit 600 and registers the processing contents of the pixel operation circuit 400 in the address management table 700. Pixel creation circuit 5
200 generates pixel data based on the pixel creation parameters input from the instruction decoder 5300. When accessing the memory 500, the pixel creation circuit 5200 outputs an address to the fetch circuit 5100. The pixel creation circuit 5200 includes a mode setting circuit 60
The address and data are output to 0, and the processing contents of the pixel operation circuit 400 are registered in the address management table 700.
FIG. 6 shows a configuration example of the pixel operation circuit 400 in FIG. 6, reference numeral 6100 denotes a register, 6200 denotes an adder, 6300 denotes a multiplier, 6400 denotes a comparator, and 6500 denotes an address conversion circuit.

In FIG. 6, what kind of pixel calculation processing is to be performed is set in a register 6100, an adder 6200, a multiplier 6300, and a comparator 6400 according to processing contents 710. The address conversion circuit 6500 performs address conversion when the amount of data input to the pixel operation circuit 400 by the filtering process is different from the amount of data output as a result of the processing performed by the pixel operation circuit 400.

FIG. 7 shows an overall configuration diagram of a second embodiment of the present invention. 7, reference numeral 7200 denotes a CPU I / F, 77
00 is a memory characteristic management table.

In FIG. 7, the memory characteristic management table 7
Access times corresponding to the main memory 510, the drawing data 520, the drawing work 530, and the frame buffer 540 are registered in the 700. When the CPU 910 accesses the memory 500, the CPU
By checking the access time from the memory property management table 7700 via F7200, the access time can be known before accessing the memory 500.

As described above, the main memory 510, the drawing data 520, the drawing work 530, the frame buffer 54
By providing a memory characteristic management table 7700 in which access times corresponding to each
When 10 accesses memory 500, memory 5 actually
By examining the access time from the memory characteristic management table 7700 before accessing
CPU9 determines how long it takes to access 0
10 can know in advance. Thus, for example, when accessing an area with a long access time,
It is possible to use means for reducing the overhead of memory access, such as making the CPU 910 frequently use burst access without random access.

FIG. 8 shows the CPU I / F 7200 in FIG.
An example of the configuration will be described. In FIG. 8, reference numeral 8100 denotes an address register, and reference numerals 8510 and 8520 denote selectors.

In FIG. 8, an address register 8100
In the table, the address to which the memory characteristic management table 7700 is assigned in addition to the contents of the address register 2100 is registered. The comparator 2200 is connected to the external bus 90
The address input from 0 is stored in the address register 8100.
And outputs the address and data input from the external bus 900 to any one of the mode setting circuit 600, the memory characteristic management table 7700, and the data buffer 2400 and the address buffer 2300.

FIG. 9 shows a first configuration example of the memory characteristic management table 7700 in FIG. In FIG.
00 is a memory characteristic management table.

In FIG. 9, the memory characteristic management table 9
100, the addresses and access times of the main memory 510, the drawing data 520, the drawing work 530, and the frame buffer 540 are registered. When an address is input from the CPU1 / F7200, the memory characteristic management table 9100 outputs the access time of the corresponding address.

FIG. 10 shows a memory map on the memory 500 in FIG.

FIG. 11 shows the memory 500 in FIG.
Here is a time chart when 10 accesses. FIG.
9A is a time chart when the main storage 510 is accessed by the CPU 910, and FIG. 9B is a time chart when the frame buffer 540 is accessed.

In FIG. 11, (a) shows that the first data is returned from the graphics processor 100 five cycles after the CPU 910 outputs the first command, and (b) shows that the CPU 910 outputs the first command. 15 shows that the first data is returned from the graphics processor 100 after 15 cycles.

FIG. 12 shows a second configuration example of the memory characteristic management table 7700 in FIG. In FIG.
Reference numeral 12100 denotes a memory characteristic management table.

In FIG. 12, a main storage 510, drawing data 520,
A bank number and an access time to which the drawing work 530 and the frame buffer 540 are respectively allocated are registered. This characteristic table 12100 is
This is a case where the memory 500 is composed of a plurality of banks. Here, the contents registered in the characteristic table 12100 include not only the access time but also the CPU 910 and the CPU I / F.
It is also possible to register protocols between 7200. For example, the main memory 510 is an SDRAM without weight.
The number of wait cycles is 0 depending on the interface and the access status of the drawing circuit 300 and the display circuit 310 in other cases.
It is also possible to register an SDRAM interface or the like with a wait that occurs for more than one cycle. Further, the registered contents of the memory characteristic management management table 7700 can be changed at any time while the system is operating. Therefore, the address and the access permission information of the drawing circuit 300 and the display circuit 310 with respect to the address are registered in the memory characteristic management table 7700, and the CPU 910 sets the drawing circuit 30
0 and the contents of the memory characteristic management table 7700 are simultaneously updated when data is transferred to the display circuit 310, and when the drawing circuit 300 or the display circuit 310 accesses the memory 500, the registered contents of the memory characteristic management table 7700 are referred to. If the access is performed while the memory is being accessed, it is possible to prevent each circuit from performing an excessive memory access and destroying data for other circuits.

FIG. 13 shows an overall configuration diagram of the third embodiment of the present invention. 13, 13100 is a graphics processor, 13200 is a CPU I / F, 13300 is a drawing circuit, 13910 is a CPU, and 13915 is a function selection signal. Note that, here, terminals that are also used in a normal memory such as an address strobe terminal, a write enable terminal, and a chip selection terminal are collectively illustrated as transfer lines between the external bus 900 and the CPU I / F 7200.

Referring to FIG. 13, a CPU 13910 has a memory 500.
Whether the pixel operation circuit 400 is used when accessing the image data and the contents of the operation processing when the image processing circuit is used are determined by the function selection signal 13915 by the graphics processor 1310.
Output to 0. The function selection signal 13915 is input to the CPU I / F 13200 in the graphics processor 13100. In the CPU I / F 13200, the processing content 13710 and the switching signal 137 are obtained from the function selection signal 13915.
11 is created and output. The drawing circuit 13300 includes a memory 50
Process contents 1372 if necessary when accessing 0
0 and a switching signal 13721 are output.

As described above, the function selection signal 1391 which outputs to the graphics processor 13100 whether the pixel operation circuit 400 is used when the CPU 13910 accesses the memory 500 and the content of the operation processing when using it.
By providing the CPU 5, when the CPU 910 accesses the main memory 510 in the same manner as the conventional memory, it can maintain the same access as the conventional memory. In many software processes, a pixel operation process which is time consuming is performed by the pixel operation circuit 400 which is shared with the drawing circuit 300, so that a drawing function not included in the drawing circuit 300 is realized by the CPU 910 when software is realized on the CPU 910. Overhead can be reduced.

FIG. 14 shows the CPU I / F 13 in FIG.
200 shows a configuration example. In FIG. 14, reference numeral 14100 denotes a buffer, and 14200 denotes a decoder.

In FIG. 14, a buffer 14100 receives a function selection signal 13915 and holds its contents.
The buffer 14100 stores the held content in the decoder 142
Output to 00. The decoder 14200 includes the buffer 14
Based on the output of 100, the processing content 13710 and the switching signal 13711 are output.

FIG. 15 shows the drawing circuit 1330 in FIG.
0 shows a configuration example. In FIG. 15, reference numeral 15200 denotes a pixel creation circuit, and reference numeral 15300 denotes an instruction decoder.

In FIG. 15, a pixel forming circuit 15200
When accessing the memory 500, the pixel operation circuit 40
If it is desired to perform the arithmetic processing at 0, the processing content 13720 and the switching signal 13721 are output. Instruction decoder 1530
0 indicates that the pixel operation circuit 4
If it is desired to perform the arithmetic processing at 00, the processing content 13720 and the switching signal 13721 are output.

FIG. 16 shows an overall configuration diagram of the fourth embodiment of the present invention. In FIG. 16, 16100 is a graphics processor, 16940 is an I / O controller, and 1692
0 is a TV tuner and 16930 is a CDROM.

In FIG. 16, the I / O controller 16
940 has a built-in high-speed serial interface. Examples of this high-speed serial interface include:
There is IEEE1394.

As described above, the I / O controller 169
By incorporating 40 in the graphics processor 16100, the number of LSIs constituting the graphics system can be reduced, and the cost can be reduced. In addition, capturing of an image from the TV tuner 16920 is also performed by the I / O
Since the controller 16940 is connected to the internal bus, the operation can be performed at high speed.

FIG. 17 shows an overall configuration diagram of the fifth embodiment of the present invention. In FIG. 17, 17100-1, 17100-
2 is a graphics processor and 17310 is a display circuit.

In FIG. 17, the display circuit 17310 does not output display pixel data while the synchronization signal 17341 input from the graphics processor 17100-2 is "1". The display circuit 17310 outputs the synchronization signal 1734.
1 outputs the synchronization signal 17340 as “1” and outputs the display pixel data as the display signal 17350 during “0”. The display circuit 17310 sets the synchronization signal 17340 to “0” after outputting the display pixel data. “0” is always input to the graphics processor 17100-2 as a synchronization signal 17342 from the outside.

As described above, by providing a signal for synchronizing display among a plurality of graphics processors, a plurality of graphics processors can be used even if one graphics processor cannot cope with a large display screen size. And improve the flexibility of the system.

FIG. 18 shows an overall configuration diagram of the sixth embodiment of the present invention. In FIG. 18, reference numeral 18100 denotes a graphics processor, and 18910 denotes a CPU.

FIG. 18 shows a graphics processor 18100 in which even the CPU 18910 is built.

As described above, by incorporating even the CPU 18910 into the graphics processor 18100, the number of pins of the package of the graphics processor 18100 can be reduced, and
Cost and graphics processor 18100
Can reduce the mounting cost and the like of a system that uses the. FIG. 19 shows an overall configuration diagram of the seventh embodiment of the present invention. FIG.
9, 19100-1 and 19100-2 are graphics processors, 19200 is an external I / F, 199
Reference numeral 10 denotes a CPU.

In FIG. 19, an external I / F 19200 is a circuit for exchanging data with the graphics processor 19100-1.

As described above, the external I / F 19200 for exchanging data with another graphics processor.
, The flexibility of the system can be improved.

As described above, the CPU 910 stores the main memory 51
When the CPU 910 performs drawing processing by software while maintaining the same access as conventional memory when accessing 0, pixel processing that is a simple processing but requires a large amount of data and takes time in software processing The processing is performed by the pixel operation circuit 400 which is shared with the drawing circuit 300, so that a drawing function not included in the drawing circuit 300 is executed by the CPU 9.
It is possible to reduce the overhead of the CPU 910 when realizing by software on the CPU 10. Further according to the present invention, the CPU 910
Actually accesses the memory 500,
0 before accessing the memory characteristic management table 7700
By checking the access time from the
CPU9 determines how long it takes to access 0
10 can know in advance. Therefore, for example, when accessing an area with a long access time, the CPU 9
For example, it is possible to use a means for reducing memory access overhead, such as using a burst access without random access as much as possible.

[0056]

According to the present invention, a frame buffer for storing pixel data for display using a graphic processor having a built-in memory and a main memory for storing programs and data for operating the CPU are provided. CPU for graphics processor with built-in memory
Can be accessed like a conventional memory. Further, it is possible to reduce the overhead generated when the CPU performs the drawing process by software.

Further, according to the present invention, when the CPU accesses the memory, the CPU can know in advance how long it takes to access the memory, so that, for example, an area having a long access time is accessed. In such a case, the overhead of memory access can be reduced, for example, the CPU makes heavy use of burst access without random access as much as possible.

[Brief description of the drawings]

FIG. 1 is an overall configuration of a first embodiment of the present invention.

FIG. 2 is a configuration of a CPU I / F 200 in FIG.

FIG. 3 shows a configuration of a mode setting circuit 600 in FIG.

FIG. 4 is a configuration of an address management table in FIG. 1;

FIG. 5 is a configuration of a drawing circuit in FIG. 1;

FIG. 6 shows a configuration of a pixel operation circuit in FIG.

FIG. 7 is an overall configuration of a second embodiment of the present invention.

FIG. 8 shows a configuration of a CPU I / F 7200 in FIG.

FIG. 9 is a first configuration of a memory characteristic management table in FIG. 7;

FIG. 10 is a memory map on a memory in FIG. 7;

FIG. 11 is a time chart when the CPU accesses the memory in FIG. 7;

FIG. 12 shows a second example of the memory characteristic management table in FIG.
It is a structure of.

FIG. 13 is an overall configuration of a third embodiment of the present invention.

FIG. 14 shows a configuration of a CPU I / F in FIG.

FIG. 15 is a configuration of a drawing circuit in FIG. 13;

FIG. 16 is an overall configuration of a fourth embodiment of the present invention.

FIG. 17 is an overall configuration of a fifth embodiment of the present invention.

FIG. 18 is an overall configuration of a sixth embodiment of the present invention.

FIG. 19 is an overall configuration of a seventh embodiment of the present invention.

[Explanation of symbols]

100, 13100, 16100, 17100, 181
00, 19100: Graphics processor, 20
0,7200,13200 ... CPU I / F, 300,133
00 drawing circuit, 310, 17310 display circuit, 32
0: arbitration circuit, 321: bus right acquisition circuit notification signal, 33
0: internal bus, 340: transfer path, 400: pixel operation circuit, 410, 411, 2510, 2520: selector,
500 memory, 510 main storage, 520 drawing data, 530 drawing work, 540 frame buffer, 600 mode setting circuit, 700 address management table, 710 processing contents, 711 switching signal, 900
... external bus, 910, 18910, 19910 ... CPU, 9
20, 16920 ... TV tuner, 930, 16930
... CDROM, 940, 16940 ... I / O controller, 950 ... CRT, 2100, 8100 ... address register, 2200 ... comparator, 2300 ... address buffer, 2400 ... data buffer, 3100, 3200 ...
Decoder, 4100 ... Address table, 5100, 151
00 fetch circuit, 5200, 15200 pixel creation circuit, 5300, 15300 instruction decoder, 6100
Register, 6200: Adder, 6300: Multiplier, 64
00: comparator, 6500: address conversion circuit, 770
0, 9100, 12100 ... memory characteristic management table,
14100: buffer, 14200: decoder, 19200
... External I / F.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 1/21 G06F 15/72 A (72) Inventor Akihiro Katsura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Inside Hitachi, Ltd.

Claims (32)

[Claims] 1. A display control circuit for controlling display data for each pixel, and a memory for storing at least an operation result created by an external CPU and the display data, wherein the display control circuit and the memory A graphics processor mounted on the same semiconductor substrate, wherein an access procedure for accessing the operation result and an access procedure for accessing the display data when the CPU accesses the memory are different. 2. The semiconductor substrate according to claim 1, wherein the semiconductor substrate includes an address strobe terminal for connecting to the CPU, a write enable terminal, a chip select terminal, and a terminal for designating an access procedure when the CPU accesses the memory. A graphics processor. 3. The graphics processor according to claim 1, wherein the graphics processor has an access information holding circuit for holding access information for the CPU to access the operation result and the display data. . 4. The graphics processor according to claim 3, wherein said access information holding circuit can dynamically update said access information. 5. The graphics according to claim 3, wherein said access information holding circuit holds, as said access information, an access time for each area in said memory when said CPU accesses said memory. Processor. 6. The graphics according to claim 3, wherein said access information holding circuit holds, as said access information, an access procedure for each area in said memory when said CPU accesses said memory. Processor. 7. The access information holding circuit according to claim 3, wherein the access information holding circuit holds access permission information as the access information, and updates the access permission information when the CPU outputs data to the memory. And a graphics processor. 8. The graphics processor according to claim 3, wherein said memory is constituted by a plurality of banks, and said access information holding circuit holds said access information for each of said banks. 9. A drawing circuit for executing a drawing process, a display control circuit for controlling display data for each pixel, and a memory, wherein the drawing circuit, the display control circuit, and the memory are the same semiconductor substrate. Graphics, wherein the memory has at least an area for storing a program or data for an external CPU and an area for storing a program or data shared by the CPU and the drawing circuit. Processor. 10. A drawing circuit that executes a drawing process, a display control circuit that controls display data for each pixel, and a memory that stores an operation result of an external CPU, a drawing result of the drawing circuit, and the display data. A graphics processor, wherein the drawing circuit, the display control circuit, and the memory are mounted on the same semiconductor substrate, and the display control circuit has a synchronization unit with the outside of the semiconductor substrate. 11. A drawing circuit for performing a pixel generation process, a pixel calculation circuit for performing a pixel calculation process on a pixel generation result of the drawing circuit, and a pixel calculation control circuit for controlling the pixel calculation circuit. A display control circuit that controls display data for each pixel; and a memory that stores an operation result of an external CPU, the pixel generation result, and the display data, wherein the drawing circuit, the pixel operation circuit, and the pixel The arithmetic control circuit, the display control circuit, and the memory are mounted on the same semiconductor substrate, the CPU and the drawing circuit output control data to the pixel arithmetic control circuit, and the pixel arithmetic control circuit stores the control data in the control data. A graphics processor for controlling the pixel operation circuit based on the graphics processor. 12. The pixel operation control circuit according to claim 11, wherein the semiconductor substrate has a terminal for the CPU to output the operation result to the memory, and the CPU uses the terminal to transmit the control data to the pixel operation control circuit. Output to the graphics processor. 13. The graphics processor according to claim 11, wherein said semiconductor substrate has a dedicated terminal for said CPU to output said control data to said pixel operation control circuit. 14. A CPU for executing a calculation process, a drawing circuit for performing a pixel generation process, a pixel calculation circuit for performing a pixel calculation process on a pixel generation result of the drawing circuit, and controlling the pixel calculation circuit. A display control circuit for controlling display data for each pixel; and a memory for storing the calculation result of the CPU, the pixel generation result, and the display data. The circuit, the pixel operation circuit, the pixel operation control circuit, the display control circuit, and the memory are mounted on the same semiconductor substrate, and the CPU and the drawing circuit output control data to the pixel operation control circuit, The graphics processor, wherein the pixel operation control circuit controls the pixel operation circuit based on the control data. 15. The graphics processor according to claim 11, wherein said semiconductor substrate has a video input terminal. 16. The semiconductor device according to claim 11, wherein said semiconductor substrate has a high-speed serial communication terminal.
A graphics processor. 17. A CPU for executing arithmetic processing, a display control circuit for controlling display data for each pixel, and a memory for storing at least the arithmetic result created by the CPU and the display data, A graphic processing device, wherein the display control circuit and the memory are mounted on the same semiconductor substrate, and the CPU has a different access procedure for accessing the operation result and an access procedure for accessing the display data. 18. The semiconductor device according to claim 17, wherein the semiconductor substrate comprises an address strobe terminal for connecting to the CPU, a write enable terminal, a chip selection terminal, and a terminal for designating an access procedure when the CPU accesses the memory. A graphics processing apparatus. 19. The display control circuit according to claim 17, wherein said CPU accesses said operation result for a predetermined access time, and said CPU waits for access to said display data according to an access state of said display control circuit to said display data. A graphic processing device for performing either access or weightless access. 20. The graphic processing apparatus according to claim 17, wherein said graphic processing apparatus includes an access information holding circuit for holding access information for allowing said CPU to access said calculation result and said display data. . 21. A graphic processing apparatus according to claim 20, wherein said access information holding circuit can dynamically update said access information. 22. The graphic processing method according to claim 20, wherein said access information holding circuit holds, as said access information, an access time for each area in said memory when said CPU accesses said memory. apparatus. 23. The graphic processing method according to claim 20, wherein said access information holding circuit holds, as said access information, an access procedure for each area in said memory when said CPU accesses said memory. apparatus. 24. The apparatus according to claim 20, wherein said access information holding circuit holds access permission information as said access information, and updates said access permission information when said CPU outputs data to said memory. Graphic processing device. 25. The graphic processing apparatus according to claim 20, wherein said memory comprises a plurality of banks, and said access information holding circuit holds said access information for each said bank. 26. A CPU that executes arithmetic processing, a drawing circuit that executes drawing processing, a display control circuit that controls display data for each pixel, and a memory, wherein the drawing circuit, the display control circuit, The memory is mounted on the same semiconductor substrate, and the memory has at least an area for storing the program or data for the CPU and an area for storing a program or data shared by the CPU and the drawing circuit. A graphic processing device characterized by the above-mentioned. 27. A CPU for executing a calculation process, a drawing circuit for executing a drawing process, a display control circuit for controlling display data for each pixel, a calculation result of the CPU, a drawing result of the drawing circuit, and the display. A memory for storing data, wherein the drawing circuit, the display control circuit, and the memory are mounted on the same semiconductor substrate, and the display control circuit has a synchronization unit with the outside of the semiconductor substrate. Characteristic graphic processing device. 28. A CPU for performing an arithmetic process, a drawing circuit for performing a pixel generation process, a pixel calculation circuit for performing a pixel calculation process on a pixel generation result of the drawing circuit, and controlling the pixel calculation circuit A pixel calculation control circuit for controlling the display data for each pixel; a memory for storing the calculation result of the CPU, the pixel generation result, and the display data; The pixel operation circuit, the pixel operation control circuit, the display control circuit, and the memory are mounted on a same semiconductor substrate; the CPU and the drawing circuit output control data to the pixel operation control circuit; A graphic processing apparatus, wherein the control circuit controls the pixel operation circuit based on the control data. 29. The pixel operation control circuit according to claim 28, wherein the semiconductor substrate has a terminal for the CPU to output the operation result to the memory, and the CPU uses the terminal to transmit the control data to the pixel operation control circuit. Output to the graphic processing device. 30. The apparatus according to claim 28, wherein said semiconductor substrate has a dedicated terminal for said CPU to output said control data to said pixel operation control circuit. 31. An apparatus according to claim 28, wherein said semiconductor substrate has a video input terminal. 32. The semiconductor device according to claim 28, wherein the semiconductor substrate has a high-speed serial communication terminal.
A graphic processing device characterized by the following.