JPH10257042A - Frame synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of frame step-out even in the transmission line of strong fluctuation like a moving transmission line for which large delay waves are present by constituting a frame phase detector by the M pieces of the delay circuits of different delay amounts, the M pieces of matched filters and a convex function judgement circuit for judging the output of the matched filters and detecting an accurate peak position at all times. SOLUTION: Reception signals considered as a unique word pattern are branched, respectively L symbol delayed in delay devices 6-8 and then, inputted to the matched filters 9-12. The convex function judgement circuit 13 performs correlation computation with a unique word by the M pieces of different initial phases from the output of the matched filters 9-12, identifies whether or not it is turned to a convex function relating to a desired phase and performs output to a frame counter as synchronizing signals. Thus, in the transmission line of a large delay spread, a frame phase is detected by an optimum phase at all times and phase fluctuation is followed up even in the case that the delay spread fluctuates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for synchronizing a demodulator in digital communication, and more particularly to a technique for stably synchronizing a frame even in a transmission line having a large delay wave and a large fluctuation such as a mobile transmission line. It relates to the technology that can be taken.

[0002]

2. Description of the Related Art In digital communication, a known pattern signal is inserted at certain time intervals, and timing may be synchronized between transmission and reception. This is equivalent to dividing the time axis by a known pattern, and is a process necessary when applying error correction or a block code. Furthermore, a method of transmitting one transmission path in a time-division manner (TDM: Time Divisio
n Multiplex), a unique word is inserted as a known pattern to identify each channel.

[0003] This is called TDMA (Time Division Multip).
le Access) The same applies to satellite communication and the like. Also,
PHS (Personal Handy Phone System), GSM (Gl
obalSystem for Mobile Communication), PDC (Per
Digital mobile communication systems such as the sonal digital cellular system use the TDMA method. In such a system, it is very important to accurately perform this unique word synchronization in order to accurately identify each channel. Processing.

[0004] The unique word synchronization method (hereinafter referred to as frame synchronization) basically includes a frame phase detector for detecting the position of the unique word from the received signal, and a unique word for the received signal based on the detected phase information. It is composed of a switch circuit to be cut out and a frame counter for performing on / off control of the switch circuit based on the frame phase information.

FIG. 1 shows an example of the configuration of a frame synchronization circuit. In the figure, numeral 1 indicates a signal input terminal, 2 indicates a frame synchronization signal output terminal, 3 indicates a frame counter, 4 indicates a switch circuit, and 5 indicates a frame phase detector.

The switch circuit 4 allows only a received signal including a unique word pattern to pass therethrough and inputs the signal to a frame phase detector. The frame phase detector 5 determines whether or not the input signal is a unique word, and inputs the result to the frame counter 3. The frame counter 3 further integrates the information from the frame phase detector 5 over several frames and determines whether a truly unique word has been received.

If it is determined that the position is not a unique word position, "frame phase is shifted", and the process shifts to the initial search mode. In the initial search mode, the switch circuit 4 is closed, and the received signal is always input to the frame phase detector to search the position of the frame phase. That is, since the initial search mode cannot result in the own channel,
Communication is not possible.

As a configuration of the frame phase detector 5, a configuration in which a matched filter using a transmission pattern as a tap coefficient is applied is known. Reference 1: R.S. A. Scholt
z: “Frame Synchronization Techniques”, IEEE
Trans. Commu., Vol. 8, pp. 12
04-1213, 1980. reference)

FIG. 15 shows an example of the configuration of a frame phase detector to which a matched filter is applied. In the figure, numeral 133 indicates an input terminal, 136 indicates an output terminal, 134 indicates a matched filter, and 136 indicates a peak counter for determining whether the output level of the matched filter is equal to or higher than a threshold value. In this configuration, since the unique word pattern is written as the tap coefficient in the matched filter, a correlation operation between the received signal and the unique word pattern appears on the output as a result.

Therefore, when the received signal and the unique word pattern are the same, the maximum output is obtained. Therefore,
The peak counter identifies whether or not the output level is to be determined as the unique word level, and outputs the result. The matched filter is constituted by a delay line filter with a tap, and the peak counter is constituted by a comparator with a predetermined level.

FIG. 16 shows a configuration example of a frame counter.
Shown in In the figure, 137 is an input terminal, 142 is an output terminal, 139 and 140 are switch circuits, 168 is an out-of-synchronization signal output device, 138 is a normal mode circuit, and 141 is an initial mode circuit. In this configuration, the normal mode circuit operates in the "frame synchronization" state and monitors whether or not "out of frame synchronization" occurs.The initial mode circuit operates in the "out of frame synchronization" state, and in which phase It checks whether "frame synchronization" is established.

That is, if the normal mode circuit determines "out of frame synchronization", the normal mode circuit stops and the initial mode circuit starts operating. Conversely, when the initial mode circuit searches for a phase that can be determined as “frame synchronization”, the normal mode circuit starts operating and the initial mode circuit stops.

FIG. 17 is a diagram showing an example of the configuration of a normal mode circuit. In the figure, numeral 143 is a synchronization signal input terminal, 142 is a frame signal output terminal, 149 is an Acq signal input terminal from the normal mode circuit, 150 is a frame phase information input terminal searched by the normal mode circuit, and circuits 144 to 144. 147 is a delay circuit, 148 is an N-input AND circuit, 170 is a frame signal generation circuit, and 150 is a NOR circuit.

In FIG. 1, when an out-of-synchronization signal is input N times consecutively, the N-input AND circuit outputs a logic "1", and "frame out-of-synchronization" occurs. In this case, the frame signal output at the time of frame synchronization, that is, the signal controlling the switch circuit 4 of FIG. 1 becomes logic "0" by the NOR circuit, and the switch circuit 4 is kept open.

Next, FIG. 18 shows an example of the configuration of the initial mode circuit. In the figure, 154 is an input terminal, 165 is an Acq signal output terminal indicating that the frame synchronization position has been searched, 164 is a terminal for outputting the search result, 156 is a logic inversion circuit, 155 is a switch circuit for branching an input,
58 to 161 are delay circuits, 162 is an N-input AND circuit, 163 is an OR circuit, and 157 is a synchronization determination circuit.

Usually, the synchronization determination circuits are provided for the number of symbols included in the unique word pattern. Therefore, when a signal indicating that a certain symbol has been continuously synchronized is output N times, the synchronization determination circuit corresponding to the phase outputs a logical 1 and is regarded as "frame synchronization" established, outputs an Acq signal, and is searched simultaneously. Transmit the phase to the normal mode circuit.

[0017]

SUMMARY OF THE INVENTION The frame synchronization circuit having the above-mentioned configuration is constructed by an AWGN (Additive White Gaussian Noisy).
e) If the channel operates well, but the level ratio between the delayed wave and the preceding wave fluctuates dynamically like a mobile transmission line and there is a large delayed wave compared to the symbol length, the matched filter Peak position cannot be determined or fluctuates.

When the conventional frame phase detector is applied, every time the peak position fluctuates, it is determined that the position is not the unique word position or "the frame is out of synchronization" as described above, and the apparatus enters the initial search mode. That is, as described above, the state becomes a “communicable state”. When the peak position fluctuates frequently as in the case of a mobile transmission line, a “communicable state” frequently occurs, and the communication state is significantly deteriorated.

When the communicating parties move as in the case of mobile communication, the optimum frame phase slowly changes. Even in such a case, as described above, the state once falls into the "out of frame synchronization" state, and the communication state is deteriorated.

Further, in order to realize good signal transmission on a transmission line where a large delay wave exists, a technique for removing the influence of the delay wave is required. Among such techniques, an adaptive equalizer can improve signal transmission characteristics in a mobile transmission line by actively using a delayed wave.

A DSP (Digital Signal) is used as an adaptive equalizer.
Decision Feedback Equalizer (DFE) (Decision Feedback Equalizer), which can be realized relatively easily by the Processer) (Reference 2: JG Proakis: “Digital Communications 2n
d ed. ", McGraw-Hill, 1989., or MLSE (Maximum Likelihood Sequence Estimati).
on) DDFS that simplifies the type equalizer (see Document 2 above)
E (Delayed Decision Feedback Sequecse Estimation)
Type equalizer (Reference 3: AD-Hellen et al .: “Delayed D
ecisionFeedback Sequecse Estimation ", IEEE T
rans.Commu., Vol. COM-37, No. 5, pp. 428
-436, 1980. ), The structure of the equalizer is not symmetrical on the time axis, so that the characteristics are significantly different between the case where the frame phase is synchronized with the preceding wave and the case where the frame phase is synchronized with the delayed wave.

However, the frame synchronization circuit to which the frame phase detector shown in FIG. 15 is applied sometimes draws in a delayed wave depending on the situation, and this situation is continued in some cases. At this time, even if the communication cannot be performed, it is an unfavorable pull-in phase for the equalizer and deteriorates the communication quality.

As described above, when a conventional frame synchronization circuit centered on a matched filter and a peak counter is applied to a transmission line in which a preceding wave and a delayed wave dynamically fluctuate like a mobile transmission line, frame synchronization is lost. There is an undesired problem that it frequently occurs and transmission characteristics are significantly deteriorated. Further, in the prior art, since only the state of the pull-in phase is observed at the time of frame synchronization, even if a large peak exists adjacently, it cannot be detected.

Therefore, there is a problem that the frame phase is continuously drawn to a frame phase which is not preferable for the receiver, and the transmission quality is deteriorated. Furthermore, assuming a receiver equipped with an adaptive equalizer, it is impossible to detect whether or not the current pull-in phase is optimal for the equalizer in the related art, although the characteristics are significantly different depending on the pull-in phase. However, there is a problem that sufficient transmission characteristics cannot be exhibited.

According to the present invention, it is possible to pull in the best pull-in phase for a receiver without causing frame synchronization loss even in a transmission line having a large fluctuation such as a mobile transmission line and having a large fluctuation. It is an object of the present invention to provide a frame synchronizing means for pulling in a preceding wave which is preferable for an equalizer.

[0026]

According to the present invention, the above-mentioned object is attained by the means described in the claims.

That is, according to the first aspect of the present invention, there is provided a switch circuit for passing only a known transmission pattern from a received signal;
The switch circuit comprises a frame phase detector for determining whether the output signal of the switch circuit is a known pattern, and a frame counter for controlling the switch circuit by a frame signal synchronized with the reception cycle of the known pattern based on the output information. In the frame synchronization circuit,

The frame phase detector comprises M delay circuits each having an M-branch (M is an integer of 3 or more) signal output from the switch circuit and having different delay amounts, and an output of each delay circuit. Consisting of M matched filters as inputs, and a convex function determining circuit that receives all matched filter output signals as input and determines whether the matched filter output is a convex function centered on a predetermined timing And

The convex function determination circuit includes a 3 / M peak detector that outputs likelihood information when a current frame phase and phases before and after the current frame phase are set from M input signals, and a 3 / M peak detection circuit. Output (1 to 3), which is an input consisting of a matched filter that is faster in time among three inputs.
And an average value determination circuit that determines whether the average value of the later output 2 is larger than the remaining output 3.

When there are a plurality of delayed waves, the case where the frame phase is synchronized with the maximum value thereof is most preferable in terms of signal quality. That is, by determining the peak value of the matched filter output based on the matched filter output values in the preceding and following phases, an accurate peak position can always be detected.

Here, the received signal is represented by r _k (where k represents time), and the unique word pattern written in the tap coefficient of the matched filter is represented by C _i (i = 1...).
N), the matched filter output signal y _k is given by Expression (1) shown by “Equation 1”.

[0032]

(Equation 1)

At this time, the condition that the matched filter output y _{k at the} time k is the maximum is given by equation (2). y _k = max {y _{k + l} ; l = 0,..., M−1} (2) In general, the condition for a function to be a convex function at a certain point is as shown in equation (3). .

Y _k−1 −y _k < 0, y _{k + n} −y _k < 0 (l, n > 0) (3) where l and n are arbitrary natural numbers. Therefore, (3) 2
The following conditional expressions are obtained by adding the expressions.

Y _{k + n} + y _k−1 < 2y _k (4) That is, by always searching for a phase that satisfies the expression (4), the frame phase peaks when there is a delay spread unlike the related art. , Demodulation can be performed using a higher-level received signal, and there is an advantage that signal transmission characteristics can be improved.

According to a second aspect of the present invention, in the frame synchronization circuit of the first aspect, the 3 / M peak detector uses the input from the matched filter that performs the correlation operation at a desired frame phase as the detector output 2, and The outputs of the L matched filters whose inputs are the received signals temporally before the matched filter are input, and the maximum value is set to three detector outputs 1
And the remaining (ML)
-1) A second maximum value detector which outputs the maximum value of the matched filter outputs as the detector output 3 is provided.

The above equation (4) can be extended to a more general case as shown in the following equation (5). {Y _{k + 1} ; l = 0,..., M / 2-1} + max {y _{k + l} ; l = M / 2,..., M-1} < 2 (5) In a wider range (0 <1 <M), y _k is the maximum peak condition.

Therefore, unlike the prior art, even when the delay spread is greatly widened, the frame phase is always set to the peak of the delay spread, so that the demodulation can be performed using the highest level received signal. There is an advantage that the signal transmission characteristics can be improved. Also,
Since the level of the preceding wave is the highest in most transmission lines, it can always be synchronized with the preceding wave, unlike the prior art.
There is an advantage that high quality transmission is possible even when an equalizer is applied.

According to a third aspect of the present invention, in the frame synchronizing circuit according to the first aspect, the 3 / M peak detector is sequentially set to (M A first (M-2J) input adder for adding the (-2J) outputs, and a third (M-2J) output adder for adding the (M-2J) outputs in order from the one receiving the received signal that is later in time. M-2J) input adder, and a second (M-2J) input adder for adding all outputs except J earlier and J later in time, and the first to third (M-2J) input adders. M-2J) The outputs 1 to 3 of the input adder are configured to be detector outputs 1 to 3, respectively.

When an adaptive equalizer is used in a mobile transmission path, transmission characteristics can be improved by the presence of a delayed wave. Therefore, it is desirable to control the frame phase so as to include more delayed waves. At this time, the above equation (4) can be extended to an equation (6) shown by the following “Equation 2”.

[0041]

(Equation 2)

Thus, unlike the prior art, even when there are a plurality of peaks in the delay spread distribution, the frame phase can be set to the phase having the maximum energy, so that when the receiver is equipped with an adaptive equalizer, There is an advantage that the best characteristics can be obtained.

According to a fourth aspect of the present invention, there is provided a switch circuit for passing only a known transmission pattern from a received signal, and determining whether or not the output signal of the switch circuit is a known pattern. In a frame synchronization circuit configured by a frame phase detector with a counter that controls a switch circuit by a signal and outputs a received signal of a known pattern as a circuit output,

The frame phase detector with a counter is composed of M delay circuits each having a different delay amount and having an input of an M-branched signal of a switch circuit, and M matched filters having an output of each delay circuit as an input. With all the matched filter output signals as inputs, it is determined whether or not the matched filter output is a convex function centered on a predetermined timing. A convex function determination circuit with a shift that detects the direction of

This output is used as an input to generate a frame signal and perform a frame phase shift based on the timing shift information, or to always close the switch circuit, which is regarded as "out of frame synchronization" based on the determination result. And a frame counter with a phase shift for controlling

The convex function judging circuit with shift comprises a 3 / M peak detector for generating three main signals for judging a convex function from the M input signals;
An average value determination circuit that determines whether the average value of the output 1 and the later output 2 from the matched filter that is earlier in time is larger than the remaining output 3, and outputs the result as a shift signal;

The three outputs of the 3 / M peak detector are input and
A peak detector for comparing the magnitudes of the output 1 and the output 3 and outputting the result as a shift direction, judging a synchronization state from the three inputs and outputting the result as a synchronization signal. A frame signal generating circuit that receives a shift direction and a synchronization signal as input, and is driven by the shift signal to change a frame phase in the shift direction;

An out-of-synchronization signal generator and a switch circuit controlled by the synchronization signal to switch between the output of the frame signal generation circuit and the output of the out-of-synchronization signal generator, so that the output of the switch circuit is the output of the frame counter with phase shift. It is a frame synchronization circuit configured.

In the configuration of claim 4, in addition to the means of claims 1 to 3, all output signals of the matched filter provided in the frame phase detector are observed, so that the frame phase is completely out of sync. Can be identified. For example, even if the condition of Equation (4) is not satisfied, if the above-described identification result is determined to be “only slightly out of frame phase”, only the frame phase can be changed without falling into the state of “out of frame synchronization”. , In the direction of the maximum power phase.

As a result, unlike the prior art, even when the terminal performing communication moves and the optimal frame phase shifts with time, it is possible to follow the frame phase without inducing the "out of frame synchronization" state, and to improve the communication quality. There is an advantage that can be improved.

According to a fifth aspect of the present invention, in the frame synchronization circuit of the fourth aspect, the peak detector receives a 3 / M peak detector output signal as an input and outputs a maximum value thereof. A threshold memory for storing a threshold value, a first subtractor for comparing the detector output signal with the threshold memory output,

A switch circuit driven by the output of the first subtractor with the output of the average value determination circuit as an input and having the output as a synchronization signal output, and an output 1 of the 3 / M peak detector.
And a second subtractor for comparing the magnitude of the output 3 and outputting the result as a shift direction.

In a normal transmission path, the frame phase shifts slowly over time without a large jump.
Therefore, it is possible to sufficiently follow the frame phase fluctuation only by shifting the phase one by one in the direction of the large peak. Therefore, as means for estimating whether or not the power is equal to or more than the set value of claim 4, the maximum peak positions before and after the current frame synchronization position are detected,

If this value is equal to or greater than the set value, the frame phase is shifted toward a higher level adjacent direction without judging whether the peak is ahead or behind in time, without determining "out of frame synchronization". Thus, unlike the related art, there is an advantage that a phase shift can be easily performed in a correct direction without remaining at a local stable point.

According to a sixth aspect of the present invention, in the frame synchronization circuit according to the fourth aspect, a three-input adder which receives a 3 / M peak detector output signal as a peak detector and outputs an addition result thereof, A threshold memory for storing a threshold, a first subtractor for comparing the output of the three-input adder with the threshold memory,

A switch circuit driven by the output of the first subtractor with the output of the average value judgment circuit as an input and the output of which is a synchronization signal output, and the magnitudes of the outputs 1 and 3 of the 3 / M peak detector are determined. And a second subtractor for comparing and outputting the result as a shift direction.

In principle, the sum of the output power of each matched filter is equivalent to integrating the energy dispersed by the delay spread, and observing this is as follows:
This is the best indicator of whether the frame phase has shifted completely. Therefore, as means for estimating whether or not the power is equal to or more than the set value of claim 4, if the outputs of the respective matched filters are all added, and this can be used as an index of whether or not a unique word is received, Estimation with high reliability becomes possible.

That is, if the addition result is equal to or greater than the set value, only the frame phase is shifted to the adjacent without falling into the state of "frame synchronization loss", thereby providing a stable and highly accurate (While determining whether or not a unique word has been received), it is possible to follow the frame phase fluctuation, thereby improving the communication quality.

[0059]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an example of a circuit configuration corresponding to each of the above claims will be described as an embodiment of the present invention.

FIG. 2 shows an example of the configuration of the frame phase detector of the present invention used in the configuration of FIG. 1 shown as the first example of the frame synchronization circuit. In the figure, numeral 171 denotes a reception signal input terminal, 6 to 8 denote delay circuits, 9 to 12 denote matched filters, 13 denotes a convex function determination circuit, and 14 denotes a frame signal output terminal. In the figure, a received signal considered to be a unique word pattern is branched, and after being delayed by L symbols (L = 0,..., M−1), it is input to matched filters 9 to 12.

The output signals of the matched filters 9 to 12 are input to the convex function determination circuit 13 to determine whether they are in a synchronous state or an asynchronous state. Then, the result is input to the frame counter. In this configuration, a correlation operation with a unique word is performed at M different initial phases, and it is determined whether or not it satisfies the above equation (4) with respect to a desired phase (ie, is a convex function). This is configured to be input to the frame counter as a synchronization signal.

Although this configuration has matched filters in parallel, it can also be realized by sliding on a time axis with a single matched filter. FIG. 3 shows an example of the configuration of the convex function determination circuit used in FIG. In the figure, numeral 59 indicates an input terminal from a matched filter,
Reference numeral 15 denotes a 3 / M peak detector for searching three peaks necessary for frame phase judgment from M inputs, and 16 denotes a convex shape of three output values of the 3 / M peak detector output with respect to the center. 5 shows an average value circuit for determining whether or not there is an error.

FIG. 4 shows a configuration example of the average value circuit. In the figure, reference numerals 18 to 20 denote input signals from the 3 / M peak detector, 21 denotes an amplifier having a gain of 2, 22 denotes an adder,
23 is a subtractor, 25 is a peak counter, 26 is an OR circuit, and 27 is a synchronization signal output terminal. This circuit outputs a synchronization signal, logic "0", regarding the three inputs as the "synchronization" position only when the center peak is the largest and the absolute value of the peak is larger than a certain value.
The embodiment described above corresponds to the first aspect of the present invention.

FIG. 5 shows an example of the configuration of the 3 / M integral value. In the figure, numeral 48 indicates an input terminal, 49 and 50 indicate maximum value selection circuits, and 56 to 58 indicate output terminals. In this configuration, the maximum value of the temporally preceding and succeeding inputs is obtained and output to the matched filter output terminal that performs the correlation operation at the optimum frame phase.

Therefore, the convex function determination circuit to which this configuration is applied can always find the maximum value among the peaks of the delay spread that have spread over time. FIG. 6 shows the configuration of the maximum value detector. In the figure, numeral 91 indicates an input terminal, 97 indicates an output terminal, and 92 to 96 indicate a level comparison / selection circuit for outputting the higher of the two inputs.
This circuit can make pairs from the input and output the highest level signal in tournament style. The example of the embodiment described above corresponds to the invention of claim 2.

FIG. 7 shows an example of the configuration of the 3 / M peak detector. In the figure, numeral 166 is an input terminal from a matched filter, 42 to 44 are M-2J input adders,
Reference numerals 5 to 47 indicate output terminals. Among the M matched filter output signals, M-2J
These are input to the adder 42, the M-2J items from the latest are input to the adder 44, and the M-2J items excluding the earliest and the latest J items are input to the adder 43. Here, J is a natural number of 1 or more and M / 2 or less.

In this configuration, in the distribution of the delayed wave spread in time, the integral value between the early M-2J and the late M-2J and the integral value of the M-2J near the center thereof are obtained. . Therefore, in the convex function determination circuit using this configuration, the maximum distribution position can be obtained from the partial integral value of the delay spread. The configuration described above is claimed in claim 3
Corresponding to the invention of the above.

FIG. 8 shows a second example of the configuration of the frame synchronization circuit.
Shown in In the figure, numeral code 118 denotes an input terminal, 1
19 is a switch circuit, 120 is a frame phase detector with a counter having both functions of the frame synchronization circuit and the frame counter of FIG. 1, and 121 is a frame synchronization signal output terminal.

FIG. 9 shows an example of the configuration of a frame phase detector with a counter according to the present invention. In the figure, reference numeral 60 denotes an input terminal, 61 to 63 denote delay circuits, 64 to 67 denote matched filters, 68 denotes a convex function halftone device with a shift, 69 denotes a frame counter with a phase shift, and 70 denotes a frame signal output terminal. ing. In this configuration, the outputs of the matched filters 64-67 are input to the convex function determination circuit with shift 68, as described in the description of FIG.

The convex function with shift determining circuit 68 checks whether or not the peak value is a convex function. If the peak value is not a convex function, the shift direction of the frame phase is determined by the frame counter with phase shift. Send to As a result, it is possible to follow a correct frame phase without causing a “frame phase shift” state.

FIG. 10 shows an example of the configuration of the convex function judgment circuit with shift 68 at this time. In FIG.
Is an input terminal, 72 is a 3 / M peak detector, 73 is an average value determination circuit, 74 is a shift signal output terminal, 75 is a peak detector, and 76 and 77 are shift direction and synchronization signal output terminals, respectively.

In this configuration, in addition to the function described in the description of FIG. 3, the input signal 7 is obtained from three outputs of the 3 / M peak detector.
A check is made to see if any of these 1s is synchronized with the frame phase. If such a frame is present and the current frame position is shifted in time, that direction is output as the shift direction.

FIG. 11 shows an example of the structure of the frame counter with shift. In FIG.
24 is an input terminal, 125 is a frame signal generator, 126
Is a switch circuit, 127 is an out-of-synchronization signal generator, 12
Reference numeral 8 denotes an output terminal. In this circuit, a frame phase, which is an output signal from a frame signal generator, is moved according to a shift direction signal using a shift signal as a sigma.

Further, an out-of-synchronization signal or a frame signal is switched by a switch according to the synchronization signal. With this configuration, the frame phase can be changed without causing “out of synchronization” unlike the related art. The example of the embodiment described above corresponds to the invention of claim 4.

The first configuration of the peak detector shown in FIG.
12 is shown in FIG. In FIG.
0 is an input terminal, 81 is an input terminal from the average value judgment circuit,
84 and 87 are subtractors, 85 is a maximum value detector, 86 is a threshold value memory, 88 is a switch circuit, and 89 is a synchronization signal output terminal. In this circuit, of the output values from the 3 / M peak detector, the difference between the earlier value and the later one is obtained by a subtractor and output.

At the same time, the maximum value of the three input signals is obtained by the maximum value detector 85, and this output signal is compared with an output signal from a threshold value memory circuit storing a preset value. As a result of this comparison, when the memory output is larger, the signal from the average value determination circuit is regarded as valid, the switch circuit is turned on, and this output is used as a synchronization signal. The example of the embodiment described above is described in claim 5.
Corresponding to the invention of the above.

The second configuration of the peak detector in FIG.
13 is shown in FIG. In FIG.
01 is an input terminal, 104 is a 3-input adder, 105 and 10
7 is a subtractor, 106 is a threshold memory, 108 is a switch circuit, and 102 and 109 are output terminals. In this circuit, of the output values from the 3 / M peak detector, the difference between the earlier value and the later one is obtained by a subtractor and output.

At the same time, the three input signals are added in the adder 104, and this output signal is compared with an output signal from a threshold value memory circuit that stores a preset value. As a result of this comparison, when the memory output is larger, the signal from the average value determination circuit is regarded as valid, the switch circuit is turned on, and this output is used as a synchronization signal.

FIG. 14 shows an example of a detailed configuration of the frame counter with shift. In FIG.
0 to 112 are input terminals, 113 is a normal mode circuit with shift, 114 and 115 are switch circuits, 116 is an initial mode circuit, 129 is a switch circuit, and 117 is an output terminal.

In this circuit, unlike the prior art, the output from the convex function determination circuit with shift is input to the normal mode circuit with shift. The shift signal from the convex function determination circuit with shift is used in place of the Acq signal in the normal mode circuit, and the phase control signal from the initial mode circuit and the shift direction signal are switched by a switch controlled by the shift signal, and this is switched to the normal mode. Used as phase shift amount information of the circuit. The example of the above embodiment corresponds to the invention of claim 6.

[0081]

As described above, by applying the frame synchronization circuit of the present invention, a frame phase can always be detected at an optimum phase in a transmission line having a large delay spread. Furthermore, even when the delay spread fluctuates, there is an advantage that the communication quality can be improved because the phase fluctuation can be followed without causing the "frame phase shift" state. Further, since the frame synchronization circuit of the present invention detects the peak / maximum energy of the delay spread, the advantage that even a receiver provided with an adaptive equalizer as a measure against delay spread can exhibit the best characteristics can be obtained. There is.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first example of a configuration of a frame synchronization circuit.

FIG. 2 is a diagram showing a frame phase detector of the present invention.

FIG. 3 is a diagram illustrating a convex function determination circuit according to the present invention.

FIG. 4 is a diagram illustrating an example of a configuration of an average value circuit.

FIG. 5 is a diagram showing a first example of the configuration of a 3 / M peak detector according to the present invention.

FIG. 6 is a diagram illustrating an example of a configuration of a maximum value detector.

FIG. 7 is a diagram showing a second example of the configuration of the 3 / M peak detector of the present invention.

FIG. 8 is a diagram illustrating a second example of the configuration of the frame synchronization circuit.

FIG. 9 is a diagram showing a configuration of a frame phase detector with a counter according to the present invention.

FIG. 10 is a diagram illustrating a configuration of a convex function determination circuit with a shift of the present invention.

FIG. 11 is a diagram showing a configuration of a frame counter with a phase shift according to the present invention.

FIG. 12 is a diagram showing a first example of a configuration of a peak detector of the present invention.

FIG. 13 is a diagram showing a second example of the configuration of the peak detector of the present invention.

FIG. 14 is a diagram illustrating an example of a configuration of a frame counter with a phase shift according to the present invention.

FIG. 15 is a diagram showing a conventional frame phase detector.

FIG. 16 is a diagram illustrating an example of a configuration of a conventional frame counter.

FIG. 17 is a diagram illustrating an example of a configuration of a normal mode circuit.

FIG. 18 is a diagram illustrating an example of a configuration of an initial mode circuit.

[Explanation of symbols]

1,2,18 ~ 20,48,59,60,71,78 ~
81, 91, 98-101, 110-112, 118,
122 to 124, 133, 137, 143, 149, 1
50,166,171 Input terminal 2,14,17,45-47,56-58,70,74
~ 76,89,90,97,102,109,121,
128,117,136,142,152,153,1
64,165 output terminals 4,88,108,119,126,129,139,
140,155 switch circuit 5 frame phase detector 3 frame counter 6-8,61-63,144-147,158-161
Delay circuit 9-12, 64-67,134 Matched filter 13 Convex function determination circuit 15,72 3 / M peak detector 16,73 Average value determination circuit 21 Double amplifier 22,42-44,104 Adder 23,84 , 87, 105, 107 Subtractor 25, 135 Peak counter 26, 163 Logical OR circuit 92-96 Level comparator / selector 49, 50, 85 Maximum value detector 68 Convex function judgment circuit with shift 69 Frame counter with phase shift 75 Peak detector 86, 106 Threshold memory 120 Frame phase detector with counter 113, 138 Normal mode circuit 116, 141 Initial mode circuit 127, 168, 169 Out of synchronization signal generator 127, 148, 162 N-input AND circuit 170 Frame signal generator 151 Logic NOR circuit 154 Logic Inverting circuit

Claims (6)

[Claims] 1. A switch circuit for passing only a known transmission pattern from a received signal, a frame phase detector for determining whether or not a switch circuit output signal is a known pattern, and reception of a known pattern based on the output information In a frame synchronization circuit composed of a frame counter for controlling a switch circuit with a frame signal synchronized with a cycle, the frame phase detector is configured to convert an M-branch (M is an integer of 3 or more) signal of a switch circuit output. M delay circuits having different delay amounts as inputs, M matched filters having outputs of the delay circuits as inputs, all matched filter output signals as inputs, and the matched filter output is centered at a predetermined timing. And a convex function determining circuit that determines whether or not the function is a convex function. A 3 / M peak detector for outputting likelihood information when the current frame phase and phases before and after the current frame phase are set from the M input signals, and outputs (1 to 3) of the 3 / M peak detector are input. As 3
Among the inputs, an output 1 consisting of a matched filter that is earlier in time and an average value determination circuit that determines whether or not the average value of the later output 2 is larger than the remaining output 3. Characteristic frame synchronization circuit. 2. The 3 / M peak detector receives an input from a matched filter that performs a correlation operation at a desired frame phase as a detector output 2 and receives a received signal temporally earlier than the matched filter as an input. A first maximum value detector that receives the outputs of the L matched filters and outputs the maximum value as three detector outputs 1, and a maximum value of the remaining (ML-1) matched filter outputs 2. The frame synchronization circuit according to claim 1, further comprising a second maximum value detector that outputs a maximum value as a detector output 3. 3. A first (M-2J) output of a 3 / M peak detector which adds (M-2J) outputs of the matched filter outputs in order from the one that receives a temporally earlier received signal as an input. ) An input adder, a third (M-2J) input adder for adding the (M-2J) outputs in order from the one receiving the received signal which is later in time, and J earlier in time. A second (M-2J) input adder for adding all outputs except for the slower J outputs, and detecting outputs 1 to 3 of the first to third (M-2J) input adders, respectively 2. The frame synchronization circuit according to claim 1, wherein the outputs are 1 to 3. 4. A switch circuit for passing only a known transmission pattern from a received signal, and determining whether or not the output signal of the switch circuit is a known pattern, and switching the switch circuit with a frame signal synchronized with a reception cycle of the known pattern. A frame synchronization circuit including a frame phase detector with a counter that controls and outputs a received signal of a known pattern as a circuit output, wherein the frame phase detector with a counter receives an M-branched signal of a switch circuit as an input. M delay circuits each having a different delay amount, M matched filters having the outputs of the delay circuits as inputs, and all matched filter output signals as inputs, and the matched filter outputs having a convex shape centered on a predetermined timing Judge whether or not it is a function of A convex function determination circuit with a shift that detects the direction of the shift, a frame signal is generated using this output as an input, and a frame phase shift is performed based on the timing deviation information, or it is regarded as “frame loss” based on the determination result. A phase counter with a phase shift for controlling a frame signal so as to always close the switch circuit, wherein the convex function determination circuit with a shift circuit determines three main signals for determining a convex function from M input signals. A 3 / M peak detector to be generated, and using this output as input, determines whether the average value of output 1 and output 2 from the matched filter that is earlier in time is larger than the remaining output 3 among the three inputs. An average value determination circuit for outputting the result as a shift signal, and three outputs of a 3 / M peak detector as inputs, A peak detector for comparing the magnitude of the output 3 and outputting the result as a shift direction, determining a synchronization state from the three inputs and outputting the same as a synchronization signal, wherein the frame counter with phase shift comprises a shift signal, a shift direction, A frame signal generation circuit which receives a synchronization signal as input and is driven by the shift signal to change the frame phase in the shift direction, an out-of-synchronization signal generator, and a switch which is controlled by the synchronization signal and switches between the output of the frame signal generation circuit and the output of the out-of-synchronization signal generator A frame synchronization circuit comprising: a switch circuit output; and a frame counter output with a phase shift. 5. A peak detector which receives a 3 / M peak detector output signal and outputs a maximum value thereof, a threshold value memory for storing a threshold value, and a threshold value memory for storing a threshold value. 5. The frame synchronization circuit according to claim 4, further comprising a second subtractor for comparing the magnitudes of the outputs 1 and 3 of the M peak detector and outputting the result as a shift direction. 6. A peak detector, which receives a 3 / M peak detector output signal as an input, and outputs a result of addition, a three-input adder, a threshold memory for storing a threshold, and a threshold. A first subtractor for comparing the output of the value memory and the three-input adder, a switch circuit driven by the output of the first subtractor having the average value determination circuit output as an input, and having the output as a synchronization signal output; The frame synchronization according to claim 4, further comprising a second subtractor that compares the magnitudes of the output 1 and the output 3 of the 3 / M peak detector and outputs the result as a shift direction. circuit.