JPH10256839A - Power amplifier device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the destruction of a power amplifier device in an overload state where one of plural loads is abnormal by controlling the signal that is inputted to a voltage amplifier against the overload of a power amplifier circuit and then controlling the power voltage supplied to a power amplifier transistor TR when the signal inputted to the power amplifier TR from the output of the voltage amplifier has a large amplitude. SOLUTION: A power amplifier device has a power voltage control circuit 4 and a pulse width modulation circuit 3. When an input cut-off control TR 23 of a power amplifier circuit 1 is turned on, a signal whose level is shifted based on the ratio set between an input resistance 26 and an input limit resistance 27 is applied to a voltage amplifier 7. Thus, the output voltage of the amplifier 7 drops. When the duty ratio of pulse width of the circuit 3 decreases, the output voltage of the circuit 4 drops and then the power voltage supplied to a power amplifier TR 8 of the circuit 1 drops. As a result, the TR 8 is released from its abnormal load state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier for providing a signal to a plurality of speakers.

[0002]

2. Description of the Related Art In a power amplifying apparatus in which a plurality of speakers are connected as a plurality of loads, if the wiring of one of the plurality of speakers is short-circuited (short-circuited), the power amplifying apparatus becomes an abnormal load (overload). State. The conventional power amplifying device includes a protection circuit that disconnects all connected speakers and releases the overloaded state in order to prevent the power amplifying device from being destroyed by an overload.

FIG. 6 is a schematic diagram showing a schematic configuration of a conventional power amplifying device. 6, the power amplifying device includes a power amplifying circuit 1, an overload detecting circuit 2, and a power supply unit 5. The power amplifying circuit 1 amplifies the voltage of the signal input from the input terminal 6 by the voltage amplifier 7, amplifies the signal from the voltage amplifier 7 by the power amplifying transistor 8, and
Output from. The power supply unit 5 includes the power amplification circuit 1
Power supply. + BH and -BH are high voltage power supplies of the power amplifier circuit 1, and + BL and -BL are low voltage power supplies of the overload detection circuit 2.

The overload detection circuit 2 applies a bias voltage set in advance by a resistor 10 to a comparator 12 through an input resistor 11, and the output thereof keeps a low (low) voltage.
The feedback resistor 13 sets the gain of the comparator 12 based on the ratio with the input resistor 11. The capacitor 14 determines a time constant based on a product of the detection resistor 15 and the capacitor. With this time constant, the power amplification transistor 8 of the power amplification circuit 1 power-amplifies the large-amplitude input signal within a range not exceeding the safe operation area.

The operation of the overload detection circuit 2 will be described. When a large-amplitude signal is input to the input terminal 6 at the time of overload such as when the output terminals 9 of the power amplifier circuit 1 are short-circuited (short circuit) or when a large number of nonstandard loads (speakers) are connected, An excessive current flows through the power amplifying transistor 8, and the voltage drop across the emitter resistor 16 increases. The increased voltage is applied to one input of the comparator 12 via the detection resistor of the overload detection circuit 2. The other input of the comparator 12 receives a preset bias voltage. The comparator 12 compares the two input voltages, and when the voltage across the emitter resistor 16 exceeds the bias voltage, inverts the output from a low (low: L) voltage to a high (high: H) voltage.

The flip-flop circuit 17 has a reset
It is a set flip-flop circuit. When the power is turned on, the charging current of the initial setting capacitor 18 flows through the initial setting resistor 19, and the flip-flop circuit 17
Is reset (R). The initial setting diode 20 is an element for accelerating the discharge of the initial setting capacitor 18 when the power is turned off, and is for ensuring the initial setting operation when the power is turned on again.

When the output of the comparator 12 is inverted from L to H, the set (S) of the flip-flop circuit 17 becomes H
It becomes a reset state. When the flip-flop circuit 17 is set, the overload detection circuit 2 outputs a voltage signal H from the output terminal (Q).

When the overload detection circuit 2 outputs the voltage signal H, the diode 21 of the power amplification circuit 1
2, the input cutoff control transistor 23 is changed from the reverse bias state to the forward bias state. When the output from the output terminal (Q) of the flip-flop circuit 17 is the voltage signal L, the input cutoff control transistor 23 sequentially controls the reverse bias setting diode 24 and the reverse bias resistor 25 with respect to the signal voltage applied to the input terminal 6. A reverse bias is applied to the input cutoff control transistor 23 so as to become a bias and not cause a distortion. A signal from the input terminal 6 of the voltage amplifying circuit 1 has an input limiting resistor 27 having a lower resistance than the input resistor 26.
Signal flows to the side. At this time, most of the signal flows to the input cutoff control transistor 23 side.
7, a low current of the signal flows to the voltage amplifier 7 side. Therefore, the overload state of the power amplification transistor 8 is reduced, and a small output signal is output from the output terminal 9. Here, the feedback resistor 28 sets the gain and the like of the voltage amplifier 7 based on the ratio with the resistor 29.

In FIG. 6, when there is no input limiting resistor 27 of the power amplifier circuit 1, when the overload detecting circuit detects an overload state and the input cutoff control transistor 23 becomes forward biased, the signal is changed to the input cutoff control. All the current flows to the transistor 23 side, no signal is input to the voltage amplifier 7, and the power amplification transistor 8 is completely released from the overload state. The overload state of the power amplification transistor 8 of the power amplification circuit 1 is detected, and when the voltage signal H is output from the output terminal (Q) of the flip-flop circuit 17 of the overload detection circuit 2, the power amplification circuit 1 There is a type in which a relay (not shown) is driven by a transistor (not shown) provided to disconnect the output of the power amplifier circuit 1 from the output terminal 9 to protect the power amplifier transistor 8 from an overload state.

[0010]

However, in the above-described power amplifying apparatus, in a high-power power amplifying apparatus in which a plurality of loads (loudspeakers) are connected over a long distance, any one of the plurality of speakers is used. When one of the loudspeakers is short-circuited, the protection circuit that disconnects all the loads connected to the power amplification transistors of the power amplification device operates, and thus has a drawback that it cannot be used for a power amplification device for emergency broadcasting.

In a power amplifying apparatus in which a small output signal is output from a power amplifying transistor in an overload state, since the power supply voltage is constant, the collector loss of the power amplifying transistor is about 1/5 of the maximum power output. Since the maximum value is obtained at the time of output, for example, when an input signal having a large amplitude is input, the amount of heat generated increases or an excessive load is applied to the power amplification transistor. When a signal is output at a low output in an overload state, there is a disadvantage that it is difficult to reduce the load on the power amplification transistor and efficiently output a small output signal.

An object of the present invention is to prevent a power amplifying device connected to a plurality of loads from being destroyed even if any of the plurality of loads becomes abnormal and becomes overloaded. An object of the present invention is to provide a power amplifying device capable of efficiently outputting a small output signal with low power.

[0013]

According to the present invention, there is provided a power amplifying apparatus for amplifying a signal to a plurality of connected loads and supplying the amplified signal to a plurality of connected loads. By comparing the power amplifier circuit that amplifies and outputs power with the amplifier transistor and the output of the power amplifier transistor of the power amplifier circuit and the bias voltage, the signal input to the voltage amplifier when the power amplifier circuit is overloaded is suppressed. An overload detection circuit that detects an amplitude of a signal input to the power amplification transistor from an output of the voltage amplifier, and a pulse width modulation circuit that controls a power supply voltage supplied to the power amplification transistor when the signal has a large amplitude. A power supply voltage control circuit for supplying a power supply voltage to the power amplification circuit. Therefore, even when one of the plurality of loads becomes abnormal and becomes overloaded, the power amplifier can be prevented from being destroyed and a small output signal can be efficiently output with low power.

[0014]

FIG. 1 is a schematic diagram showing a schematic configuration of an embodiment of a power amplifying apparatus according to the present invention. 1, the power amplifier includes a power amplifier circuit 1, an overload detection circuit 2, a pulse width modulation circuit 3, a power supply voltage control circuit 4, and a power supply unit 5.

The power amplifying circuit 1 amplifies a signal input from an input terminal 6 by a voltage amplifier 7, amplifies a signal from the voltage amplifier 7 by a power amplifying transistor 8, and outputs the amplified signal to an output terminal 9. is there. That is, the voltage amplifier 7 applies a constant current to amplify the voltage of the input signal, and the voltage-amplified signal is power-amplified by the power amplification transistor 8.

The overload detection circuit 2 applies a bias voltage set in advance by a resistor 10 to a comparator 12 through an input resistor 11, and its output keeps a low voltage. The feedback resistor 13 sets the gain of the comparator 12 based on the ratio with the input resistor 11. Capacitor 1
Reference numeral 4 determines a time constant based on a product of the detection resistor 15 and the detection resistor 15. With this time constant, the power amplification transistor 8 of the power amplification circuit 1 power-amplifies the large-amplitude input signal within a range not exceeding the safe operation area of the power amplification transistor 8.

The operation of the overload detection circuit 2 will be described. When a large-amplitude input signal is input to the input terminal 6 at the time of overload such as when the output terminals 9 of the power amplifier circuit 1 are short-circuited (short-circuited) or when a large number of nonstandard loads (speakers) are connected, An excessive current flows through the power amplification transistor 8, and the voltage across the emitter resistor 16 of the power amplification transistor 8 increases. The increased voltage is applied to the overload detection circuit 2
Is applied to one input of the comparator 12 through the detection resistor 15. The other input of the comparator 12 receives a preset bias voltage. The comparator 12 compares the two input voltages, and when the voltage across the emitter resistor 16 of the power amplifying transistor 8 of the power amplifying circuit 1 exceeds the bias voltage, the output becomes low (low:
L) The voltage is inverted to a high (high: H) voltage.

The flip-flop circuit 17 has a reset-
It is a set flip-flop circuit. When the power is turned on, the charging current of the initial setting capacitor 18 flows through the initial setting resistor 19, and the flip-flop circuit 17
Is reset (R). The initial setting diode 20 is an element for accelerating the discharge of the initial setting capacitor 18 when the power is turned off, and is for ensuring the initial setting operation when the power is turned on again.

When the output of the comparator 12 is inverted from L to H, the set (S) of the flip-flop circuit 17 becomes H
It becomes a reset state. When the flip-flop circuit 17 is set, the overload detection circuit 2 outputs a voltage signal H from the output terminal (Q).

When the overload detection circuit 2 outputs the voltage signal H, the diode 21 of the power amplification circuit 1
2, the input cutoff control transistor 23 is changed from the reverse bias state to the forward bias state. The reverse bias setting diode 24 and the reverse bias resistor 25 are connected to the overload detection circuit 2.
When the voltage signal L is output from the output terminal (Q) of the flip-flop circuit 17, the input cutoff control transistor 23 becomes forward-biased with respect to the signal voltage applied to the input terminal 6 of the power amplifying circuit 1, thereby causing distortion. A reverse bias is applied to the input cutoff control transistor 23 so as not to become impossible. The signal from the input terminal 6 of the voltage amplifier circuit 1 flows to the input cutoff control transistor 23 side by the input limiting resistor 27 having a lower resistance than the input resistor 26, and the input to the voltage amplifier 7 is cut off. When the input signal is cut off, the power amplifying transistor 8 is released from the overload state, and the output from the output terminal 9 stops. Here, the feedback resistor 28
Sets the gain and the like of the voltage amplifier 7 based on the ratio with the resistor 29.

The pulse width modulation circuit 3 controls the power supply voltage supplied to the power amplification transistor 8 according to the output of the voltage amplifier 7 of the power amplification circuit 1. The output of the voltage amplifier 7 of the voltage amplifying circuit 1 is level-shifted by the resistor 30, peak-rectified by the full-wave rectifier circuit 31, level-shifted by the resistor 32, and input to one of the comparators 33. The transmitter 34 transmits a triangular wave or a sawtooth wave. The output of the transmitter 34 is level-shifted by the resistor 35, and is input to the other of the comparator 33. Comparator 33
Generates and outputs a pulse based on the input from the full-wave rectifier circuit 31 and the transmitter 34. When the output voltage of the voltage amplifier 7 of the power amplifier circuit 1 is high, a pulse with a high duty ratio is output, and when the output voltage of the voltage amplifier 7 is low, a pulse with a low duty ratio is output. The inverter 36 outputs a pulse in which the polarity of the output from the comparator 33 is inverted.

The power supply voltage control circuit 4 uses the two outputs from the pulse width modulation circuit 3 to switch the switching transistor 3
7 and outputs the pulse-controlled output to the smoothing capacitor 3
The power supply voltage supplied to the power amplification transistor 8 of the power amplification circuit 1 is smoothed by the choke coil 39 and the diode 40. For example, when the output voltage of the voltage amplifier 7 of the power amplification circuit 1 is high, the pulse output of the pulse width modulation circuit 3 having a high duty ratio is output from the power supply voltage control circuit 4, that is, the power amplification of the power amplification circuit 1. The power supply voltage of the transistor 8 is set to a high voltage.

The power supply unit 5 is a power supply for the power amplification circuit 1. + BH and -BH are high voltage power supplies of the power amplifier circuit 1, and + BL and -BL are low voltage power supplies of the overload detection circuit 2, the pulse width modulation circuit 3, and the like.

In the embodiment shown in FIG. 1, the power amplification device including the power supply voltage control circuit 4 and the pulse width modulation circuit 3
When the input cutoff control transistor 23 of the power amplification circuit 1 is on, the voltage amplifier 7 has an input resistor 26 and an input limiting resistor 2
The signal level-shifted by the ratio of 7 is added.
Therefore, when the output voltage of the voltage amplifier 7 decreases and the duty ratio of the pulse width of the pulse width modulation circuit 3 decreases, the output voltage of the power supply voltage control circuit 4 decreases and the power amplification circuit 1
The power supply voltage supplied to the power amplifying transistor 8 decreases. As a result, the power amplification transistor 8
Released from abnormal load condition.

FIG. 2 is a schematic diagram showing a schematic configuration of a load device using the power amplifying device of this embodiment. As shown in FIG. 2, a speaker load 44 is connected to the power amplifying device 41 through an output transformer 42 and a switch box 43.
Is connected.

The speaker load 44 has a plurality of speaker units 45. The speaker unit 45 includes a matching transformer 46 and a speaker 47. Each speaker unit 45 is connected by a line 48. There is a route resistance 49 between each speaker unit 45 and the line 48 or between the speaker unit 45 and the speaker unit 45, and the route resistance 49 is the impedance of the wiring used for connection. Speaker load 44
Has a plurality of speaker units 45 connected by a single line 48 and a plurality of the lines 48.

The switch box 43 includes an output transformer 4
2 are provided for each line 48 of the speaker load 44, and the same number of switches are provided for a plurality of lines 48.

The output transformer 43 is a transformer for reducing a power loss or the like due to the line resistance 49 of the speaker load 44, and keeps the power of the power amplifier 41 on the primary side constant, and keeps the signal on the secondary side high. The output voltage is output at a low current.

The case where the speaker load 44 is connected to the power amplifier 41 shown in FIG. 2 and the power amplifier 41 is overloaded will be described. FIG. 3 is a schematic diagram illustrating an overload state when one speaker load is connected to the power amplifying device of the present embodiment. In FIG.
When the speaker load 44 having one speaker 47 is connected to the power amplifying device 41, a plurality of places (short points 50) where an overload state occurs can be considered. Regardless of the short-circuit point 50 shown in FIG. 3, no signal is output from the speaker 47 because the short-circuit occurs before the speaker 47. When the speaker load 44 is overloaded, the power amplifier 41
Then, the protection circuit operates to protect the power amplification transistor 8 from destruction. Since the wiring distance between the power amplifying device 41 and the speaker 47 of the speaker load 44 is short, the route resistance 49 is low, and the short circuit at the short point 50 affects the power amplifying device 41 almost equally. is there.

Next, an overload state of the power amplifying device 41 in a state where the speaker load 44 having a plurality of speaker units 45 is connected to the power amplifying device 41 will be described. FIG. 4 is a schematic diagram illustrating an overload state when a plurality of speaker loads are connected in the power amplifying device of the present embodiment. In FIG. 4, no signal is output from the speaker 47 in any case of the short point 50. In the case of the connection state shown in FIG. 4, the line resistance 49 increases because the wiring distance of the speaker 47 is long, and the inductance component and the capacitance component are also included as impedance components. The resistance 49 becomes high resistance. However, the impedance of the speaker load 44 in the overload state is lower than the impedance of the speaker load 44 not in the overload state.

Also, by using a negative feedback amplifier (not shown) for the power amplifying device 41, the output impedance of the power amplifying device 41 decreases in proportion to the amount of negative feedback. The signal source impedance of the power amplifying device 41 and the rated speaker load impedance have a ratio of about 1 to 10 or more. Therefore, even if a part of the line 48 of the speaker load 44 is short-circuited to lower the impedance, the power amplifier 41
As long as the power supply does not completely shut off the output, the output voltage can supply power to the speaker 47 connected before the short point 50.

Therefore, the power amplifying device 41 can set a small output state in a range that does not destroy even if the speaker load 44 is completely short-circuited, and controls the output state to the set output state even when the protection circuit is activated. A small output signal can be output from the speaker 47 upstream of the connected short point 50.

FIG. 5 is a schematic diagram showing an equivalent circuit in an overload state when a plurality of speaker loads are connected in the power amplifying apparatus of the present embodiment. In FIG. 5, the power amplifying device 41 outputs a signal source voltage E1 of the power amplifying device 41,
It has a signal source impedance R0. Speaker load 44
Has a speaker impedance RL. Each speaker 47 is connected in plurality,
The line resistors 49 are connected by a line 48 having a line resistance impedance RI. The voltage E2 is the power amplifier 4
1 is the voltage across the output terminal of the power amplifier 41 when the speaker load 44 is connected. The voltage E3
Is the voltage across the speaker load 44.

When the speaker load 44 is in the normal state, since R0 <RI <RL (1), E1 ≒ E2 ≒ E3 (2).

When the speaker load 44 is overloaded, that is, when one of the plurality of speakers 47 (impedance RL) is short-circuited, the voltage applied to the other speaker 47 is R0 <RI <RL (3) E2 = E1 * (RI + RL) / (R0 + RI + RL) ＲE1 * RL / RL (4), and E1 ≒ E2 ≒ E3 (5) That is, the output voltage does not change even when a short circuit occurs.

As described above, in a power amplifying apparatus in which a plurality of speakers are connected over a long distance and the speakers are driven by a large amount of power, when one of the plurality of connected speakers is in a state such as a short circuit or the like. However, the protection circuit that suppresses the power consumption of the power amplifier operates by limiting the voltage of the input signal by level shifting to limit the output to a small output and controlling the supply voltage to the power amplifier to the minimum necessary low voltage.
It is possible to output a signal from a speaker that is not in any other state as long as the power amplifier is not destroyed.

Further, since the voltage of the input signal is low and the supply voltage of the power amplifier is also low, the power consumption of the power amplifier is greatly reduced. Even when the load impedance of the output is lower than the standard value and the input signal is large, The protection circuit operates to level shift the voltage of the input signal to a small output and reduce the supply voltage of the power amplifier to reduce the power consumption of the power amplifier.

[0038]

According to the present invention, in a power amplifier connected to a plurality of loads, even if any of the plurality of loads becomes abnormal and becomes overloaded, the power amplifier is prevented from being destroyed. In addition, a small output signal can be efficiently output with low power.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of one embodiment of a power amplifying device of the present invention.

FIG. 2 is a schematic diagram showing a schematic configuration of a load device using the power amplifying device of the present embodiment.

FIG. 3 is a schematic diagram illustrating an overload state when one speaker load is connected in the power amplifying device of the present embodiment.

FIG. 4 is a schematic diagram illustrating an overload state when a plurality of speaker loads are connected in the power amplifying device of the present embodiment.

FIG. 5 is a schematic diagram showing an equivalent circuit in an overload state when a plurality of speaker loads are connected in the power amplifying device of the present embodiment.

FIG. 6 is a schematic diagram showing a schematic configuration of a conventional power amplifying device.

[Explanation of symbols]

1 power amplification circuit, 2 overload detection circuit, 3 pulse width modulation circuit, 4 power supply voltage control circuit, 5 power supply section, 6 input terminals, 7 voltage amplifier, 8 power amplification transistor,
9 output terminal, 10 resistor, 11 input resistor, 12 comparator, 13 feedback resistor, 14 capacitor, 15 detection resistor, 16 emitter resistor, 17 flip-flop circuit, 18 initial set capacitor, 19 initial set resistor, 20 initial set Diode, 21 diode, 22 buffer resistor, 23 input cutoff control transistor, 24 reverse bias setting diode, 25 reverse bias resistor, 2
6 input resistance, 27 input limiting resistance, 28 feedback resistance, 29 resistance, 30 resistance, 31 full-wave rectification circuit, 32 resistance, 33 comparator, 34 transmission circuit, 35 resistance, 36 inverter, 37 switching transistor, 38 smoothing capacitor, 39 Choke coil, 40 diode, 41 power amplifier, 42
Output transformer, 43 switch box, 44 speaker load, 45 speaker unit, 46 matching transformer, 47 speakers, 48 lines, 49 line resistance, 50 short points.

Claims (1)

[Claims] A power amplifying circuit for power amplifying and supplying a signal to a plurality of connected loads, and a power amplifying circuit for amplifying an input signal with a voltage amplifier, amplifying the power with a power amplifying transistor, and outputting the amplified signal. An overload detection circuit that compares an output of a power amplification transistor of a power amplification circuit with a bias voltage and suppresses a signal input to the voltage amplifier when the power amplification circuit is overloaded; and an output of the voltage amplifier. A pulse width modulation circuit for detecting the amplitude of a signal input to the power amplification transistor from the power amplifier and controlling a power supply voltage supplied to the power amplification transistor when the signal has a large amplitude; and supplying a power supply voltage to the power amplification circuit. A power amplification device comprising: a power supply voltage control circuit.