JPH10256533A - Compound semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the source and drain resistances by forming a first InGaP compd. semiconductor layer between a semiconductor substrate and channel layer, and forming an Ohmic contact layer contg. an n-type impurity, adjacent to the first semiconductor layer and channel layer. SOLUTION: A device is produced by forming on a semi-insulative substrate 101, a buffer layer 102, first InGaP compd. semiconductor regrown surface layer 103, buffer layer 104, second InGaAs compd. semiconductor channel layer 105, spacer layer 106, electron feed layer 107, Schottky contact layer 108, gate electrode 111, and insulation film 112, etching with this film 112 used for a mask to form a mesa gate electrode region laminate, and forming an n-type impurity-contg. GaAs Ohmic contact layer 109, InGaAs Ohmic contact layer 110, drain electrode 113 and source electrode 114.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor using a compound semiconductor as a constituent material and a method for manufacturing the same, and more particularly to a high electron mobility transistor (HEMT) and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor (FE) has been used.
As one type of T), on a semi-insulating GaAs substrate, a non-doped InGaAs channel layer and an electron supply layer made of a semiconductor such as AlGaAs or InGaP doped with a high concentration of n-type impurities having a smaller electron affinity than InGaAs. 2. Description of the Related Art A high electron mobility transistor (hereinafter, referred to as a HEMT) having a hetero abutment is known. H
A feature of the EMT is that a two-dimensional electron gas (2DE) having a high electron mobility formed in a high-purity InGaAs channel layer is used.
By using G) as a carrier, high speed and noise characteristics are excellent.

On the other hand, in order to realize high performance of a field effect transistor, it is necessary to reduce a gate length, a gate resistance, a source resistance, and other parasitic resistances and capacitances. Therefore, in this type of field effect transistor, a T-shaped gate electrode is often used to reduce the gate length and the gate resistance. FIG. 9 shows a conventional I
FIG. 3 is a diagram showing a cross-sectional structure of a HEMT using nGaP as an electron supply layer.

[0004] In such a HEMT manufacturing method, first, a non-doped GaAs buffer layer 502 and a non-doped InGaAs channel layer 50 are formed on a semi-insulating GaAs substrate 501 by metal organic chemical vapor deposition (MOCVD) or the like.
3, non-doped InGaP spacer layer 504, Si-doped n-type InGaP electron supply layer 505, non-doped InG
An aP short key contact layer 506 and a Si-doped n-type GaAs ohmic contact layer 507 are sequentially grown. Next, the drain electrode 508 and the source electrode 509 are formed apart from each other by an electrode metal vapor deposition and alloying process by photolithography. Thereafter, a recess 510 having a concave groove shape is formed in the n-type GaAs ohmic contact layer 507 partially exposed by the electron beam exposure, and the surface of the non-doped InGaP Schottky contact layer is exposed, and a gate electrode 511 is formed thereon. .

In the conventional HEMT having such a structure, wet etching using an etchant is mainly used for forming the recess 510, and it is difficult to control the depth direction and the width direction of the recess 510, thereby lowering the manufacturing yield. Caused a rise in costs. A gate electrode 511 serving as a shot key electrode is formed on the surface exposed by wet etching.
When formed, the surface state is liable to change, and this has been a factor that causes deterioration of characteristics such as an increase in gate leak current.

In this type of transistor,
There are so-called parasitic resistances such as a source resistance and a drain resistance. When these resistances increase, the operating frequency band, noise characteristics, and reliability are reduced. On the other hand,
If these parasitic resistances are reduced, there arises a problem that a sufficient gate-drain breakdown voltage (breakdown voltage) cannot be obtained. For example, in order to improve the gate-drain breakdown voltage, a gate electrode is provided at a position near the source electrode 509 at the bottom of the recess 510 and the drain electrode 508 is formed.
If the gate electrode 511 is to be kept away from the GaAs ohmic contact layer 5 on the source electrode 509 side,
07 occurs. Further, the gate electrode 511 and the ohmic contact layer 50 having a high impurity concentration are formed.
As the distance from the gate electrode 7 decreases, the parasitic capacitance of the gate increases and the high-frequency characteristics deteriorate. Further, if the height and width of the head are increased by lowering the legs of the gate electrode in order to reduce the gate resistance, various problems such as the above problem become more remarkable.

[0007] In order to improve the problem peculiar to the HEMT having such a recess structure, a HEMT structure in which a portion other than a region where a gate electrode is formed is removed by etching and buried with a low resistance layer has been proposed. I have. For example,
JP-A-2-143432, JP-A-5-13467, JP-A-6-216160, JP-A-6-34211 and the like. FIG. 10 shows the structure of a HEMT according to JP-A-6-342811 as a representative example. Semi-insulating GaAs substrate 60
1 and an undoped GaAs buffer layer 602 having a thickness of about 500 nm, a first semiconductor layer (corresponding to the channel layer 503 in FIG. 9) 603 made of an undoped GaAs layer having a thickness of about 50 nm, and a film thickness of about 40 nm. , Donor density is about 2
A second semiconductor layer 604 (corresponding to the electron supply layer 505 in FIG. 9) made of an n-type AlGaAs layer of × 10 ¹⁸ cm ^−3, a thickness of about 100 nm, and a donor density of about 4 × 10 ¹⁸ cm ⁻³
A third semiconductor layer (corresponding to the ohmic contact layer 507 in FIG. 9) 605 made of an n-type GaAs layer, a gate electrode 606 made of WSi, a source electrode 608 and a drain electrode 607 made of AuGe / Ni / Au, and SiO2 It is formed from an insulating film below a gate electrode eave. The first semiconductor layer and the second semiconductor layer are formed so as to be in electrical contact with the low-resistance third semiconductor layer.

[0008]

According to the conventional HEMT having the structure as shown in FIG. 10, since recess etching is not performed, improvement in recess yield and reduction in gate leak current can be expected. Further, by embedding with a low resistance layer, the source resistance and the drain resistance can be reduced, and improvement of high frequency characteristics can be expected. However, the HEMT having such a structure has many problems in the manufacturing process. That is, the Al that becomes the second semiconductor layer
Selective dry etching is possible with AlGaAs having a high composition, but a GaAs layer serving as a first semiconductor layer or InG
Since there is almost no selectivity in the wet etching of the aAs layer, there is a problem that the etching depth (the thickness of the buried layer) and the recess width vary greatly in the plane of the wafer. In particular, when a large-diameter GaAs substrate is used, the etching depth is not uniform, and a completely flat surface cannot be obtained after etching, so that the distance between the gate and the source or drain electrode fluctuates. In addition, the drain resistance may fluctuate for each element formed at a different location on the wafer, or the gate-drain breakdown voltage may be reduced. For these reasons, high-frequency characteristics and noise characteristics cannot be sufficiently improved. Also, improvement in product yield cannot be expected.

Therefore, the present invention solves the above-mentioned problems of the HEMT device, and has a HEMT having a low source resistance, a low drain resistance and a high gate-drain breakdown voltage.
It is an object of the present invention to provide a method for manufacturing an element with a high yield and an element structure enabling the method.

[0010]

According to a first embodiment of the present invention, a first compound semiconductor layer containing In, Ga, and P is formed on a semiconductor substrate, and the first compound semiconductor layer is formed on the first compound semiconductor layer. , Directly or via a buffer layer, at least Ga
Forming a channel layer made of a second compound semiconductor layer containing Al and As, laminating an electron supply layer and a Schottky contact layer on the channel layer, and forming a channel layer on the Schottky contact layer. Forming a mesa-shaped gate electrode region laminate by performing an etching process toward the first compound semiconductor layer via a mask; and forming the first compound exposed on both sides of the mesa-shaped gate electrode region laminate. Growing an ohmic contact layer made of a semiconductor containing an n-type impurity on the semiconductor.

In the compound semiconductor device manufactured according to the first embodiment, a gate electrode made of a refractory metal is formed on the Schottky contact layer, and the ohmic contact on the source electrode side is self-aligned with the gate electrode. A layer is formed, and the distance between the gate electrode and the ohmic contact layer on the source electrode side is shorter than the distance between the gate electrode and the ohmic contact layer on the drain electrode side.

Further, the compound semiconductor device manufactured according to the first embodiment has a channel layer formed on a semi-insulating semiconductor substrate, and a channel layer formed between the semi-insulating semiconductor substrate and the channel layer. An InGaAlP layer, an electron supply layer having an electron affinity smaller than that of the channel layer containing an n-type impurity, a Schottky contact layer having an electron affinity smaller than that of the channel layer, and an n formed in contact with the InGaAlP layer and the channel layer. An ohmic contact layer comprising a low-resistance semiconductor layer containing a semiconductor impurity and having a higher electron affinity than that of the Schottky contact layer. A drain electrode and a source electrode are formed on the ohmic contact layer. Next, according to the second embodiment of the present invention, when the ohmic contact layer, which is a low-resistance semiconductor layer, is regrown, the surface of the semiconductor layer exposed adjacent to the gate electrode region laminate is insulated. A manufacturing method is employed in which the film is covered with a film and epitaxially grown laterally from both side walls of the gate electrode region laminate. By employing this method, it is possible to reduce the introduction of crystal defects and deep energy levels that are likely to occur between the regrowth region and the side walls of the gate electrode region stack.

The compound semiconductor device manufactured according to the second embodiment has a gate electrode made of a high melting point metal, and a low resistance semiconductor layer forming a source electrode and a drain electrode is formed by regrowth. Since a material serving as a mask during regrowth remains between the semiconductor substrate and the regrown layer, parasitic capacitance between the semiconductor substrate and the regrown layer can be reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view schematically showing a configuration of a HEMT according to a first example of the first embodiment of the present invention. This HEMT is manufactured by metal organic chemical vapor deposition (MO)
The non-doped GaAs buffer layer 10 of 500 nm is formed on the semi-insulating GaAs substrate 101 by CVD.
2, 100 nm non-doped In _0.48 Ga _0.52 P regrowth surface layer 103, 20 nm non-doped GaAs buffer layer 104, 10 nm non-doped In _0.22 Ga _0.78 As
Channel layer 105, 3 nm non-doped In _0.3 Ga
_0.7 P spacer layer 106, Si surface density Ns = 3 × 10 ¹²
Electron supply layer 1 consisting of a planar doping layer of cm ⁻²
07, 15 nm non-doped In _0.48 Ga _0.52 P Schottky contact layer 108, In _0.48 Ga _0.52 P regrown surface layer 103 and In _0.22 Ga _0.78 As channel layer 105
Si-doped n-type GaAs ohmic contact layer 109 of 45 nm and N _D = 5 × 10 ¹⁸ cm ⁻³ , 5 nm
And N _D = 5 × 10 ¹⁹ cm ⁻³ Te-doped n-type In _0.5 G
a _0.5 As ohmic contact layer 110 is grown.
A gate electrode 111 and an insulating film 112 are formed on the In _0.48 Ga _0.52 P Schottky contact layer 108,
_A drain electrode 113 and a source electrode 114 are formed on the _0.5 Ga _0.5 As ohmic contact layer 110.

In the above embodiment of the present invention, In
_{The 0.48} Ga _0.52 P regrowth surface layer 103 may be made of an InGaAlP material that is substantially lattice-matched with a GaAs substrate.
A layer containing Al such as _0.48 (Ga _0.6 Al _0.4 ) _0.52 P may be used. In _0.22 Ga _{0.78 In of the} channel layer 105
The composition y may be in the range of y = 0.22 ± 0.1.
The In composition z of the In _0.3 Ga _0.7 P spacer layer 106 may be in the range of z = 0.2 to 0.6. The spacer layer 106 and the shot key contact layer 108 are made of In.
GaAlP material, for example, In _0.48 (Ga
_0.6 Al _0.4) may be a material such as _{0. 52} P, AlGa
As may be used. When using AlGaAs, the Al composition x
It is appropriate that x is about 0.15 to 0.3. In _0.5
The In composition w of the Ga _0.5 As ohmic contact layer 110 may be in the range of w = 0.2 to 1.0.

Next, a method of manufacturing the above HEMT will be described. As shown in FIG. 2A, semi-insulating GaAs
On a substrate 101, a GaAs buffer layer 102, In _0.48
Ga _0.52 P regrowth surface layer 103, GaAs buffer layer 1
04, In _0.22 Ga _0.78 As channel layer 105, In
_{A 0.3} Ga _0.7 P spacer layer 106, a planar doping layer 107, and an In _0.48 Ga _0.52 P short key contact layer 108 are sequentially formed by MOCVD.

Next, as shown in FIG.
After forming an insulating film 112a such as O ₂ or SiN, only part of the surface of the Schottky contact layer 108 is exposed by electron beam exposure, and a gate electrode 111 is formed thereon. As a gate electrode metal, WSi
Was used. As the gate electrode, other WTi, WN, W
For example, a high melting point metal such as The gate length d _l is 0.
It was 1 μm. Since the gate electrode is formed not on the surface exposed by wet etching but on the outermost growth surface,
There is an advantage that the surface state is always stable. It was confirmed that the gate leakage current was reduced by 50% or more as compared with the case where wet recess etching was used, and the yield at the time of forming the gate electrode was improved. After that, an insulating film 112b serving as a mask for regrowth is formed, and portions other than the vicinity of the gate electrode are removed as shown in FIG. In order to form the ohmic contact layer on the source electrode side in a self-aligned manner with the gate electrode, the insulating film 112 on the source electrode side is formed.
b is removed leaving only on the gate electrode. In order to make the distance between the gate electrode and the ohmic contact layer on the source electrode side shorter than the distance between the gate electrode and the ohmic contact layer on the drain electrode side, the insulating film 11 on the drain electrode side is used.
In 2a and 112b, portions other than the gate electrode portion are left.
At this time, the dimension of the absolute green film was d ₂ = 0.25 μm. d ₃ =
It was 0.50 μm.

As shown in FIG. 2C, etching is performed so that the In _0.48 Ga _0.52 P regrowth surface layer 103 is exposed using the insulating film 112 as a mask. In _0.3 Ga _0.7 P
Spacer layer 106, planar doping layer 107, I
A mixed solution of hydrochloric acid and phosphoric acid was used for etching the n _0.48 Ga _0.52 P short key contact layer.

Next, the GaAs buffer layer 104, In
_For etching the _0.22 Ga _0.78 As channel layer 105,
A mixture of sulfuric acid, hydrogen peroxide and water was used. In this sulfuric acid-based mixed solution, InGaP is hardly etched and GaAs
Selective etching with s is possible. Therefore, the in-plane distribution of the etching depth (the thickness of the buried layer) and the recess width could be almost eliminated over the entire surface of the large-diameter wafer.

Next, as shown in FIG. 2D, GaAs is formed on the In _0.48 Ga _0.52 P regrowth surface layer 103 by MOCVD.
The ohmic contact layer 109 and the InGaAs ohmic contact layer 110 are regrown. Regrowth temperature is 50
0 ° C. Since a high melting point metal was used for the gate electrode, no degradation of the Schottky characteristics occurred even after a high temperature process by regrowth, and no increase in gate leak current was observed. Since a low melting point metal such as Ti diffuses into the semiconductor film even at the regrowth temperature, it is necessary to use a high melting point metal in the device structure for performing the regrowth as in this embodiment. At the time of regrowth, no growth occurs in the portion of the insulating film 112, and only the etched portion selectively grows and is buried. And the In _0.48 Ga _0.52 P regrown surface layer is cleaned by etching with sulfuric acid-based mixture, by a surface oxide film in InGaP is not easily formed as compared with GaAs, better surface than regrowth I got the morphology. Buried layer thickness (GaAs
s ohmic contact layer 109 and In _0.5 Ga _0.5 A
The sum of the thickness of the s ohmic contact layer 110 (the thickness of the GaAs buffer layer 104,
n _0.22 Ga _0.78 As channel layer 105, In _0.3 Ga
_0.7 P spacer layer 106, planar doping layer 10
7, In _0.48 Ga _0.52 P Schottky contact layer 10
8 sum). The In _0.5 Ga _0.5 As ohmic contact layer 110 may not be provided, but is preferably provided to reduce the contact resistance between the drain electrode and the source electrode.

Thereafter, the drain electrode 113 and the drain electrode 113 are formed by photolithography, electrode metal deposition and alloying steps.
Then, the source electrode 114 is formed to be separated as shown in FIG. Through these steps, a HEMT structure as shown in FIG. 1 is created. The effect of the thickness of the regrown buried layer will be described with reference to FIG. As shown in FIG. 3A, when only the In _0.3 Ga _0.7 P spacer layer 106, the planar doughpin layer 107, and the In _0.48 Ga _0.52 P short key contact layer 108 were etched, the thickness of the buried layer was removed by etching. If it is the same as the thickness of the layer, it will be 20 nm. The N _D = 5 × 10 ¹⁸ Si-doped n-type GaAs ohmic contact layer 109 of cm ^-3 15
nm, N _D = 5 × 10 ¹⁹ cm ⁻³ Te-doped n-type In
_0.5 Ga _0.5 As ohmic contact layer 110 is 5 n
In the case of m growth, the buried layer has a high sheet resistance of 300 Ω / port or more. This means that the thickness of the buried layer is 2
This is because it is as thin as 0 nm. In order to reduce the source resistance and the drain resistance, the sheet resistance of the ohmic contact layer needs to be 200 Ω / port or less, preferably 120 Ω / port or less. When the carrier concentration of GaAs is N _D =
In the case of 5 × 10 ¹⁸ cm ⁻³ , the sheet resistance is 200 Ω /
The thickness of the buried layer should be 30 nm or more and 12
In order to make it 0 Ω / port or less, it is necessary to make it 50 nm or more. To reduce the sheet resistance, there is a method of increasing the carrier concentration of the ohmic contact layer.
For Si-doped GaAs grown by CVD, N _D = 5 × 10 ¹⁸
Further doping above cm ^-3 is not possible because of significant degradation of the morphology.

On the other hand, as shown in FIG. 3B, a method of growing the buried layer so that the thickness of the buried layer is larger than the thickness of the layer removed by etching can be considered. However, such a shape causes problems such as the gate electrode 111 and the In _0.5 Ga _0.5 As ohmic contact layer 110 being in contact with each other. Also,
When the distance between the gate electrode and the ohmic contact layer having a high impurity concentration is reduced, the parasitic capacitance of the gate is increased, and there is a disadvantage that the high frequency characteristics are deteriorated. For this reason, the thickness of the buried layer is not problematic as long as it is about 5 nm thicker than the thickness of the layer removed by etching, but it is necessary that it be about the same. With a structure in which the ohmic contact layer and the Schottky contact layer are substantially on the same plane, the distance between the gate electrode and the ohmic contact layer can be sufficiently increased, and the conventional structure as shown in FIG. The gate parasitic capacitance can be significantly reduced as compared with the HEMT. In order to suppress the short channel effect and increase the maximum gain Gm, the shorter the distance between the two-dimensional electron gas and the Schottky contact, the better. Spacer layer, electron supply layer,
It is advantageous that the sum of the thicknesses of the shot key contact layers is small. That is, when the channel layer is left as shown in FIG. 3, the thickness of the buried layer is further reduced, the sheet resistance of the ohmic contact layer is reduced, and the distance between the good electrode and the ohmic contact layer is not reduced. I can't do that. However, as in the embodiment of the present invention, InG is provided between the semiconductor substrate and the channel layer.
Forming the aAlP regrowth surface layer and etching to form the buried layer makes it possible for the first time to achieve both reduction in sheet resistance and reduction in gate parasitic capacitance. By changing the thickness of the GaAs buffer layer 104, the sheet resistance can be reduced. In this embodiment, the sheet resistance is set to 120Ω by setting the thickness of the GaAs buffer layer to 20 nm.
/ Mouth and very low value. As the thickness of the buried layer increases, the sheet resistance decreases but the time required for regrowth increases, and Si diffusion from the planar doping layer occurs. Therefore, it has been experimentally confirmed that a thickness of about 100 nm or less is appropriate. As described above, the thickness of the buried layer is at least 30 n due to the combination with the sheet resistance.
m or more, preferably 50 nm or more, and about 10
It has been clarified that the element performance can be improved by setting the thickness to 0 nm or less.

In the HEMT having the cross-sectional structure as shown in FIG. 1, the characteristics of the device having a gate width of 200 μm were evaluated.
The gate-drain breakdown voltage was 10 V, the source resistance was 1Ω, and the drain resistance was 2Ω. The conventional HEM shown in FIG.
By making the distance between the gate electrode and the ohmic contact layer on the drain electrode side twice as large as T, the withstand voltage was improved by 5 V or more. The source resistance decreased by 2Ω or more, and the drain resistance decreased by 1Ω or more, and significant improvements were observed. It has been confirmed that such a reduction in source resistance / drain resistance and gate parasitic capacitance leads to excellent high frequency characteristics. 160 GH as the maximum oscillation frequency fmax
z was obtained, which was improved by 30 GHz or more. There was no deterioration during the operation of the device, and the reliability was improved.

FIG. 4 is a sectional view schematically showing a configuration of a HEMT according to a second example of the first embodiment of the present invention. This HEMT is manufactured by metal organic chemical vapor deposition (MO)
A 500 nm non-doped GaAs buffer layer 20 is formed on the semi-insulating GaAs substrate 201 by CVD.
2, 100 nm undoped In _0.48 Ga _0.52 P regrowth surface layer 203, 10 nm undoped In _0.22 Ga _0.78
As channel layer 204, 3 nm non-doped In _0.3 G
a _0.7 P spacer layer 205, N _D = 4 × 10 at 10 nm
¹⁸ cm ⁻³ Si-doped n-type In _0.48 Ga _0.52 P electron supply layer 206, 10 nm non-doped In _0.48 Ga _0.52 P Schottky contact layer 207, In _0.48 Ga _0.52 P regrown surface layer 203 and In _0.22 Ga _0.78 As channel Layer 2
Si of 30 nm and N _D = 5 × 10 ¹⁸ cm ^-3
Doped n-type GaAs ohmic contact layers 208, 3
Te doped n-type In with N _D = 5 × 10 ¹⁹ cm ^{−3 in} nm
_{A 0.5} Ga _0.5 As ohmic contact layer 209 is grown. In _0.48 Ga _0.52 P Schott key contact layer 2
A gate electrode 210 and an insulating film 211 are formed on the gate electrode 07 and the In _0.5 Ga _0.5 As ohmic contact layer 20.
On 9, a drain electrode 212 and a source electrode 213 are formed. The manufacturing method was made in the same procedure as the method shown in FIG.

In the above-described embodiment of FIG. 1, the planar doping layer 107 as the electron supply layer has a thin surface structure, whereas in this embodiment, In _0.48
The difference is that the thickness of the Ga _0.52 P electron supply layer 206 is increased to 10 nm, and that the GaAs buffer layer 104 in the embodiment of FIG. 1 is not formed. GaAs
The reason that the s buffer layer 104 is not formed is that In
_{This is} because the thickness of the _0.48 Ga _0.52 P electron supply layer 206 is increased to 10 nm, so that the thickness of the buried layer is substantially the same as that in the embodiment of FIG.

In the embodiment of the present invention, similarly to the above-described embodiment, the In _0.48 Ga _0.52 P regrown surface layer 203 is formed of InGaAs substantially lattice-matched to the GaAs substrate.
Any material can be used as long as the material is InP, In _0.48 (Ga _0.6 Al _0.4 )
A layer containing Al such as _0.52 P may be used. In _0.22 Ga _0.78
The In composition y of the As channel layer 204 is y = 0.22 ±
It may be in the range of 0.1. The In composition z of the In _0.3 Ga _0.7 P spacer layer 205 may be in the range of z = 0.2 to 0.6. Spacer layer 205, electron supply layer 206,
The shot key contact layer 207 is made of an InGaAlP material, for example, In _0.48 (Ga _0.6 Al _0.4 ) containing Al.
A material such as _0.52 P or AlGaAs may be used.
When using AlGaAs, the Al composition X is x = 0.1
About 5 to 0.3 is appropriate. The In composition w of the In _0.5 Ga _0.5 As ohmic contact layer 209 is w = 0.2
It may be in the range of ~ 1.0.

In a HEMT having a sectional structure as shown in FIG. 4, the characteristics of the device having a gate width of 200 μm were evaluated.
The Goutow drain withstand voltage was as good as 12 V, the source resistance was 1 Ω, and the drain resistance was 2 Ω. Compared with the conventional HEMT, a great improvement was observed, and it was confirmed that the high frequency characteristics and the reliability were excellent.

FIG. 5 is a sectional view schematically showing the configuration of a HEMT according to a third embodiment of the first embodiment of the present invention. This HEMT is manufactured by metal organic chemical vapor deposition (MO)
A 500 nm non-doped GaAs buffer layer 30 is formed on a semi-insulating GaAs substrate 301 by CVD.
2, 10 nm non-doped In _0.48 Ga _0.52 P layer 30
Si-doped n with N _D = 4 × 10 ¹⁸ cm ⁻³ at 4,10 nm
Type In _0.48 Ga _0.52 P electron supply layer 305, 3 nm non-doped In _0.3 Ga _0.7 P spacer layer 306, 10 nm
Non-doped In _0.22 Ga _0.78 As channel layer 307,
3 nm non-doped In _0.3 Ga _0.7 P spacer layer 30
8, 10 nm, ND = 4 × 10 ¹⁸ cm ⁻³ Si-doped n
Type In _0.48 Ga _0.52 P electron supply layer 309,10nm of undoped In _{0. 48} Ga _0.52 P Shi yacht key contact layer 310, In _0.3 Ga _0.7 P spacer layer 306 and the In
_{In contact with 0.22} Ga _0.78 As channel layer 307, 30 nm ND = 5 × 10 ¹⁸ cm ^-3 Si-doped n-type GaAs ohmic contact layer 311, ₃ nm N _D = 5 × 10 ¹⁹ c
A m ⁻³ Te-doped n-type In _0.5 Ga _0.5 As ohmic contact layer 312 is grown. The gate electrode 313 is formed on the In _0.48 Ga _0.52 P Schottky contact layer 31O.
And an insulating film 314 are formed. On the In _0.5 Ga _0.5 As ohmic contact layer 312, a drain electrode 315 and a source electrode 316 are formed. This embodiment has a double hetero structure, and has a non-doped In _0.3 Ga _0.7
The P spacer layer 306 also serves as a regrowth surface layer. This structure was created by the same procedure as the method shown in FIG.

In this embodiment, In _0.22 G
The In composition y of the a _0.78 As channel layer 307 is y = 0.
It may be in the range of 22 ± 0.1. In _0.3 Ga _0.7 P
The In composition z of the spacer layers 306 and 308 is z = 0.2
It may be in the range of 0.6. Spacer layers 306, 30
8, the electron supply layer 305,309, shea yacht key contact layer 310, InGaAlP material, for example, also may a material such as _{In 0.48 (Ga 0.6 Al 0.4)} 0.52 P containing Al, may be AlGaAs. When AlGaAs is used, it is appropriate that the Al composition x is about x = 0.15 to 0.3. In composition W of In _{0. 5} Ga _0.5 As ohmic contact layer 312 may be in the range of w = 0.2 to 1.0.

In the HEMT having the sectional structure as shown in FIG. 5, the gate-drain breakdown voltage, the source resistance, and the drain resistance are greatly improved as compared with the conventional HEMT.
It was confirmed that the high frequency characteristics and the reliability were also excellent.

FIG. 6 is a cross-sectional view schematically showing a configuration of a HEMT according to a fourth example of the first embodiment of the present invention. This HEMT is a metal organic chemical vapor deposition (MOC)
VD method) on a semi-insulating GaAs substrate 401
500 nm non-doped GaAs buffer layer 402, 1
00 nm non-doped In _0.48 Ga _0.52 P regrowth surface layer 403, 10 nm non-doped GaAs buffer layer 40
4, 50 nm non-doped Al _0.2 Ga _0.8 As layer 40
Si-doped n-type Al _0.2 Ga _0.8 As electron supply layer 406 with N _D = 2 × 10 ¹⁸ cm ⁻³ at 5 and 5 nm, ³ nm non-doped Al _0.2 Ga _0.8 As layer spacer layers 407 and 15
nm non-doped In _0.15 Ga _0.85 As channel layer 40
8, 3 nm non-doped Al _0.2 Ga _0.8 As spacer layer 409, electron supply layer 410 consisting of a planar doping layer with Si surface density Ns = 5 × 10 ¹² cm ⁻² , 10 nm
And N _D = 5 × 10 ¹⁷ cm ⁻³ Si dove Al _0.2 Ga
_0.8 As short-cut key contact layer 411, In _0.3 G
N _D = 5 × 10 ¹⁸ c at 96 nm in contact with the a _0.7 P regrowth surface layer 403 and the In _0.15 Ga _0.85 As channel layer 408
An m- ³ Si-doped n-type GaAs ohmic contact layer 412 is grown. A gate electrode 413 and an insulating film 4 are formed on the Al _0.2 Ga _0.8 As short-circuit key contact layer 411.
14 is formed, and the GaAs ohmic contact layer 41 is formed.
On 2, a drain electrode 415 and a source electrode 416 are formed. This embodiment uses AlG instead of the InGaP layer.
It has a double hetero structure using an aAs layer.
Was prepared in the same manner as the method shown in FIG.

In the above embodiment, In _0.15 Ga
_0.85 The In composition y of the As channel layer 408 is y = 0.1
It may be in the range of 5 ± 0.1. Spacer layers 407, 4
09, the electron supply layer 406, the Schottky key contact layer 4
11 is an InGaAlP material, for example, In _0.3 Ga
_0.7 P, In _0.48 Ga _0.52 In _0.48 (G
a _0.6 Al _0.4 ) A material such as _0.52 P may be used. AlGa
When As is used, the Al composition X is such that x = 0.15-0.
It suffices if it is in the range of 3.

In the HEMT having the cross-sectional structure shown in FIG. 6, the gate-drain breakdown voltage, the source resistance, and the drain resistance are greatly improved as compared with the conventional HEMT.
It was confirmed that the high frequency characteristics and the reliability were also excellent.

FIG. 7 is a schematic sectional view showing a first example of the heterojunction field effect transistor according to the second embodiment of the present invention. Semi-insulating G having (001) crystal plane
A non-doped GaAs buffer layer 702 and a non-doped InGa are formed on an aAs substrate 701 by metal organic chemical vapor deposition.
An As channel layer 703, a non-doped AlGaAs spacer layer, and a Si-doped AlGaAs electron supply layer 704 are grown. Trimethyl gallium (CH ₃ ) ₃
Ga, trimethyl aluminum (CH ₃ ) ₃ Al, trimethyl indium (CH ₃ ) ₃ In, arsine As
H ₃ and disilane Si ₂ H ₆ are used as a dopant material (FIG. 7A). On top of this, a 200 nm thick WSiN
After the gate electrode 705 made of
An SiO ₂ layer 706 is formed. After removing WSiN and SiO ₂ 706 while leaving the gate portion by lithography, SiO ₂ is again vapor-deposited on the entire surface, the gate electrode portion is covered with a resist, and then anisotropic dry etching is performed to form a sidewall 707. (FIG. 7-b).

[0036] _{Then, H 3 P0 4, H 2} 0 2, H 2 and semiconductor at O mixture was etched to Baffua layer 702 (FIG. 7-c), from subsequent substantially vertical second SiO ₂ layer 7
08 is deposited to cover the exposed GaAs buffer layer 702 and used as a mask during regrowth (FIG. 7-d). Since the gate electrode portion serves as a mask, the slope beneath the gate has Si
O ₂ does not deposit. Next, a high-concentration Te-doped low-resistance GaAs layer 709 is grown by metal organic chemical vapor deposition. Here, triethylgallium and tert-butylarsine,
The growth rate is increased at a low temperature by using diisopropyl propyl tellurium as a raw material (FIG. 7-e). After regrowth is over,
An AuGeNi ohmic electrode 710 is formed on the low-resistance GaAs layer 709 (FIG. 7F). The SiO ₂ 706 on the gate electrode 705 is removed by dry etching.
Through the above steps, a field effect transistor having an insulating film below the ohmic layer can be formed.

FIG. 8 is a schematic sectional view showing a second example of the heterojunction field effect transistor according to the second embodiment of the present invention. 8, parts corresponding to those in the embodiment of FIG. 7 are denoted by corresponding reference numerals, and detailed description thereof will be omitted. 8A to 8C are formed in the same steps as in the first embodiment shown in FIG. In FIG. 8D, SiO
_{After the two} layers 708 are deposited, an ohmic electrode 711 is formed by depositing Ti / Pt / Ge / Pt in this order from the vertical direction of the substrate by a resistance heating method. Then diffuses into Pt is in GaAs layer 712 constituting the ohmic electrode 711 during the growth of the low-resistance GaAs layer 712 in FIG. 8 (e) PtGa, continue to form a compound such as PTAS _2. G
By adding e, the resistance of the reaction layer at the interface between the electrode 711 and the GaAs layer 712 can be reduced, and an ohmic electrode can be realized.

The present invention is not limited to the embodiment described above. In the embodiment, GaAs, AlGaAs,
The heterojunction field effect transistor using InGaAs as a constituent material has been described, but MESFET + GaAs
It is also possible to apply to a heterojunction field effect transistor using InP, InGaAs, InAlAs, InP or the like as a constituent material. The insulating film below the low resistance layer may be made of SiN, SiON, or Al ₂ O ₃ other than SiO ₂ .

[0039]

As described above, in the field-effect transistor according to the first embodiment of the present invention, the first compound semiconductor layer containing In, Ga, and P is formed between the semiconductor substrate and the channel layer. Then, an ohmic contact layer made of a low-resistance semiconductor containing an n-type impurity is formed in contact with the first compound semiconductor layer and the channel layer.

A gate electrode made of a refractory metal is formed on the Schottky contact layer, an ohmic contact layer on the source electrode side is formed in self-alignment with the gate electrode, and an ohmic contact layer on the gate electrode and the source electrode side is formed. Is shorter than the distance between the gate electrode and the ohmic contact layer on the drain electrode side. By these means, in the present invention, it is possible to reduce the source resistance and the drain resistance, improve the gate-drain breakdown voltage, and improve the element performance of the HEMT.

Further, according to the field-effect transistor according to the second embodiment of the present invention, it is possible to use a low-resistance layer in which high-concentration n-type doping is performed in the ohmic contact layer, and it is possible to reduce the source resistance. Further, since the insulating layer is provided on the substrate side of the ohmic contact layer, the parasitic capacitance between the ohmic contact layer and the substrate can be reduced. Furthermore, the regrowth also serves as annealing of the damage introduced into the Schottky contact layer when depositing the refractory metal.

According to this embodiment, a defect is generated between the regrown layer and the semiconductor layer under the gate, the interface between them is increased in resistance, and a deep level is introduced at a high density. And a good regrowth layer can be formed.

The present invention is not limited to the above embodiment. For example, in order to form a recess structure, etching using a gate electrode as a mask is performed on a semiconductor substrate, but after forming a mask on a Schottky contact layer and performing etching for forming a recess structure, the mask is removed. It is also possible to use a method of removing and removing the mask to form a gate electrode. In addition, various modifications can be made without departing from the spirit of the present invention.

[Brief description of the drawings]

FIG. 1 is a sectional view of a HEMT according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method for manufacturing the HEMT of the present invention shown in FIG.

FIG. 3 is a sectional view showing a modification of the HEMT of the present invention shown in FIG.

FIG. 4 is a sectional view of a HEMT according to another embodiment of the present invention.

FIG. 5 is a sectional view of a HEMT according to another embodiment of the present invention.

FIG. 6 is a sectional view of a HEMT according to another embodiment of the present invention.

FIG. 7 is a sectional view of a HEMT according to another embodiment of the present invention.

FIG. 8 is a sectional view of a HEMT according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a structure of a conventional HEMT.

FIG. 10 is a sectional view showing another structure of the conventional HEMT.

[Explanation of symbols]

Reference Signs List 101 semi-insulating GaAs substrate 102 GaAs buffer layer 103 InGaP regrown surface layer 104 GaAs buffer layer 105 InGaAs channel layer 106 InGaP spacer layer 107 Electron supply layer made of Si planar doping layer 108 InGaP Schottky contact layer 109 GaAs ohmic contact layer 110 InGaAs ohmic contact layer 111 Gate electrode 112 Insulating film 113 Drain electrode 114 Source electrode 701 GaAs substrate 702 GaAs buffer layer 703 InGaAs channel layer 704 AlGaAs electron supply layer 705 Gate electrode 706 SiO ₂ layer 707 Side wall 708 Second ninth SiO ₂ layer Low resistance GaAs layer 710 AuGeNi ohmic electrode 711 Ohmic electrode 71 Low-resistance GaAs layer

Claims (9)

[Claims] 1. A first compound semiconductor layer containing In, Ga, and P is formed on a semiconductor substrate, and a first compound semiconductor layer containing at least Ga and As is directly or via a buffer layer on the first compound semiconductor layer. Forming a channel layer made of the compound semiconductor layer of No. 2, a step of stacking an electron supply layer and a Schottky contact layer on the channel layer, and the step of: Forming a mesa-shaped gate electrode region laminate by performing an etching process toward the first compound semiconductor layer; and forming n on the first compound semiconductor exposed on both sides of the mesa-shaped gate electrode region laminate. Growing an ohmic contact layer made of a semiconductor containing a type impurity. 2. A step of laminating a channel layer, an electron supply layer, and a Schottky contact layer on a semiconductor substrate;
A step of performing an etching process on the semiconductor substrate through a mask formed on the Schottky contact layer to form a mesa-shaped gate electrode region laminate, and exposing the semiconductor substrate on both sides of the gate electrode region laminate Covering the semiconductor layer surface parallel to the semiconductor substrate with an insulating film, and epitaxially growing laterally from the exposed side walls of the gate electrode region laminate, forming an ohmic contact layer as a low-resistance semiconductor layer on the insulating film. Forming a source electrode and a drain electrode on the ohmic contact layer. 3. The method according to claim 2, wherein a gate electrode is formed on the Schottky contact layer, and the mask is formed on an upper surface and both side surfaces of the gate electrode. 4. A semiconductor device comprising: a channel layer formed on a semi-insulating semiconductor substrate; an InGaAlP layer formed between the semi-insulating semiconductor substrate and the channel layer; and electrons from the channel layer containing an n-type impurity. An electron supply layer having a small affinity, a Schottky key contact layer having a smaller electron affinity than the channel layer, an n-type impurity formed in contact with the InGaAlP layer and the channel layer, and having a larger electron affinity than the Schottky contact layer. A compound semiconductor device comprising: an ohmic contact layer made of a low-resistance semiconductor layer; and a drain electrode and a source electrode formed on the ohmic contact layer. 5. A gate electrode made of a refractory metal is formed on the Schottky contact layer, an ohmic contact layer on a source electrode side is formed in self-alignment with the gate electrode, and a gate electrode and a source electrode side are formed. 5. The compound semiconductor device according to claim 4, wherein a distance between the gate electrode and the ohmic contact layer is shorter than a distance between the gate electrode and the ohmic contact layer on the drain electrode side. 6. It has a gate electrode made of a high melting point metal,
A compound semiconductor device, wherein a low-resistance semiconductor layer forming a source electrode and a drain electrode is formed by regrowth, and a material serving as a mask during regrowth remains between the semiconductor substrate and the regrown layer. 7. A mask material during regrowth, a compound semiconductor device according to claim 6, characterized in that the insulating film such as SiO2 or SiNx or SiON, or Al ₂ 0 _3. 8. It has a gate electrode made of a high melting point metal,
A compound in which a low-resistance semiconductor layer forming a source electrode and a drain electrode is formed by regrowth, and a material serving as a mask during regrowth and an ohmic electrode are sandwiched between the semiconductor substrate and the regrown layer. Semiconductor device. 9. When forming an ohmic electrode before regrowth, at least one of the ohmic electrodes has a laminated structure of a plurality of different metals, and the uppermost layer of the electrode is Pt.
Alternatively, the contact portion between the ohmic electrode and the low-resistance layer is made of Pt or Pd after the low-resistance layer is regrown.
9. The compound semiconductor device according to claim 8, comprising an intermetallic compound of the compound and a constituent element of the compound semiconductor.