JPH10256490A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a highly functional high-gain high-frequency power amplifying function by realizing highly stable operations. SOLUTION: In a semiconductor integrated circuit which is provided with a plurality of FETs 211-215 as active elements, a plurality of inductors 231-235 as passive elements, a plurality of capacitors, and coplanar wiring which are arranged on a semiconductor substrate, is composed of a plurality of FETs for amplification, and has a high-frequency amplifying function, at least a first coplanar ground surface 112 connected through the source of the last-stage FET for amplification and a second coplanar ground surface 111 connected through the source of the FET for amplification in an input stage are separated from the inside of a chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having a high-stability amplifying function in a high-frequency amplifier comprising a plurality of FETs provided on a chip.

[0002]

2. Description of the Related Art In recent years, wireless communication technology using microwaves has been remarkably developed. In particular, the mobile communication market is expanding significantly. Schottky gate type field effect transistor formed on GaAs substrate (MEtal Semico
nductor Field Effect Transistor = MESFET)
Has been widely used in high frequency power amplifiers of mobile communication terminals in a frequency band called L band.

This high-frequency power amplifier comprises a plurality of transistors and a plurality of passive elements. When these are formed on the same semiconductor chip, a monolithic integrated circuit for microwaves (Monolithic Microwave Integrated Circuit) is used.
t = MMIC), and the demand is particularly large because the terminal can be miniaturized. In the MMIC-type high-frequency power amplifier, it is necessary to achieve a low power supply voltage operation of about 3 V for miniaturization of a terminal, a single power supply operation that does not require a gate bias for enabling simplification of the system, and high efficiency. is there. In recent years, in addition to these items, on the premise of high integration, a high-gain, high-performance power amplifier in which an amplifier composed of two chips of an output power variable amplifier and a power amplifier is integrated on one chip has been developed. Is being sought.

FIG. 9 shows a high gain circuit having a power gain of 40 dB.
1 shows a high-performance power amplifier. FIG. 10 is an equivalent circuit diagram of the high gain and high function power amplifier. Variable gain and output power variable two-stage amplifier having 20 dB class gain using coplanar wiring and 20 dB using coplanar wiring
A two-stage power amplifier having a class of gain is cascaded. 9 and FIG.
5 is a MESFET, 1021 to 1025 are MIM capacitors,
1031-1035 is an inductor; 1041-1045
Is a resistance, and 1051-1053 is a parasitic inductance due to the coplanar ground plane. In FIG. 10, ME
The SFET 1015 is provided to have a function of varying output power.

FIG. 11 shows the frequency characteristics of the stabilization coefficient K when the power amplifier shown in FIG. 9 is mounted on a package and when the power amplifier is directly mounted on a measuring jig. From FIG.
The value of the stabilization coefficient K in the frequency range of 0.1 to 5 GHz is
It is absolutely stable at 1.2 or more when mounted directly on the measurement jig, and it can be seen that the chip itself operates stably. On the other hand, when the MMIC is mounted on a package, it is not possible to maintain an absolutely stable value of 1 or more, indicating that the stability of the circuit is significantly impaired.

Such a loss of stability causes a large change in the impedance of the output terminal or the input terminal due to the failure of the antenna or the device at the preceding stage, even if the oscillation of the power amplifier is avoided in a normal use condition. In such a case, self-excitation occurs, and when the signal strength further increases, the device is destroyed.

[0007]

As described above, the function of the high-frequency power amplifier is realized on the MMIC,
However, there is a problem in that mounting the device on a package significantly deteriorates the stability of the circuit and leads to the self-excitation of the circuit and the destruction of the device.

The present invention has been made in consideration of the above circumstances, and has as its object to realize a semiconductor having a high-performance and high-gain high-frequency power amplifying function by realizing a highly stable operation. It is to provide an integrated circuit.

[0009]

According to the present invention, the following means have been taken in order to solve the above-mentioned problems. The gist of the present invention is that at least the coplanar ground plane connected via the source of the final-stage amplification FET and the input-stage amplification FE
The coplanar ground plane connected via the source of T is separated on the chip. A typical example is a coplanar ground plane connected via the source of the final-stage amplifying FET and a coplanar ground plane connected from the source or source of the preceding-stage amplifying FET via the element. Are separated on the chip. Here, a coplanar ground plane connected from the source or source of the amplification FET at the preceding stage of the final stage via the element and a coplanar ground connected from the source or source of the amplification FET at the preceding stage via the element. The surfaces are separated in the chip.

A coplanar ground plane connected via the source of the last-stage amplifying FET and a coplanar ground plane connected via the element from the source or source of the preceding-stage amplifying FET on the last stage. Connected in a chip, and further amplifying F at a stage before the last stage.
There is also a configuration in which a source of the ET or a coplanar ground plane connected from the source via an element or separated from the coplanar ground plane.

In the above configuration, the separated coplanar ground plane is connected via a resistor. With the above configuration, the final stage F on the chip
Since the coplanar ground plane via the source of the ET is separated from other coplanar ground planes, there is no feedback loop formed from the last stage via the coplanar ground plane. In addition, a semiconductor integrated circuit having high circuit stability can be obtained.

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a semiconductor integrated circuit having a power amplifying function according to a first embodiment of the present invention, in which four FETs having an amplifying function are composed of passive elements such as inductance, capacitance, resistance, and coplanar wiring. It is configured by cascade connection via an interstage matching circuit. FIG. 2 is an equivalent circuit diagram of the semiconductor integrated circuit of FIG. 1 of the present invention.

In FIGS. 1 and 2, reference numerals 111-112 denote a coplanar ground plane, and 211-215 a MESFE.
T, 221-225 are MIM capacitors (Metal-Insulator-Me
tal), 231-235 are inductors, 241-245
Indicates a resistance, and 251-252 indicates a parasitic inductance due to the ground plane. In FIG. 2, the MESFET 215
Is provided to make the output power variable. In addition, each of the amplifying transistors uses a common source type.

In the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 1, the coplanar ground plane connected through the source of the final-stage amplifying FET and the amplifying circuit in the preceding stage of the final-stage are used. The coplanar ground plane connected to the source of the FET or the source via the element is separated.

FIG. 3 is a schematic diagram when the semiconductor integrated circuit of FIG. 1 is mounted on a package. In FIG.
Reference numerals 311 and 312 denote coplanar ground planes, respectively.
3 shows a microstrip. FIG. 4 shows a power supply voltage of 3 V and a current consumption of 200 m at the input and output terminals of the IC of FIG.
9 is a simulation result of the frequency characteristic of the stabilization coefficient K under the operation condition of A.

As can be seen from FIG. 4, under operating conditions of a power supply voltage of 3 V and a current consumption of 200 mA, a frequency of 0.1 to
In the region of 5 GHz, the value of the stabilization coefficient K of the device of the present invention is 1
The above is maintained, indicating that the stability of the circuit is sufficiently ensured.

FIG. 5 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. In FIG. 5, reference numerals 511 and 512 indicate coplanar ground planes.
Other configurations are the same as those in FIG.
Description is omitted.

The second embodiment is different from the first embodiment in that the coplanar ground plane is not separated into the last stage and the stage before the last stage. Separated by That is, the final stage FE for amplification
A coplanar ground plane connected via the source of T and a coplanar ground plane connected from the source or source of the amplifying FET of the preceding stage of the final stage via an element are connected in the chip. A ground plane and a coplanar ground plane connected to the source of the amplifying FET in the preceding stage of the final stage and the source via the element from the source are separated.

This semiconductor integrated circuit was mounted on the package shown in FIG. 3 and a simulation of the frequency characteristic of the stabilization coefficient K was performed.
Under the operating condition of 00 mA, the frequency is 0.1 to 5 GHz.
, The value of the stabilization coefficient K is maintained at 1 or more.

FIG. 6 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. In FIG. 6, 611-613 indicates a coplanar ground plane. Other configurations are the same as those in FIG. 1, and therefore, are denoted by the same reference numerals and description thereof will be omitted.

In the third embodiment, in addition to the first embodiment, a coplanar ground plane connected to the source or source of the amplifying FET in the preceding stage of the final stage via an element and a further amplifying FET in the preceding stage. The source of the FET or a coplanar ground plane connected from the source via the element is separated in the chip.

That is, in the semiconductor device according to the third embodiment, the coplanar ground plane connected via the source of the final-stage amplification FET and the amplification FE in the preceding stage of the final stage.
The source of T or a coplanar ground plane connected from the source via the element is separated on the chip, and a coplanar connected from the source or source of the amplifying FET of the preceding stage of the final stage via the element. A ground plane and a coplanar ground plane connected to the source of the amplifying FET at the preceding stage via a device from the source are separated in the chip.

This semiconductor integrated circuit was mounted on the package shown in FIG. 3, and the frequency characteristic of the stabilization coefficient K was simulated.
Under the operating condition of 00 mA, the frequency is 0.1 to 5 GHz.
, The value of the stabilization coefficient K is maintained at 1 or more. Further, the stabilization coefficient K in the present embodiment is further stabilized as compared with the first embodiment.

FIG. 7 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention. In FIG. 7, reference numerals 711 and 712 denote coplanar ground planes. In other configurations, the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is different from the first embodiment in that
The difference is that the separated coplanar ground planes 711 and 712 are connected by a resistor 713. That is, the coplanar ground plane 712 connected via the source of the final-stage amplification FET and the coplanar ground plane 711 connected from the source or source of the previous-stage amplification FET via the element are connected to the chip. And the separated coplanar ground planes 711 and 712 are connected via a resistor 713.

The semiconductor integrated circuit according to the present embodiment was mounted on the package shown in FIG. 3, and the frequency characteristics of the stabilization coefficient K were simulated.
Under the operating conditions of V and a current consumption of 200 mA, the value of the stabilization coefficient K is maintained at 1 or more in a frequency range of 0.1 to 5 GHz.

FIG. 8 is a diagram showing a schematic configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention. In FIG. 8, reference numerals 811 and 812 denote coplanar ground planes. In other configurations, the same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is different from the second embodiment in that
The difference is that the separated coplanar ground planes 811 and 812 are connected by a resistor 813. That is, the coplanar ground plane connected via the source of the final-stage amplification FET, the coplanar ground plane 812 connected via the source of the previous-stage amplification FET, and the amplification FET further upstream thereof Coplanar ground surface 811 connected to the source or the source via an element is separated on the chip, and further separated coplanar ground surface 81
1, 812 are connected via a resistor 813.

That is, the coplanar ground plane connected via the source of the last-stage amplifying FET and the coplanar ground plane connected via the element from the source or the source of the preceding-stage amplifying FET on the last stage. A coplanar ground plane connected within the chip and further connected to the source or source of the amplifying FET of the preceding stage of the last stage via an element from the coplanar ground surface is further separated from the coplanar ground surface. The planar ground plane is connected via a resistor.

The semiconductor integrated circuit according to the present embodiment was mounted on the package shown in FIG. 3, and the frequency characteristic of the stabilization coefficient K was simulated.
Under the operating conditions of V and a current consumption of 200 mA, the value of the stabilization coefficient K is maintained at 1 or more in a frequency range of 0.1 to 5 GHz.

As described above, it is extremely effective to stabilize the circuit to separate the coplanar ground plane connected to the source to the amplifying FET on the chip. The present invention is not limited to the above embodiment of the present invention.

In each of the embodiments according to the present invention, each amplification stage is constituted by the grounded source of the FET, and the source and the coplanar ground plane are treated as the same node. It is not always necessary to connect the source of the FET to the coplanar ground plane via an inductor, or to connect the FET source to the coplanar ground plane via a parallel connection of resistors and capacitors. Even when used, the method of separating the coplanar ground plane used in the present invention is effective. In addition, it goes without saying that various modifications can be made without departing from the scope of the present invention.

[0033]

According to the present invention, the following effects can be obtained. As described above, the coplanar ground plane via the source of the last-stage FET on the chip is separated from other coplanar ground planes, and there is no feedback loop formed from the last stage via the coplanar ground plane, or The coplanar ground plane via the source of the last-stage FET on the chip and the coplanar ground plane via the source of the previous-stage FET are connected, but are separated from this coplanar ground plane and other coplanar ground planes. Therefore, there is no feedback loop returning from the last stage to the first stage via the coplanar ground plane, or the separated coplanar ground plane is connected by a resistor, and as a result, the gain of the formed feedback loop is significantly reduced. Therefore, a semiconductor integrated circuit having a high gain power amplification function and high circuit stability can be obtained.

[Brief description of the drawings]

FIG. 1 is a view schematically showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a view schematically showing the semiconductor integrated circuit according to the first embodiment of the present invention mounted on a package;

FIG. 4 is a diagram illustrating frequency dependence of a stabilization coefficient when the semiconductor integrated circuit according to the first embodiment of the present invention is mounted on a package.

FIG. 5 is a view schematically showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a view schematically showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 7 is a view schematically showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 8 is a diagram schematically illustrating a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 9 is a diagram schematically illustrating a conventional semiconductor integrated circuit having a high-gain power amplification function.

FIG. 10 is a diagram showing an equivalent circuit of a conventional semiconductor integrated circuit having a high-gain power amplification function.

FIG. 11 is a diagram illustrating frequency dependence of a stabilization coefficient when a conventional semiconductor integrated circuit having a high-gain power amplification function is mounted on a package.

[Explanation of symbols]

111-112, 511-512, 611-613, 7
11-712, 811-812, 911: Coplanar ground plane, 211-215, 1011-1015 ... MESFET, 221-225, 1021-1025 ... MIM capacitance, 231-235, 1031-1035 ... Inductor, 241-245, 1041-1045 ... resistance, 251-252, 1051-1053 ... parasitic inductance by coplanar ground plane, 713, 813 ... resistance.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masami Nagaoka 1 Toshiba R & D Center, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Pref. No. 1 town Toshiba R & D Center

Claims (2)

[Claims] 1. A semiconductor integrated circuit having an FET as an active element, a plurality of inductors as a passive element, a plurality of capacitors, and a coplanar wiring on a semiconductor substrate and having a function of high frequency amplification constituted by a plurality of amplifying FETs. In the circuit, at least a first coplanar ground plane connected via the source of the final-stage amplifying FET and a second coplanar ground plane connected via the source of the input-stage amplifying FET are connected to the chip A semiconductor integrated circuit, wherein the semiconductor integrated circuit is separated in the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said first coplanar ground plane and said second coplanar ground plane are connected via a resistor.