JPH10255404A - Data transfer method for storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely execute a transfer without reducing the transfer rate, by executing the error correction processes, in which error data are read from a buffer, errors are corrected and the data are again written in the buffer in the period which is other than the data reading period from a data region. SOLUTION: While data are being read, an ECC4 always conducts an error check. While Data 0, which is the data region of a first sector 0, are read, error checks are conducted against all the data of the Data 0. If an error is found in the Data 0, the ECC4 reports the fact that there is an error in the present sector against a BM5 in the region other than the non-data region between the reading of the Data 0 is completed and before start reading Data 1 of a next sector 1. If the BM5 receives the report, the BM5 stores and holds the leading address of a buffer 6 of the Data 0 stored in the buffer 6. This is to conduct a smooth correction in a next error data correction process. The corrected data are then transferred to a host 8 from the buffer 6 through a host I/F 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method in error data correction processing of a storage device, particularly a disk device.

[0002]

2. Description of the Related Art Conventionally, a data transfer method in error data correction processing of a disk device of this kind is disclosed in, for example,
As typified by Japanese Patent Application Laid-Open No. 2-132270, error data is read from a buffer during an idle time of data transfer, and this data is written to the same address during an idle time of data transfer after correction.

FIG. 4 shows a block diagram of this conventional embodiment.
The timing chart is shown in FIG. In the conventional disk drive, as shown in FIG. 4, the memory management processor 60 is configured such that the control unit 11 of the main controller 10 and the DMA controller 4
0, and issues a command for reading data from the disk 30 to the control unit 21 of the disk interface 20. In response to this, Disk Interface 2
0 reads data from the disk 30 and temporarily stores it in the sector buffer 22 through the drive interface 23. All of the read data are checked for errors by the error processor 24. After this, the data is D
It is stored in the main memory 50 via the MA controller 40. If an error is found, the main controller 10 reads the error data from the main memory 50 into the sector buffer 12 and sends it to the error processor 13.
And correct data is stored in the main memory 50 again.

FIG. 5 shows the detailed timing. Looking at this, the disk interface reads data R1, R2, R3, R4, and R5 one by one from the disk. Thereafter, the data W is transmitted from the disk interface to the DMA controller as shown in FIG.
0, W1, W2, W3, and W4 are transferred in one memory cycle, and the data is stored in the main memory as it is. If an error is found in the data R1, the DMA controller reads the error data r1 from the main memory after transferring the data W1, and sends it to the main controller.
The main controller performs error recovery of the error data r1, and when the recovery is completed, after transferring the data W3, sends the true data w1 obtained by correcting the error data r1 to the DMA controller, and the DMA controller stores this in the main memory.

As described above, the conventional disk device performs reading of error data and writing of correction data during idle time of data transfer.

[0006]

However, in the prior art, when a plurality of errors are found when reading data from a disk, the error data is read and the corrected data is written each time the data transfer is vacant. It is difficult to use the data bus, and the available time of the data bus is reduced. As a result, there is a danger that the data transfer rate is reduced or the data cannot be transferred. As described above, since the conventional method performs data transfer in error data correction processing unplannedly, there is a possibility that it is very difficult to cope with a plurality of errors as described above.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a disk format in which a sector is formed in units of sectors, and the sector is composed of a data area in which user data is written and other data areas. Read the data from the disk and the disk separated into the area, temporarily store the data in the buffer while checking whether there is an error in the read data, read the error data from the buffer after calculating the error if there is an error, and Error data is read out from the buffer at a time other than when reading the data area in a sector on the disk, and then written to the same address after error correction in a disk device that stores the data in the buffer again after correcting the error data. It is to realize a data transfer method for performing processing.

[0008]

In order to solve the above-mentioned problems, a data transfer method for a storage device according to the present invention comprises the following steps. (1) The format format of a recording medium is constituted by sectors, and user data is written in the sectors. In a data transfer method for a storage device using a recording medium separated into a data area and an area other than the data area, an error data correction process of reading error data from a buffer, correcting the error, and writing data to the buffer again is performed. , At a time other than when data is read from the data area.

(2) When an error is detected in the data being read, an error detection bit is asserted between the time of reading the data area of this sector and the time of reading the data area of the next sector.

(3) In response to the error detection bit, the head address of the buffer storing the data of the sector in which the error data is found is stored and held.

(4) When the error calculation is completed, the error correction bit is asserted between the time of reading the data area of the sector currently being read and the time of reading the data area of the next sector.

(5) The offset address indicating the location of the error data is transmitted at the same time as asserting the error correction bit.

(6) When an error is detected in the data being read, an error detection bit is asserted between the time of reading the data area of this sector and the time of reading the data area of the next sector. And the head address of the buffer in which the data of the sector in which the error data is found is stored, and when the error calculation is completed, the data area of the currently read sector is read and the data area of the next sector is read. During the time, the error correction bit is asserted, the error correction bit is asserted, and at the same time, the offset address indicating the location of the error data is transmitted, and the error correction bit is received, and the buffer address obtained by adding the start address and the offset address is received. Read error data from
After correcting the data, the data is written to the added buffer address.

(7) If error data is found in the previous sector after the error data correction processing is completed except at the time of reading the data area, the error detection bit is asserted after the error correction bit is negated. Features.

[0015]

According to the above configuration of the present invention, error data can be systematically corrected by reading error data from the buffer and writing correction data to the buffer other than when reading the data area on the disk. This enables data transfer without lowering the transfer rate.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment) A disk device will be described as an example of a storage device.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a timing chart showing timings for reading error data and writing corrected data according to the embodiment of the present invention, and FIG. 3 is a more detailed view of FIG. FIG. 4 is a timing chart showing various timings.

First, the flow of data at the time of reading (reading) a normal disk device will be described.

As shown in FIG. 1, a read command is first sent from the host 8 through the host I / F 7 to the CPU.
1 receives. In response to this, the CPU 1 sends a read command to each block. The disk I / F 3 reads data written on the disk 2 from the disk 2. In the disk I / F 3, the data area of the sector on the disk 2 and the other area are separately detected. Although the format of the disk 2 varies, the disk 2 is usually configured in units of sectors, and the contents of these sectors are divided into a data area in which user data is written and other areas as shown in FIG. The extracted data is EC
The data is sent to C4, where it is checked whether there is an error in the data.
Is stored in the buffer 6 via When an error is detected in the data by the ECC 4, the error is calculated, and the BM 5 takes out the error data from the buffer 6, corrects the error data, and stores it in the buffer 6 again. The corrected data is then transferred from the buffer 6 to the host 8 via the host I / F 7.

As described above, the disk device performs a reading operation.

Next, the details of the present invention will be described. FIG. 1B
Explaining the flow of read data focusing on M5, first, when data is to be transmitted from ECC4 to BM5,
Asserts a data request (Data Request) and sends out data (Data). Upon receiving this, the BM 5 receives the ECC 4 if there is no request from another block or even if there is a request from another block.
If the request from is higher priority, ECC4
Data Acknowledge (Data Acknowledgment)
edge) is asserted, and data is fetched internally. Usually, this data is in units of 1 byte (8 bits) or 1 word (16 bits). Thereafter, the BM 5 sends the buffer address (Buf
ferAddress) and the write signal (B
While asserting “buffer control”, the data (buffer data) is stored in the buffer 6. Normally, processing is performed once in units of one byte or one word. For example, in some DRAMs, a page mode can be used, and when this is used, data can be processed continuously.

Next, the operation at the time of error correction will be described. As described above, an error check is always performed by the ECC 4 when data is being read. Referring to FIG. 2, while reading the data area Data0 of the first sector 0, all data of the data area Data0 are read. Usually, one sector is 512 bytes, or a block of 1024 bytes or 2048 bytes of data. If one error is found in Data0 as shown in FIG.
No. is an area other than the data before reading Data1, which is the data area of the next sector 1 after reading of 0 is completed.
During t Data1, the ECC 4 reports to the BM 5 that there is an error in Data 0 in the data area of the current sector 0. As shown in FIG. 2, the error detection bit (Error Detect) is asserted at the time of Not Data1. BM5 is this Error De
When receiving Tect, the Dat stored in buffer 6
The head address in the buffer of a0 is stored and held.
The reason why the data is stored and held in this way is to smoothly correct the error data when the next error data correction process is performed.

Next, after the end of Not Data1 of sector 1, Data1, which is the data area of sector 1, is read out.
The error calculation of data0 is performed. As shown in FIG.
Data0 error calculation is completed during the ta1 transfer, and EC
C4 is ready to send corrected data to BM5. After this, after the transfer of Data1 is completed, during Not Data2 which is other than the data area of the next sector 2, Data
The error data of a0 is corrected. As shown in FIG. 2, an error correction bit (Error Correct) and Data
Request is asserted, and the ECC 4 notifies the BM 5 that the corrected data of Data 0 will be transmitted.
When the BM 5 receives this, as described above, if there is no request from another block, or if there is a request from another block, if the priority of the request from the ECC 4 is high, Data ACKNO is sent to the ECC 4
Assert wledge to capture data. An example of this detailed timing is shown in FIG.

Looking at this, first, the first clock (CL
OCK) rises and ECC4 becomes Data Req
At the same time as est and Error Correct are asserted, the correction data (Din1) and the offset address (Offset Address) indicating the location of the error are transmitted.

At the next rising edge of the clock, the BM 5 returns Data Acknowledge to the ECC 4 if the priority of the request from the ECC 4 is high as described above, and takes in the correction data and the offset address.

At the next rising edge of the clock, ECC4 becomes D
The data request is negated, and the transmission of the correction data and the offset address is stopped. The BM 5 is a start address (Start Address) of a buffer in which Data 0 which is a data area of the sector 0 in which an error is detected and stored, and an offset address (Offse) indicating an error location received from the ECC 4.
t Address), and error data (Din2) is read from this address. As shown in FIG. 3, Buffer Control Read (a read control signal from the buffer) is asserted to the buffer, and the buffer is read.
Address1 = Star in the far Address
t Address + Offset Address is transmitted, and Buffer Data which is error data is transmitted.
(Din2).

At the next rising edge of the clock, the error data (Din2) fetched into the BM 5 is corrected based on the correction data (Din1) fetched from the ECC 4. In this embodiment, Din1 and Din2 are exclusive.
-OR (exclusive sum) is taken.

At the next rising edge of the clock, the BM 5 writes the corrected data (Dout) to the buffer. At this time, the buffer address is Address1 as before. Asserts Buffer Control Write (buffer control signal for writing) to Buffer
Address1 and Buffer D in Address
Dout is sent to each data, and true data is stored in the buffer.

Error at the next rising edge of the clock
Correct is negated, and the error data correction processing ends. If there are multiple errors, this Error
What is necessary is just to repeat the above operation | movement in the state of asserting Correct.

When an error is detected in the data area Data1 of the sector 1 as shown in FIG. 2, the error data correction of the data area Data0 of the sector 0 is performed during Not Data2 other than the data area of the sector 2. After the processing is completed, that is, after Error Correct is negated, Error Detect is asserted. The subsequent processing is as described above.

As described above, the error data correction processing is performed with five clocks per data. It is needless to say that by using this method, the disk can be applied to all disk devices configured in the data area and the other area in sector units.

[0032]

According to the present invention as described above,
In any disk device in which the disk is configured in sector units, by using a planned method such as performing error data correction processing other than when reading the data area of the sector on the disk, the transfer rate can be reliably reduced without lowering Can be processed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing timings for reading error data and writing corrected data according to the embodiment of the present invention.

FIG. 3 is a timing chart showing detailed timings at the time of error data reading and correction data writing according to the embodiment of the present invention.

FIG. 4 is a block diagram showing the entire configuration of an embodiment of the conventional invention.

FIG. 5 is a timing chart showing timings of reading error data and writing correction data according to the embodiment of the conventional invention.

[Explanation of symbols]

 1 CPU 2 Disk 3 Disk I / F 4 ECC 5 BM 6 Buffer 7 Host I / F 8 Host 10 Main Controller 11 Control Unit 12 Sector Buffer 13 Error Processor 20 Disk Interface 21 Control Unit 22 Sector Buffer 23 Drive Interface 24 Error Processor 30 Disk 40 DMA controller 50 main memory 60 memory management processor

Claims (7)

[Claims] 1. A data transfer method for a storage device using a recording medium in which a format format of a recording medium is configured in units of sectors and the sectors are separated into a data area in which user data is written and an area other than the data area. A data transfer method for a storage device, wherein an error data correction process of reading error data from a buffer, correcting the error, and writing data to the buffer again is performed at a time other than when data is read from the data area. 2. The method according to claim 1, wherein when an error is detected in the data being read, an error detection bit is asserted between the time of reading the data area of this sector and the time of reading the data area of the next sector. Data transfer method for a storage device. 3. The storage device according to claim 2, wherein in response to the error detection bit, a start address of the buffer storing data of a sector in which the error data is found is stored. Data transfer method. 4. The storage according to claim 1, wherein when the error calculation is completed, an error correction bit is asserted between the time of reading the data area of the currently read sector and the time of reading the data area of the next sector. Device data transfer method. 5. The data transfer method for a storage device according to claim 4, wherein said error correction bit is asserted and an offset address indicating a location of error data is transmitted at the same time. 6. When an error is detected in the data being read, an error detection bit is asserted between the time of reading the data area of this sector and the time of reading the data area of the next sector. The head address of the buffer in which the data of the sector in which the error data was found is stored and held, and when the error calculation is completed, between the time of reading the data area of the currently read sector and the time of reading the data area of the next sector Asserting the error correction bit to, and simultaneously transmitting the offset address indicating the location of the error data while asserting the error correction bit, receiving the error correction bit, from the buffer address obtained by adding the start address and the offset address Reads error data and corrects data before Data transfer method of a storage apparatus according to claim 1, wherein the write data to the addition to the buffer address. 7. An error detection bit is asserted after negating the error correction bit when error data is found in the previous sector after the error data correction processing is completed except at the time of reading the data area. 2. The data transfer method for a storage device according to claim 1, wherein