JPH10253986A - Semiconductor device, and production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance semiconductor device by exactly forming plural impurity-contg. regions varying in concn. in a semiconductor layer with high accuracy. SOLUTION: Gate electrodes 11 and electrodes 20 for masks are simultaneously formed and the exposure of a positive type resist PR is executed by using the edges of these gate electrodes 11. The resist is then developed. With these resists as a mask, ion implantation is executed to form low-concn. regions N-. A negative type resist NR is formed and is exposed by utilizing the edges of electrodes 20 for the masks. The resist is then developed. With these resists as a mask, ion implantation is executed to form the high-concn. regions constituting sources and drains. Since both of the high-concn. regions and low-concn. regions are regulated with the boundaries by using the gate electrodes 11 and electrodes 20 for the masks patterned by using the same masks, the electrodes are formed exactly with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, to a liquid crystal display (LCD).
The present invention relates to a method of manufacturing a peripheral drive circuit integrated type LCD in which a thin film transistor (TFT) using a polycrystalline semiconductor layer is formed in a display portion and a peripheral portion.

[0002]

2. Description of the Related Art The technique of forming a semiconductor film on a substrate is used to increase the degree of integration of an integrated circuit to increase the capacity, or to form a matrix pixel on one of a pair of substrates sandwiching a liquid crystal. TFT to be the switching element of the unit
The development of mass production of active matrix type LCDs capable of displaying high-definition moving images has been carried out.

In particular, MOSF fabricated on a silicon substrate
If a TFT capable of exhibiting characteristics close to ET can be formed on an insulating substrate, not only the switching element in the matrix pixel portion of the LCD but also a CMOS formed in the periphery and a desired drive signal voltage is applied to the matrix pixel portion It is also possible to integrally form a peripheral driving circuit for supplying, so that mass production of a so-called driver built-in LCD can be performed.

[0004] The LCD with a built-in driver eliminates the need for externally attaching a driver element to the liquid crystal panel.
The number of processes can be reduced and the frame can be narrowed. In particular, narrowing the frame can reduce the size of the product itself in applications such as a portable information terminal or a monitor of a handy video camera in recent years. As such a TFT, a polycrystalline semiconductor in which a large number of single crystal grains (grains) having a grain size of several hundreds to several thousands of mm are in contact with each other is used for a channel layer so that a driver portion can be formed. It can be an applicable high-speed element. In particular, polycrystalline silicon or polysilicon (p
-Si) has a mobility of about several tens to several hundreds cm2 / Vs, and is two orders of magnitude higher than amorphous silicon, that is, amorphous silicon (a-Si). Therefore, N-chT
By forming the FT and the P-ch TFT, a CMOS having a sufficient speed for forming an LCD driver is formed.

[0005] In particular, the applicant has previously set a process temperature of at most about 600 ° C. or less in order to reduce the cost, and as a substrate, it is possible to use an inexpensive alkali-free glass substrate or the like having low heat resistance. Has been developed. Such a manufacturing process of the p-Si TFT LCD in which the entire process is suppressed to a temperature lower than the limit temperature of the heat resistance of the substrate is called a low temperature process.

FIG. 9 shows a sectional structure of such a p-Si TFT. The left side of the figure is an N-ch TFT, and the right side is P
-Ch TFT. A gate electrode (51) made of a metal such as Cr is formed on a substrate (50), and a gate insulating film (52) made of SiNx or / and SiO2 is formed so as to cover the gate electrode (51). On the gate insulating film (52), p-Si (53) is formed. p-Si
(53) uses an edge of a stopper (54) made of SiO2 or the like which is patterned thereon, and in the N-ch, a low concentration (LD:
lightly doped) region (N −) and a high concentration region (N +) serving as a source and a drain containing an N type impurity at a high concentration outside the region (N −). Is contained at a high concentration, and a high concentration region (P +) serving as a source and a drain is formed. N-ch, P-
In each of the channels, immediately below the stopper (54) is an intrinsic region (IN) substantially containing no impurities.
An interlayer insulating film (55) made of SiNx or the like is formed to cover the p-Si (53), and a source and drain electrode (56) made of metal is formed on the interlayer insulating film (55).
Are formed, and are connected to the high-concentration regions (N +, P +) of p-Si (53) through contact holes formed in the interlayer insulating film (55). Although omitted here, in the pixel portion, ITO (indium tin oxide) is further formed on the interlayer insulating film covering the source and drain electrodes (56).
A display electrode for driving a liquid crystal, which is made of a transparent conductive film such as xide), is formed and connected to the source electrode.

In the N-ch, a structure in which an LD region (N−) is formed between a high concentration region (N +) and an intrinsic region (IN) is called an LDD (lightly doped drain). In an LCD, such an LDD structure is adopted for the purpose of suppressing off current. The fabrication of the LDD structure is performed as follows. First, a positive resist is further formed on the insulating film formed on the p-Si (53). Next, light is irradiated from the substrate (50) side to form a gate electrode (5).
Exposing the resist reflecting the pattern shape of 1),
A so-called backside exposure is performed. Subsequently, after developing the resist, the insulating film is etched using the resist as a mask to form a pattern of the stopper (54) in the same shape as the gate electrode (51). Then, using the stopper (54) (resist) as a mask, an impurity ion exhibiting N-type conductivity such as phosphorus (P) is doped at a low concentration to form the stopper (54).
The intrinsic region (IN) immediately below and the LD region (N
-) Form. After that, resist is stopped by stopper (5
4) It is formed in a shape larger than that, and this is used as a mask,
By doping N-type impurity ions at a high concentration,
A high concentration region (N +) serving as a source and a drain is formed. Thus, an LDD structure in which the LD region (N−) is interposed between the intrinsic region and the high-concentration region (N +) is completed for the N-ch.

Similarly, the P-ch also reflects the shape of the gate electrode (54), and reflects the high concentration of the source and the drain highly doped with P-type impurities in the intrinsic region (IN) and the outside thereof. A region (P +) is formed.
However, the P-ch does not employ the LDD structure.

[0009]

The intrinsic region (IN) and the LD region (N) are formed by utilizing the pattern of the gate electrode (54).
-) Can be defined with high precision (N-ch), or the boundary between the intrinsic region (IN) and the high concentration region (P +) can be defined with high precision (P-ch). Become. However, in the N-ch, the boundary between the LD region (N−) and the high-concentration region (N +) is further defined by the positioning accuracy of resist pattern formation used as a mask when performing high-concentration doping. Depends on. That is, the gate electrode (54)
A plurality of regions having different impurity concentrations are formed by strictly defining the boundary lines by using the pattern (2).
Kind is the limit. Therefore, in the above-described example, since the mutual alignment accuracy between the mask alignment for forming the gate electrode (51) and the mask alignment for forming the high concentration region (N +) and the LD region (N−) depends on each other, The boundary between the LD region (N−) and the high-concentration region (N +) with respect to the gate electrode (51) cannot be strictly defined. As a result, the width of the LD region (N−) varies. L
Since the D region (N−) is usually interposed as a resistor,
Enlargement of the LD region (N−) leads to an increase in resistance, and reduction or extinction of the LD region (N−) leads to a decrease in resistance, thus deteriorating element characteristics.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and in a semiconductor device having a single or multiple semiconductor layers and electrode layers, the semiconductor layer comprises:
The semiconductor device includes a plurality of impurity-containing regions having different concentrations and having a boundary reflecting at least a part of the shape of the electrode.

Thus, since the boundaries between the plurality of regions having different concentrations in the semiconductor layer are strictly determined in accordance with the shape of the electrode, positioning with respect to the electrode is performed with high accuracy. In a semiconductor device in which a single layer or a plurality of electrode layers are formed, the semiconductor layer includes an intrinsic region containing substantially no impurities, a low-concentration region containing impurities at a low concentration, and A high-concentration region containing a high concentration, a boundary between the intrinsic region and the low-concentration region,
In addition, a boundary between the low-concentration region and the high-concentration region conforms to at least a part of the edge of the electrode in a plane.

Thus, in each case, the boundaries between the intrinsic region and the low-concentration region and between the low-concentration region and the high-concentration region are strictly determined according to the shape of the electrode. It becomes possible. In addition, an electrode layer, an insulating layer, and a semiconductor layer are formed over the substrate, and the semiconductor layer is formed over the semiconductor layer in the method for manufacturing a semiconductor device including a plurality of impurity-containing regions having different concentrations.
At least a part of the edge forms a coating film corresponding to at least a part of the edge of the electrode, and the plurality of impurity-containing layers having different concentrations are formed according to an inverted shape of the coating film. .

Thus, the boundaries between the plurality of regions having different impurity concentrations are strictly determined with reference to the electrodes in accordance with the shape of the electrodes, so that a high-definition and accurate element can be formed. Further, a semiconductor device in which a gate electrode over a substrate, an insulating layer covering the gate electrode, a semiconductor layer having a plurality of impurity-containing regions with different concentrations over the insulating layer, and source and drain electrodes connected to the semiconductor layer are formed. In the manufacturing method, a step of forming a light shielding electrode simultaneously with the gate electrode on the substrate, a step of forming the insulating layer covering the gate electrode and the light shielding electrode, and forming a semiconductor layer on the insulating layer Forming, forming a coating film on the semiconductor layer, and forming the coating film such that at least a part of its edge is at least one of the edges of the gate electrode and / or the light shielding electrode. Processing into a shape that matches the part,
Forming at least two types of impurity-containing regions having different concentrations by performing ion implantation of the impurity into the semiconductor layer through the processed coating film.

Thus, since the boundaries between the plurality of impurity-containing regions having different concentrations in the semiconductor layer are strictly defined according to the edges of the gate electrode and the light shielding electrode, it is possible to form a high-definition and accurate element. . Further, a semiconductor device in which a gate electrode over a substrate, an insulating layer covering the gate electrode, a semiconductor layer having a plurality of impurity-containing regions with different concentrations over the insulating layer, and source and drain electrodes connected to the semiconductor layer are formed. In the manufacturing method, a step of forming a light shielding electrode simultaneously with the gate electrode on the substrate, a step of forming the insulating layer covering the gate electrode and the light shielding electrode, and forming a semiconductor layer on the insulating layer Forming, forming a first coating film on the semiconductor layer, and forming the first coating film such that at least a part of an edge thereof is at least a part of an edge of the gate electrode. And a step of performing ion implantation of the impurity into the semiconductor layer at a low dose through the processed first coating film to thereby obtain two types of impurity-containing regions having different concentrations. The shape And forming a second coating film on the semiconductor layer, and forming the second coating film such that at least a part of an edge thereof is at least a part of an edge of the light shielding electrode. And a step of performing the ion implantation of the impurity into the semiconductor layer through the processed second coating film at a high dose so that a total of three types of impurities having different concentrations are contained. Forming a region.

Thus, the boundary between the two types of impurity-containing regions having different concentrations in the semiconductor layer is strictly defined by the gate electrode, and the boundary between the other two types of impurity-containing regions having different concentrations is dedicated. Since it is strictly defined by the provided light-shielding electrode, by using these designs together, three types of impurity-containing regions having different concentrations can be formed with high precision and accuracy.

[0016]

1 to 8 are sectional views showing steps of a manufacturing method according to an embodiment of the present invention. First,
Referring to FIG. 1, a gate electrode (11) and a mask electrode (20) are formed by forming a Cr film on a substrate (10) and etching it. The gate electrode (11) is connected to a gate line which is a scanning signal supply line. The masking electrode (20) is formed of p-Si (1
It is formed corresponding to at least a part of the high concentration region (N +) of 3). A gate insulating film (12) made of SiNx and SiO2 is formed on the entire surface covering the gate electrode (11) and the masking electrode (20), and an amorphous silicon (12) is formed on the gate insulating film (12). a-S
i) is formed. This a-Si film is crystallized by excimer laser annealing to form polycrystalline silicon, ie, polysilicon (p-Si) (13). This p-
A predetermined island shape is formed by etching Si (13), and SiO2 (14) covering this is formed.

In FIG. 2, a positive photoresist (PR) is applied and formed on SiO 2 (14), and light is irradiated from above the substrate (10) through a reticle (MSK) masking the gate electrode (11). Irradiation is performed to expose the front surface, and light is irradiated from below the substrate (10) to expose the back surface. The pattern edge of the reticle mask (MSK)
It is located between the gate electrode (11) and the mask electrode (20). Therefore, the alignment of the reticle (MSK) is not required to be so precise, and is performed by surface exposure so as to have an edge between the gate electrode (11) and the mask electrode (20). In order to compensate for this, the backside exposure is performed to exactly correspond to the edge of the gate electrode (11), and the area other than the gate electrode (11) is exposed with high precision and becomes soluble in the developing solution. Denatured. The surface exposure and the back surface exposure may be performed simultaneously or separately, or the surface exposure may be omitted.

In FIG. 3, after developing the resist (PR), the SiO 2 (14) is etched to form the gate electrode (1).
1) Leave it only on the top to make a stopper (14). With the resist (PR) remaining, ion implantation of phosphorus as an N-type impurity is performed at a low dose of the order of 10 13, and p-Si (13) other than the stopper (14) region is doped at a low concentration. , LD region (N−). The resist (PR) is exposed by the surface exposure substantially corresponding to the region other than the gate electrode (11), and the edge of the gate electrode (11) is strictly reflected by the back surface exposure, so that the resist (PR) is formed on the gate electrode (11). Only left. That is, the edge of the LD region (N−) is extremely accurately formed on the gate electrode (1−).
The edge of 1) is matched.

In FIG. 4, a positive photoresist (P
After stripping R), a negative photoresist (NR) is applied and formed, and surface exposure is performed via a reticle (MSK) that masks a region other than the N-ch gate electrode (11), and back surface exposure is performed. . Reticle mask (MSK)
The gate electrode (1
Positioning is performed so that an edge is located between 1) and the mask electrode (20), and front surface exposure is performed. However, exposure that strictly reflects the edge of the mask electrode (20) is performed by back surface exposure. Will be That is, a reticle mask (MSK)
The back surface exposure using the mask electrode (20) is performed in such a manner as to compensate for the low accuracy of the alignment. Therefore, the resist (N) is formed along the edge of the mask electrode (20).
The exposure of R) is carried out strictly, and is denatured insoluble in a developer.

In FIG. 5, after the resist (NR) is developed, phosphorus ions are implanted at a high dose of the order of 10 15 using the resist (NR) as a mask, and a high-concentration region (N + ) Is formed. Since the edge of the negative resist (NR) is strictly and accurately defined according to the pattern edge of the mask electrode (20), a certain distance from the gate electrode (11), that is, the intrinsic region (IN), with respect to N-ch. A high concentration region (N +) is formed at a distance. That is, the LD region (N−) interposed between the high-concentration region (N +) and the intrinsic region (IN) is strictly and accurately formed.

In FIG. 6, after stripping the negative resist (NR), a positive resist (PR) is formed, and exposure is performed using the N-ch as a mask. Thereby, the resist (PR) is denatured so as to be soluble in the developer only on the P-ch. In FIG. 7, after the resist (PR) is developed, boron, which is a P-type impurity, is ion-implanted by using the resist as a mask, so that in the P-ch, just below the implantation stopper (14) is left in the intrinsic region (IN). Thus, a high-concentration region (P +) in which another region becomes a source and a drain is formed.

In FIG. 8, after removing the resist (PR), an interlayer insulating film (15) of SiNx or the like is formed, a predetermined contact hole is formed by etching, and Al /
Source and drain electrodes (16) are formed by Mo film formation and etching, and are connected to the high-concentration regions (N +, P +) that are the source and drain of p-Si (13), respectively.

These source and drain electrodes (16)
Is extended to a CMOS connection in the driver portion, and is connected to a display electrode for driving liquid crystal and a drain line as a signal voltage supply line in the pixel portion. In the present invention, the boundary between the intrinsic region (IN) and the LD region (N−) is defined using the edge of the gate electrode (11), and the edge of the mask electrode (20) is used. , LD region (N−) and high concentration region (N +). Gate electrode (11) and mask electrode (20)
Are simultaneously formed using one mask, so that p-S
The three regions (IN, N-, N +) of i (13) are formed with high accuracy by using these electrodes (11, 20).

[0024]

As is apparent from the above description, in the present invention, a single layer of electrodes serving as a mask at the time of exposure is formed for exclusive use, or a coating film serving as an injection mask is formed by utilizing the edges of these electrodes. Is formed, and impurities are implanted at various concentrations using this, whereby a semiconductor layer having a plurality of impurity-containing regions having different concentrations can be formed. Since the boundaries between the plurality of impurity-containing regions are strictly defined according to the edge of the electrode, each impurity-containing region can be formed with the same precision as the electrode.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 substrate 11 gate electrode 12 mask electrode 13 gate insulating film 14 p-Si 15 interlayer insulating film 16 source and drain electrodes

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 627C

Claims (5)

[Claims] In a semiconductor device in which a semiconductor layer and a single electrode layer or a plurality of electrode layers are formed, the semiconductor layer contains a plurality of impurities of different concentrations having a boundary reflecting at least a part of the shape of the electrode. A semiconductor device having a region. 2. In a semiconductor device in which a semiconductor layer and an electrode layer are formed in a single layer or a plurality of layers, the semiconductor layer includes an intrinsic region substantially containing no impurities and a low concentration region containing impurities at a low concentration. A boundary between the intrinsic region and the low-concentration region, and a boundary between the low-concentration region and the high-concentration region. A semiconductor device that matches at least a part of the shape of the semiconductor device. 3. A method of manufacturing a semiconductor device having an electrode layer, an insulating layer, and a semiconductor layer formed on a substrate, wherein the semiconductor layer has a plurality of impurity-containing regions having different concentrations. , At least part of the edge,
A method of manufacturing a semiconductor device, comprising: forming a coating film corresponding to at least a part of an edge of the electrode; and forming a plurality of impurity-containing regions having different concentrations according to an inverted shape of the coating film. 4. A gate electrode, an insulating layer covering the gate electrode, a semiconductor layer having a plurality of impurity-containing regions having different concentrations on the insulating layer, and source and drain electrodes connected to the semiconductor layer are formed on the substrate. In the method for manufacturing a semiconductor device, a step of forming a light shielding electrode at the same time as the gate electrode on the substrate; a step of forming the insulating layer covering the gate electrode and the light shielding electrode; A step of forming a semiconductor layer; a step of forming a coating film on the semiconductor layer; and at least a part of an edge of the coating film is an edge of the gate electrode and / or the light shielding electrode. Processing the semiconductor layer into a shape conforming to at least a part thereof, and ion-implanting the impurity into the semiconductor layer through the processed coating film, so that at least two types of impurities having different concentrations are obtained. Forming a pure substance containing region. 5. A gate electrode, an insulating layer covering the gate electrode, a semiconductor layer having a plurality of impurity-containing regions having different concentrations on the insulating layer, and source and drain electrodes connected to the semiconductor layer are formed on the substrate. In the method for manufacturing a semiconductor device, a step of forming a light shielding electrode at the same time as the gate electrode on the substrate; a step of forming the insulating layer covering the gate electrode and the light shielding electrode; A step of forming a semiconductor layer; a step of forming a first coating film on the semiconductor layer; at least a part of an edge of the first coating film is an edge of the gate electrode. A step of processing into a shape conforming to at least a part, by performing ion implantation of the impurity into the semiconductor layer through the processed first coating film at a low dose amount,
A step of forming two types of impurity-containing regions having different concentrations; a step of forming a second coating film over the semiconductor layer; Processing a shape conforming to at least a part of an edge of the light shielding electrode; and performing ion implantation of the impurity into the semiconductor layer at a high dose through the processed second coating film. By
Forming a total of three types of impurity-containing regions having different concentrations.