JPH10243337A - Still picture recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record and read out data without changing the number of input/ output pins on a main body and a memory card even when the number of memories on the memory card is changed while freely attaching and detaching the main body of an electronic still camera and memory card. SOLUTION: The memory card freely attachable and detachable to the electronic still camera is provided with plural memories 23, and a chip selector 26 for recording or reading out data while generating an address based on a start address for recording or reading out the data, and selecting any correspondent memory 23 out of plural memories 23 based on that start address when that address is inputted to any one of these memories 23 at least.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a still image recording device such as an electronic still camera.

[0002]

2. Description of the Related Art In a camera widely used at present, a silver halide film is used as a recording medium, and this film is developed by chemical processing after photographing, so that an image photographed by the camera can be instantly viewed. That was impossible.

[0003] In recent years, video cameras that record analog video on a tape-shaped magnetic recording medium have appeared, and it has become possible to instantly see and hear images and sounds taken by the video camera. However, the image quality is poor because the analog data is analog, and the data is large and heavy because a mechanical drive system is required.

Therefore, in recent years, a still image recording apparatus including a semiconductor memory element capable of electrically rewriting data and a liquid crystal display element, that is, an electronic still camera has been developed.

[0005] This electronic still camera can record a subject as a still image in a semiconductor memory device without having a mechanical drive system, so it is small and lightweight, and an image of the photographed subject can be directly displayed on a liquid crystal display device. It can be projected to

Although the appearance of the electronic still camera seems to have almost satisfied the needs of the user, the number of recordings is limited by the relationship between the capacity and the image quality of the semiconductor memory element which is merely mounted on the camera body in advance. From the user,
There is a demand for increasing the capacity of a recording medium. For this reason, it is necessary to meet this demand while standardizing the attachment / detachment part between the camera body side and the recording medium side, that is, the interface.

By the way, once an interface is standardized, the number of data lines, control lines, and the like is determined, so that it is necessary to transmit and control data while making full use of the standardized interface.

[0008]

However, in such a still image recording apparatus, when the number of semiconductor storage elements in the recording medium is increased and the storage capacity is increased, data lines and control lines between the camera body and the recording medium are not provided. However, there is a problem that the number increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and while recording / removing a camera main body and a recording medium, data recording and data recording on a recording medium having a plurality of semiconductor memory elements built-in. It is an object of the present invention to provide a still image recording device capable of controlling reading.

[0010]

SUMMARY OF THE INVENTION A still image recording apparatus according to the present invention comprises an image pickup means for picking up a still image, a common bus line for transmitting at least data of the still image picked up by the image pickup means, and this common bus. A main body portion having a main body side terminal portion connected to a line, and a recording medium having a medium side terminal portion detachably attached to the main body side terminal portion, wherein the main body portion is provided inside the recording medium. Means for sending a start address for specifying a recording start address of the still image and the data of the still image to the recording medium through the common bus line. Or a plurality of recording means which are branched and connected via input / output control means connected to the medium-side terminal section and which can write and read the data, and each terminal from the common bus line. An address generating means for generating an address with the start address inputted through,
Selecting means for selecting at least one of the plurality of recording means based on an address of the address generating means, wherein the data is recorded or read through the common bus line.

According to the present invention, a plurality of recording means, that is, semiconductor storage elements, are provided in a recording medium, and a start address is sent from the main body to the recording medium through a common bus line, and the address is recorded on the recording medium side using the start address. Since the data is generated and the data is written or read by selecting the recording means based on this address, while the camera body and the recording medium are made detachable, the data is transferred to a recording medium having a plurality of built-in recording means. Data recording and reading can be controlled.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic perspective view of an electronic still camera according to one embodiment of the present invention.

The electronic still camera shown in FIG. 1 includes a camera main body 1 and a memory card that is detachable from the main body 1. The camera body 1 includes a lens barrel 3, a viewfinder 4, a shutter 5, and the like, like a normal camera.
An opening 6 into which the memory card 2 is inserted is provided. The memory card 2 fulfills the function of a film used in a normal camera.

FIG. 2 is a block diagram for explaining the configuration of the camera body 1.

In FIG. 1, a lens indicated by reference numeral 7 is disposed in the lens barrel 3, and an image of a subject is projected on the CCD 8 disposed on the back of the lens 7 by the lens 7. The CCD 8 outputs an analog electric signal in accordance with the brightness of the image projected in this manner. This electric signal is converted into a digital signal by an A / D converter 9 and then converted into a band compression circuit. The band is compressed by 10 and input to the memory card control circuit 11.

Reference numeral 41 denotes a microphone arranged outside the main body 1, and an audio signal inputted from the microphone 41 is supplied to the memory card control circuit 11 via an A / D converter 42 and a digital audio circuit 43. Is input to

The CPU 12 controls the entire electronic still camera including the memory card 2, and controls the driving of the CCD 8 via the driving system 13, and controls the compression ratio of the band compression circuit 10. , And also controls the memory card control circuit 11 and the memory card 2.

FIG. 3 shows a memory card control circuit 11.
FIG. 2 is a block diagram for describing a configuration around the device.

In FIG. 1, reference numeral 14 denotes a band compression circuit 1.
0 or an I / O control circuit for performing input / output control between the CPU 12 and the memory card 2 for exchanging data signals between them.

That is, a data input terminal indicated by reference numeral 15 is for inputting a data signal relating to an image from the band compression circuit 10, and a data input terminal indicated by reference numeral 44 is a data signal relating to audio from the digital audio circuit 43. The data signal and the data signal generated by the CPU 12 are sent from the data input / output terminal 16 to the memory card 2 via the I / O control circuit 14.

On the other hand, the data signal from the memory card 2 input from the data input / output terminal 16 is transmitted to the I / O control circuit 1
4 to the CPU 12.

Here, the CPU 12 and the I / O control circuit 14
A memory 17 is interposed on the data line between the two, and an interface of the data transfer speed is provided between them. That is, the data signal input / output by the CPU 12 is a serial signal and has a low speed, while the data signal input / output by the I / O control circuit 14 is a parallel signal and has a high speed. The serial signal or the parallel signal is converted into a parallel signal or a serial signal, respectively.

Reference numeral 18 denotes an address generation circuit which sequentially generates an address signal corresponding to an initial address value designated by the CPU 12 and an address value obtained by sequentially adding "1" to this value. This address signal is sent from the address output terminal 19 to the memory card 2.

Further, reference numeral 20 denotes a timing signal generation circuit, and this timing signal generation circuit 20
2, the I / O control circuit 14, the memory 1
7. A predetermined timing signal is generated from the address generating circuit 18 or the timing output terminal 21 to the memory card 2.

FIG. 4 is a schematic view of the memory card 2. The memory card 2 has a plurality of semiconductor memory elements (RAM), for example, a plurality of electrically rewritable memories 23 such as an E ² ROM on a substrate 22. Are mounted and connection terminals 24 connected to the camera body 1 are arranged at one end.

FIG. 5 is a block diagram for explaining the configuration of such a memory card 2. As shown in FIG. Reference numeral 24a is the main body 1.
A data input / output terminal connected to the data input / output terminal 16 on the side, and the data input / output terminal 24a is connected to each data input / output terminal of the plurality of memories 23 via the I / O control circuit 25.

Reference numeral 24b denotes an address input terminal connected to the address output terminal 19 of the main body 1, and the address input terminal 24b is connected to each address input terminal of each memory 23 and the chip select circuit 26. .

Reference numeral 24c denotes a timing input terminal connected to the timing output terminal 21 of the main body 1,
This timing input terminal 24c is connected to each timing input terminal of each memory 23.

Note that the chip select circuit 26 is
A predetermined memory 23 to be operated according to an address signal from the side is selected.

FIG. 6 is a memory map for explaining a memory area constituted by a large number of memories 23 mounted on the memory card 2.

As shown in FIG. 3, the memory area includes a card header area 27 in which data unique to the memory card 2 itself is recorded, and a start address 28a and an end address 28b of an area in which each image data is recorded.
Are stored in the image data area 29 in which the image data is actually recorded.

The card header area 27 has a card number where data unique to the memory card 2 itself is recorded. The remaining memory capacity area 2 in which the remaining data of the area where the data can be written in the area 27a and the image data area 29 is recorded.
7b, a captured image number area 27c in which data of the number of captured images of the memory card 2 is recorded, and an image data final address area 27d in which data of the last use address of the image data in the image data area 29 is recorded.

The data area 29 is recorded in one-screen data areas 29a,... Divided for each screen, and these one-screen data areas 29a are respectively composed of an image header area 29b and an image in which actual image data is recorded. And a data area 29c.

The image header area 29b includes an information classification area 29d indicating what kind of data, for example, image and audio data is recorded in the image data area 29c of the one screen data area 29a, and an image data area. 29c
What kind of image processing system, for example, NTSC, CCIR
A system area 29e indicating whether data is recorded by a method such as a method, a screen number area 29f in which screen number data is recorded, for example, an image quality in which data of an image quality mode set by a compression ratio of the band compression circuit 10 is recorded. It includes a mode area 29g, time areas 29h to 29m in which data of the recorded time is recorded, a title area 29n in which data of a title of a recorded image is recorded, and the like. Next, the photographing operation of the electronic still camera configured as described above will be described.

First, when a memory card is inserted into the camera body 1 through the opening 6, the terminals 16, 19, 21 of the memory card control circuit 11 in the body 1 and the terminals 24a, 24b, 24c in the memory card 2 are connected. Connected respectively.

Thereafter, the CPU 12 causes the timing signal generation circuit 20 to generate a signal for reading data from the memory 23, and causes the address generation circuit 18 to generate an address of the card header area 27.

Thus, a signal relating to data in the card header area 27 of the memory 23 in the memory card 2 is transferred to the CPU 12 via the I / O control circuit 25, the I / O control circuit 14, and the memory 17, and the CPU 12 Whether or not image data can be written from the data in the card header area 27 to the memory 23 of the memory card 2 is determined by writing the next image data from an address (start address) to an address (end address) in the memory. Confirm whether it is good, and calculate.

If the image data can be written, the CPU 12 sets the start address and the end address in the address generation circuit 18.

Thus, the camera is operated by the user's shutter O
It is in a state of waiting for N.

When the user presses the shutter 5, C
The PU 12 causes the timing signal generation circuit 20 to generate a signal for writing data to the memory 23,
The address signal set as described above is generated at a predetermined timing for the address generation circuit 18.

Therefore, thereafter, the image data signal from the CCD 8 is sent to the memory card 2 via the A / D converter 9, the band compression circuit 10, and the I / O control circuit 14. At the same time, the address signal generated by the address generation circuit 18 is also sent to the memory card 2 side.

Thus, in the memory card 2,
Address generation circuit 1 for image data area 29 of memory 23
The image data is sequentially written to the address corresponding to the address signal from No. 8.

When such writing is completed, the CPU 1
2 is input to the memory 23 via the memory 17, the I / O control circuit 14, and the I / O control circuit 25, and the card header area 27 is updated. The data signals of the start address and the end address corresponding to the written image data are also sent from the CPU 12 to the memory 23, and these data are written in the direct area 28. After this, C
The PU 12 causes the timing signal generation circuit 20 to generate a signal for stopping a series of write operations to the memory 23.

As described above, in the electronic still camera of this embodiment, the memory card 2 for recording image data is
Since the data of the M, E ² ROM and the like are constituted by the green recording means capable of electrically rewriting data, the means for writing to the recording means can be constituted by electric elements. In addition, the size of the device is reduced and the current consumption is reduced.

On the other hand, in the memory 23 of the memory card 2, as described above, the memory area has a card header area 27 in which data unique to the memory card 2 itself is recorded.
Strike address 28 of the area where each image data is recorded
a and an end address 28b, and a director area 28 in which image data is actually recorded, and an image data area 29 in which each image data is actually recorded. These areas are further subdivided according to functions. Therefore, address management can be performed reliably and easily.

Incidentally, between the main body 1 and the memory card 2, as described above, image data, address data,
In addition, since signals need to be exchanged at various timings, usually a minimum number of input / output pins corresponding to these are required.

In the second embodiment shown below, the number of input / output pins is reduced and the attachment / detachment of the memory card 2 is improved.

FIG. 7 is a diagram for explaining the configuration of the memory card control circuit 11 'and its peripheral components which are different from the above-described embodiment in the second embodiment.

The memory card control circuit 11 'shown in FIG. 7 differs from the memory card control circuit 11 shown in FIG. 3 in that the address generation circuit 18 is eliminated and a status generation circuit 30 is newly provided.

FIG. 8 is a diagram showing the configuration of the memory card 2 'of the second embodiment. Reference numeral 24a denotes a data input / output terminal connected to the terminal 16 of the main body 1, and the data input / output terminal 24a is connected to each data input / output terminal of the memory 23 via the I / O control circuit 25.

Reference numeral 24d denotes a terminal 19 'on the main body 1 side.
The status input terminal 24d is connected to the status decoder 31. Further, reference numeral 24e denotes a timing input terminal connected to the terminal 21 of the main body 1, and the timing input terminal 24e is connected to the timing control circuit 32.

Reference numeral 33 denotes an address counter for generating a predetermined address.

In this embodiment, the data bus and the address bus are shared. That is, the image data signal and the address signal are transferred to the shared bus line indicated by reference numeral 34. As the address signal transferred in this manner, only the start address data for starting the reading or writing of the image data is transferred instead of the address data corresponding to each image data as in the first embodiment described above. The address data corresponding to each image data is generated by the address counter 33, which is input to the memory 23 and the chip select 26.

By the way, since the data bus and the address bus are shared, it is necessary to distinguish whether the signal being transferred is an image data signal or an address signal. Also, for image data, the transfer direction must be distinguished.

Therefore, the status generating circuit 3 is provided on the main body 1 side.
0, a status decoder 31 is provided on the memory card 2 side, and a status signal shown in FIG. 9 is sent from the status generation circuit 30 to the status decoder 31, and an enable signal is sent from the timing generation circuit 20 to the timing control circuit 32. You.

In FIG. 9, "x" indicates don't care,
“0” indicates a LOW level, and “1” indicates a HIGH level.

Then, case 1 does not operate, that is, the bus line 34 is in a high impedance state. Case 2 to case 7 are modes for transferring read or write address data. Note that the existence of a plurality of modes as described above means that the maximum
This is because the bus line 34 has only an 8-bit transfer capability while it has 24 bits. That is, case 2 is a mode in which the lower byte start address for reading is transferred. Case 3 is a mode in which the lower byte start address for writing is transferred. case 4 is a mode in which the middle byte start address for reading is transferred. case 6
Is a mode for transferring an upper start address for reading. case 7 is a mode in which the upper start address for writing is transferred. However, by combining these modes, it is possible to transfer start address data for each of the read and write cases. Case 8 is a mode for outputting read data, and case 9 is a mode for inputting write data.

As described above, in the second embodiment, writing of data to the memory card 2 or reading of data from the memory card 2 is performed using these modes. That is, when reading arbitrary data from the memory card 2, the CPU 12 first sets case 2, case 4,
The start address corresponding to the data to be read in the case 6 mode is loaded from the status generation circuit 30 into the address counter 33, and the data required in the case 8 mode is read.

The above operation completes the read preparation.

Then, the address counter 33 starts counting up from the loaded address, and supplies the value to the memory 23. As a result, data corresponding to these addresses is read from the memory 23.

On the other hand, when writing data to the memory card 2, the CPU 12 first supplies a start address corresponding to the data to be written in the mode of case 3, case 5 or case 7 from the status generating circuit 30 to the address counter 3.
Then, data is written into the memory 23 in the case 9 mode. With the above operation, the preparation for writing data is completed.

The address counter 33 starts counting up from the loaded address, and supplies the value to the memory 23. As a result, data is written in the memory 23 corresponding to these addresses.

Next, a procedure for reproducing the image data recorded on the memory card 2 using a reproducing device (not shown) will be described.

When the memory card 2 is mounted on the player, the player reads card header information and directory information from the memory card 2 and reads the number of screens recorded on the memory card 2 and the start address of each recorded image. , Detecting the end address. When the user specifies a screen to be reproduced, the start address corresponding to the screen is transferred to the memory card 2, and the target image data is read and reproduced. As described above, according to the second embodiment, a plurality of memories provided inside the memory card 2 by specifying addresses from the main body 1 without changing the number and arrangement of the input / output pins of the removable memory card 2 23 can be individually controlled to record and read data.

It should be noted that the still image and the sound may be recorded simultaneously in separate memories 23 as described above, or may be recorded independently.

[0067]

As described above, according to the still picture recording apparatus of the present invention, the start address is transmitted from the main unit through the common bus line while the detachment of the recording medium is improved with the minimum number of terminals. , Data recording and reading can be individually controlled for a plurality of recording means provided inside the recording medium.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of an electronic still camera according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing the internal configuration of the electronic still camera of FIG.

FIG. 3 is a block diagram showing a configuration of a memory card control circuit shown in FIG. 2;

FIG. 4 is a schematic perspective view showing the inside of the memory card shown in FIG. 1;

FIG. 5 is a block diagram showing a configuration of the memory card shown in FIGS. 1 and 4;

FIG. 6 is a view for explaining a memory area of a memory in the memory card shown in FIG. 5;

FIG. 7 is a diagram illustrating a configuration of a memory card control circuit according to a second embodiment of the present invention and peripheral components thereof;

FIG. 8 is a diagram showing a configuration of a memory card according to the second embodiment.

FIG. 9 is a diagram showing a status signal sent in the second embodiment.

[Explanation of symbols]

1 camera body, 2 memory card, 7 lens, 8 ...
CCD, 9 A / D converter, 11 memory card control circuit, 12 CPU, 14, 25 I / O control circuit, 17 memory, 18 address generation circuit, 20 timing signal generation circuit, 23 memory, 27 card header area, 28 directory area, 29 data area, 41 microphone, 42 A / D converter, 43 digital audio circuit.

Claims (1)

[Claims] 1. A main body having an image pickup means for picking up a still image, a common bus line for transmitting at least data of a still image picked up by the image pickup means, and a main body side terminal connected to the common bus line. And a recording medium having a medium-side terminal portion detachably attached to the main-body-side terminal portion, wherein the main body portion includes a start address for designating a recording start address in the recording medium and the still image. Means for transmitting the data to the recording medium through the common bus line, wherein the recording medium is connected to the medium-side terminal portion by branching or connected to the medium-side terminal portion. A plurality of recording means, which are branched and connected via a control means and which can write and read the data, and a start address input from each of the common bus lines through each terminal unit; Address generating means for generating an address, and selecting means for selecting at least one of the plurality of recording means based on the address of the address generating means, and recording or reading the data through the common bus line. A still image recording device.