JPH10243259A - Device and method for processing image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly display the processing result by designating the characteristics of non-linear processing to image data through a GUI. SOLUTION: A personal computer 72 displays a GUI image for input on a monitor. When a user designates non-linear characteristics through an input device 70 to the GUI image, the personal computer 72 extracts a diagonal line function, showing non-linear characteristics and displays it in the GUI image. Further, the personal computer 72 generates a program for a linear array type multi-parallel processor (DSP 80) to execute non-linear processing which is shown by the extracted diagonal function and downloads the generated program to the DSP 80.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for supplying image data to a plurality of element processors.
eam) An image processing apparatus and a method for controlling and performing image processing in parallel.

[0002]

2. Description of the Related Art RG
A plurality of types of color signals such as a B signal, a YIQ signal, and a YCrCb signal (hereinafter, a luminance signal Y is also treated as a color signal) are processed in fields such as image signal processing and television signal processing. Correction of video camera optical system, correction of display device (display) nonlinearity,
Alternatively, it may be necessary to perform non-linear processing such as color correction and γ (gamma) correction on these various color signals in order to provide a special effect or the like.

In the past, non-linear processing on these various color signals was performed by analog processing. However, if the color signal is processed in an analog manner, the processing will be non-uniform between the components of the color signal, or a temporal change will occur due to the repetition of the processing, and the image will be degraded. Therefore, today, nonlinear processing on color signals is generally performed by digital processing.

As a method of nonlinear processing by digital processing, for example, a method using a dedicated logic circuit for realizing each nonlinear input / output characteristic by broken line approximation using a logic circuit such as a delay circuit, a multiplication circuit and an addition circuit will be described. be able to. However, in the former method, since a logic circuit needs to be prepared for each processing, the processing content lacks flexibility, and this method is rarely adopted.

As another method of nonlinear processing by digital processing, for example, there is a method of associating input data values with output data values via a memory. According to this method, the content of the nonlinear processing can be easily changed only by changing the storage content of the memory that associates the input data with the output data. However,
Conventionally, a method of designating the processing content using a GUI (graphical user interface) has not been established. Moreover, the confirmation of the result of the non-linear processing is performed by once recording the image data obtained by the processing on a VTR tape or the like, and reproducing and displaying the recorded image data, which is very troublesome. .

A device for associating input / output data by this method is usually configured exclusively for non-linear processing such as color correction and gamma correction, and performs other processing by placing a dedicated device in front or behind. There is a need. Therefore, even when the color correction and the γ correction are performed in association with the input / output data, it is necessary to prepare dedicated hardware in accordance with other processes, similarly to the method using the logic circuit.

On the other hand, in order to perform various image processing flexibly,
A method of processing image data by software using a DSP (digital signal processor) is considered. However, although DSPs are generally suitable for linear arithmetic processing, they are not suitable for nonlinear processing such as color correction and gamma correction, and there have been few examples of using DSPs for nonlinear processing.

The present invention has been made in view of the above-mentioned problems of the prior art. For example, there is provided an image processing apparatus and method capable of performing non-linear processing such as color correction on image data using a DSP. The purpose is to provide. Further, the present invention describes the content of the non-linear processing such as color correction as the components (Y, Cr, Cb, R,
(G, B, etc.) can be arbitrarily set by using a GUI, and an image processing apparatus and a method thereof capable of immediately confirming a result of a color correction process or the like on a GUI screen are provided. Aim.

[0009]

In order to achieve the above object, an image processing apparatus according to the present invention provides an input image displaying an input image indicating input / output characteristics between input image data and output image data. Display means, designated data accepting means for accepting designated data input according to the displayed input image and designating the input / output characteristics, and input / output characteristics for extracting the input / output characteristics from the received designated data Extraction means, input / output characteristic image display means for displaying an input / output characteristic image indicating the extracted input / output characteristics, and the input image data and the output image data are in a relationship indicated by the extracted input / output characteristics Image data processing means for processing the input image data to generate the output image data.

Preferably, the input image display means displays a graph of the initial value of the input / output characteristics, and the designated data receiving means adds and adds at least a passing point of a curve of the displayed graph. The first specified data for specifying the position of the passing point on the graph, the second specified data for specifying the changed position of the added passing point, and the changed position of the changed passing point, Accepting third designated data designating deletion of the passing point, and the input image display means changes the graph of the input / output characteristics based on the accepted first designated data to third designated data I do.

Preferably, the image data processing means includes input / output characteristic data generating means for generating input / output characteristic data for associating the input image data with the output image data in accordance with the extracted input / output characteristics. Converts the value of the input image data into the value of the output image data by a memory mapping method based on the generated input / output characteristic data.

Preferably, the image data processing means processes the input video data based on a set program to generate the output video data, and outputs the image data based on the extracted input / output characteristics. The processing means has a program generating means for generating a program for generating the output image data from the input image data.

Preferably, the image data processing means includes
It is a linear array type multi-parallel processor controlled by IMD.

[0014] The input image display means, for example,
The color signal components (R, G, B,
Y, I, Q, etc .; input and output indicating that the value (x) of the input image data is not changed and output as the value (y) of the component (output image data) of the color signal obtained as a result of the processing A graph of the initial value of the characteristic (y = x) is displayed in the window of the GUI image for each component of the color signal.

The user adds, for example, using a mouse to each window of the color signal components of the GUI image, adding a passing point of a curve of the displayed graph, a position of the added passing point on the graph, When the change of the position of the added passing point and the change of the position after the change or the deletion of the added passing point are designated, the designated data receiving means accepts designated data indicating these designations for each component of the color signal.

The input / output characteristic extracting means extracts the input / output characteristic indicated by the received designated data, for example, a function (line function) indicated by a broken line for each component of the color signal. The input / output characteristics image display means displays a graph showing a line function indicating the extracted input / output characteristics in each window of the color signal components on the GUI screen when all the designated data has been input.

The input / output characteristic data generating means converts input / output characteristic data for associating the value of the input image data with the output image data in accordance with the extracted input / output characteristic, for each color signal component, based on the extracted line function. Generate.
The image data processing means stores, for example, the input / output characteristic data, takes the input image data as an address input, and outputs the value of the input / output characteristic data stored at the address indicated by the value of the input image data as output image data According to the memory mapping method described above, input image data is processed for each color signal component to generate and display output image data.

For example, when the input image data is processed for each color signal component using a SIMD-controlled linear array type multi-parallel processor to generate output image data, the program generating means outputs the extracted input data. A program for realizing the output characteristics is created and downloaded to the processor.

Further, the image processing method according to the present invention displays an input image indicating input / output characteristics between input image data and output image data, and inputs the image in accordance with the displayed input image. Accepting specified data specifying output characteristics, extracting the input / output characteristics from the received specified data, displaying an input / output characteristics image indicating the extracted input / output characteristics, displaying the input image data and the output image data And so that the extracted input / output characteristics show a relationship,
The input image data is processed to generate the output image data, and the generated output image data is displayed.

Preferably, a graph of an initial value of the input / output characteristic is displayed, and a passing point of a curve of the displayed graph is added, and first designation data for designating a position on the graph of the passing point to be added. And second designated data for designating a change in the position of the added passing point, a changed position of the passing point to be changed, and third designated data for designating deletion of the added passing point. At least accepted, said accepted first
The graph of the input / output characteristics is changed based on the specified data to the third specified data.

Preferably, input / output characteristic data for associating the input image data with the output image data in accordance with the extracted input / output characteristic is generated, and a memory mapping method is performed based on the generated input / output characteristic data. To convert the value of the input image data into the value of the output image data.

Preferably, the input image data is processed based on a set program to generate the output image data, and the output image data is converted from the input image data based on the extracted input / output characteristics. A program to be generated is created, the generated program is executed, the input image data is processed, and the output image data is generated.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Hereinafter, a first embodiment of the present invention will be described. Conventionally, NTSC and PAL have been used in image display devices (displays) using a CRT (cathode ray tube) such as a television receiver.
When displaying image signals of various image transmission methods such as
A method has been adopted in which an image signal is processed in an analog manner according to each of these image transmission methods, and the horizontal scanning frequency is changed to display the image signal.

On the other hand, with the recent advance in digital signal processing technology, a method has been adopted in which the image data of each image transmission method is displayed by making the horizontal scanning frequency of the image display device coincide with the image data by digital processing. Is coming. The image resolution differs for each image transmission method (NTSC, PAL, etc.), and the number of pixels in the vertical and horizontal directions of the image also differs. In addition to the NTSC and PAL systems,
There are various image transmission systems such as the HDTV system, and the standard of the resolution (the number of pixels) differs for each system. In addition, there are various image display devices, and in fixed pixel display devices such as recent LCDs, there are displays having various pixel sizes.
Therefore, when the same digital image processing system processes and displays all the image data of the image transmission method, the image data of a certain image transmission method is
There is a need for conversion to image data suitable for the display device, etc., due to an “interpolation filter”.

Hereinafter, a filtering method using an interpolation filter for converting the number of pixels of an image will be described by taking as an example the process of enlarging / reducing an image and converting a sampling frequency (number of pixels). Each of the enlargement / reduction processing of the image and the conversion processing of the sampling frequency of the image (the conversion processing of the number of pixels between image transmission methods having different resolution standards) is performed for each pixel of the original image (original image). This is realized by performing an operation of calculating pixel data that did not exist in the original image from the position (1) and data (pixel data) expressing the luminance and color of the pixel.

The interpolation filter filters the image data by performing operations for enlarging / reducing the image and converting the sampling frequency, so that these processes can be realized using the interpolation filter. it can.

FIG. 1 is a diagram exemplifying an arrangement of pixels of an original image. In practice, an image is often composed of many pixels, but for simplicity of description and illustration,
FIG. 1 exemplifies an image composed of a small number of pixels (6 vertical pixels × 8 horizontal pixels). In FIG. 1, the circles indicate the positions of the pixels of the original image (hereinafter, the same applies to each drawing). ).

An image whose length is enlarged while maintaining the pixel arrangement
Enlargement processing First, referring to FIGS. 2 and 3, the original image shown in FIG. 1 is replaced with the pixel arrangement (pixel interval and positional relationship) shown in FIG. 1 without changing the image display standard itself. The image enlargement process will be described by taking as an example a case where the image is enlarged by (10/7) times by the length ratio while keeping the same.

FIG. 2 is a diagram showing an enlarged image in which the length is enlarged to (10/7) times while maintaining the arrangement of pixels of the original image shown in FIG. 1 without changing the image display standard itself. It is. When the original image (FIG. 1) is enlarged while maintaining the arrangement of the pixels, an enlarged image shown in FIG. 2 is obtained. That is, since the enlargement magnification of the length of the image is 1.429 (≒ 10/7) times, the length of one side of the enlarged image (enlarged image) is 1.429 times, and the number of pixels is about 1.429. Increase by a factor of ^two .

Specifically, for example, in the horizontal direction (horizontal scanning direction), the number of pixels of the original image is 8, while the number of pixels of the enlarged image is 11 or 12 [≒ 8 × 10 /
7 (11.429)] pixels. Therefore, the positional relationship between the pixels of the original image and the positional relationship of the pixels of the enlarged image change, and the pixel pixel data of the enlarged image has a different value from the corresponding pixel data of the original image.

FIG. 3 is a diagram showing the horizontal positional relationship between the pixels of the original image shown in FIG. 1 and the pixels of the enlarged image obtained by enlarging the length of the original image by an enlargement factor (10/7). It is. In FIG. 3, the symbol Ri (i = 1, 1) on the upper side of the horizontal axis
2,...) Represent pixels of the original image, and the symbol Q below the horizontal axis
i indicates a pixel of the enlarged image. FIG. 3 shows only the positional relationship between the pixels of the original image and the pixels of the enlarged image in the horizontal direction. However, the pixels of the original image and the pixels of the enlarged image in the direction (vertical direction) perpendicular to the horizontal scanning direction are shown. Is also the same.

As shown in FIG. 3, in terms of the pixel position with respect to the image projected on the screen, the pixel Ri of the original image is used.
In contrast, the pixel Qi of the enlarged image is (10 /
7) They are arranged at double intervals. As will be described later, the pixel data of each pixel of the enlarged image includes a predetermined number of pixels around each pixel of the enlarged image in accordance with the correspondence between each pixel of the original image and the pixel of the enlarged image shown in FIG. Is calculated by performing an interpolation filter operation, that is, a convolution operation on an interpolation function, on the pixel data values of the original image.

Increase sampling frequency while maintaining pixel arrangement
That the image conversion processing will further with reference to FIG. 4, the original image shown in FIG. 1,
Sampling frequency without changing image size (10/7)
An image conversion process (sampling frequency conversion process) for increasing the sampling frequency will be described by taking the case of double conversion as an example.

FIG. 4 is a diagram showing a converted image obtained by converting the original image shown in FIG. 1 to a sampling frequency (10/7) times without changing the size of the image. In this sampling frequency conversion process, the original image is converted to a resolution standard (10 /
7) This is equivalent to converting the image into an image of the image transmission method that is twice as high. That is, as shown in FIG. 4, by this sampling frequency conversion process, the original image shown in FIG. 1 has the number of pixels of [10/7 (= 1.429 times)] and the same area within the same length. The image is converted into a converted image (with a surface density of 1.429 ² times) containing 1.429 ² times the number of pixels.

The positional relationship between each pixel of the original image (FIG. 1) and each pixel of the enlarged image (FIG. 2), and the relationship between each pixel of the original image and each pixel of the image after sample frequency conversion (FIG. 4). Since the positional relationship is the same, and both are as shown in FIG. 3, the calculation for increasing the sampling frequency and the areal density of pixels is the same as the above-described calculation for the enlargement processing on the original image.

For an image whose length is reduced while maintaining the pixel arrangement,
With reference to FIGS. 5 and 6, the original image shown in FIG. 1 is replaced with the pixel arrangement shown in FIG. 1 (pixel spacing and positional relationship) without changing the image display standard itself. The image reduction processing will be described by taking as an example the case where the length is reduced at a reduction ratio of (10/13) times while maintaining the same. When the image is reduced in this way, the pixel intervals and the positional relationship in the image (reduced image) obtained by the reduction process are the same as the original image shown in FIG.

FIG. 5 is a view showing a reduced image obtained by reducing the length of the original image shown in FIG. 1 to (10/13) times without changing the arrangement of pixels. In this reduction processing, since the reduction magnification is 0.769 (= 10/13) times, the length of one side of the image is 0.769 times, and the number of pixels constituting the reduced screen is about 0.769 ² times. To decrease.

For example, as shown in FIG. 1, when the number of pixels in the horizontal direction of the original image is 8, the number of pixels in the horizontal direction of the reduced image is 6 or 7 [≒ 8 × 10/13 (6 .15
4)]. Therefore, the positional relationship between the pixels of the original image and
The positional relationship between the pixels of the reduced image changes, and the pixel data of the reduced image has a different value from the corresponding pixel data of the original image.

FIG. 6 shows the pixels of the original image shown in FIG. 1 when the image projected on the screen is fixed, and the reduced image obtained by reducing the length of the original image by a (10/13) times reduction magnification. FIG. 3 is a diagram illustrating a positional relationship between pixels and a horizontal direction. In FIG. 6, Ri (i = 1, 2,...) Above the horizontal axis indicates pixels of the original image, and Qi below the horizontal axis indicates pixels of the reduced image. Although FIG. 6 shows the positional relationship between the pixels of the original image and the pixels of the reduced image in the horizontal direction, the same applies to the positional relationship in the vertical direction.

As shown in FIG. 6, the pixel Ri of the original image is
The pixels are arranged at intervals of (10/13) times the pixel Qi of the reduced image. The value of the pixel data of the reduced image is calculated by performing an interpolation filter operation on the pixel data of a predetermined number of pixels around the corresponding pixel of the original image according to the correspondence relationship with each pixel of the original image shown in FIG. That is, it is calculated by performing a convolution operation of the interpolation function.

Lowering the sampling frequency while maintaining the pixel arrangement
That the image conversion processing will further with reference to FIG. 7, the original image shown in FIG. 1,
The sampling frequency is changed (10/1) without changing the size of the image.
3) The sampling frequency conversion processing for lowering the sampling frequency will be described by taking as an example the case where the conversion is performed twice.

FIG. 7 is a diagram showing a converted image obtained by converting the original image shown in FIG. 1 to a sampling frequency (10/13) times without changing the size of the image. In this sampling frequency conversion processing, the original image is converted to a resolution standard (10
/ 13) It is equivalent to converting the image into an image of the image transmission method which is lower by a factor of two. That is, as shown in FIG. 7, by this sampling frequency conversion process, the original image shown in FIG. 1 has the number of pixels of [10/13 (≒ 0.769 times)] and the same area within the same length. Including 0.769 ² times the number of pixels (1.429 ²
Is converted to a converted image (of double area density).

The positional relationship between each pixel of the original image (FIG. 1) and each pixel of the reduced image (FIG. 5), and the position of each pixel of the original image and each pixel of the image after the sampling frequency conversion (FIG. 7) Since the relationship is the same and both are as shown in FIG. 6, the calculation for lowering the sampling frequency and the surface density of pixels is the same as the calculation for the above-described reduction processing on the original image.

As described above, the enlargement / reduction processing of the image and the sampling frequency conversion processing require filtering by an interpolation filter for calculating pixel data of a new pixel at a position where no pixel exists in the original image. It is.

Calculation of Interpolation Filter Hereinafter, calculation used for filtering by the interpolation filter will be described. FIG. 8 is a diagram illustrating filtering by an interpolation filter. As shown in FIG. 8, the sampling interval of the original image is S, and a position (distance P) from the position of the pixel R of the original image is determined by the position of the pixel (interpolated pixel) Qi generated by interpolation (interpolation). ), The interpolation pixel Qi
Is calculated by performing a convolution operation on a value R of a pixel in the vicinity of the original image (hereinafter, referred to as a peripheral pixel).

FIGS. 9A to 9D are diagrams showing an interpolation function used for a filtering operation by an interpolation filter. Ideal "interpolation" based on "sampling theorem"
The calculation processing of the pixel data of the interpolated pixel by the following formula is performed by using the sinc function shown in the following expression 1 and FIG. This is performed by a convolution operation up to the pixel data of the pixel.

[0047]

F (x) = sinc (π × x) = sin (π × x) / (π × x) (1) where π is a circular constant.

However, in practice, it is necessary to calculate the pixel data of the interpolated pixel within a finite time. Therefore, the interpolation function obtained by approximating the sinc function shown in Equation 1 and FIG. Use. Methods for approximating the sinc function include the nearest neighbor approximation, bilinear approximation, and Cu
A bic approximation method and the like are known.

Among the above-described approximation methods, the nearest neighbor approximation method uses the interpolation function shown in the following equation 2 and FIG. Calculate pixel data for each minute.

[0050]

F (x) = 1; −0.5 <x ≦ 0.5 f (x) = 0; −0.5 ≧ x, x> 0.5 (2) 9 (B), the variable x is a horizontal displacement (P in FIG. 8) from the pixel position of the original image,
This is a quantity normalized by the sample interval S of the original image (the same applies to the following equations).

The bilinear approximation method is given by the following equation 3 and FIG.
The pixel data for one interpolation pixel is calculated from the pixel data for two pixels of the original image using the interpolation function shown in FIG.

[0052]

F (x) = 1− | x |; | x | ≦ 1 f (x) = 0; | x |> 1 (3)

The bilinear approximation is well known as linear interpolation, and calculates pixel data of an interpolated pixel by calculating a weighted average of pixel data on both sides of a pixel of an original image.

In the Cubic approximation method, data of one pixel of one interpolated pixel is obtained from pixel data in the vicinity of four pixels of the original image by using the following equation 4 and the interpolation function shown in FIG. calculate.

[0055]

F (x) = | x | ³ -2 | x | +1; | x | ≦ 1 f (x) = − | x | ³ +5 | x | ² + 4-8 | x |; 1 <| x | ≦ 2 f (x) = 0; 2 <| x | (4)

These convolution operations are performed by a so-called FIR
This can be performed using a digital filter. When the interpolation point (the position of the interpolation pixel) is set at the center of the interpolation function, the value of the coefficient (filter coefficient) set for each multiplication element of the FIR digital filter that realizes this convolution operation is calculated around the center. The value of the interpolation function at a predetermined number (nearby) of pixel positions (sample points) of the original image is used. Note that a combination of filter coefficients set for each multiplication element of the FIR digital filter is called a filter coefficient set.

Filter Coefficient Set The filter coefficient set of the FIR digital filter for realizing the convolution operation will be further described with a specific example.

In the case of performing interpolation processing by the bilinear approximation method,
Filter coefficient set, for example, FI used for interpolation processing by the bilinear approximation method
The R digital filter employs a two-tap configuration. When the value of the position difference (phase P shown in FIG. 8) between the pixel of the original image and the interpolation pixel normalized by the sampling interval S of the original image is 0.0. , The two filter coefficients set in this FIR digital filter are 1.0 and 0.0. In other words, these two
When the position of the pixel of the original image and the position of the interpolation pixel match (phase P = 0), the FIR digital filter outputs the pixel data of the original image as it is as the pixel data of the interpolation pixel. Construct a coefficient set.

For example, when the phase P is 0.5, the two filter coefficients set in the FIR digital filter are 0.5 and 0.5. For example, when the phase P is 0.3, the two filter coefficients set in the FIR digital filter are 0.7 and 0.3.

When performing interpolation processing by the Cubic approximation method
The FIR digital filter used for the interpolation processing by the filter coefficient set Cubic approximation method has a 4-tap configuration, and has a phase P of 0.
When 0, the four filter coefficients set in the FIR digital filter are 0.0, 1.0, 0.0,
0.0, and these four filter coefficients constitute a filter coefficient set for outputting the pixel data of the pixel of the original image whose position coincides with the interpolation pixel as the pixel data of the interpolation pixel.

When the phase P is 0.5, F
The four filter coefficients set in the IR digital filter are -0.125, 0.625, 0.625, -0.
125. When the phase P is 0.3,
The four filter coefficients set in the FIR digital filter are -0.063, 0.847, 0.363,-
0.147.

Since the phase P changes for each interpolation pixel, it is necessary to prepare a filter coefficient set having a different value for each phase, and to perform interpolation processing using a filter coefficient set having a value corresponding to the phase of each interpolation pixel. There is.

Interpolation Filter Arithmetic Apparatus Hereinafter, an interpolation filter arithmetic unit for performing a convolution operation of an interpolation function on pixel data of an original image will be described. FIG.
Is an interpolation function using the Cubic approximation method [FIG.
(D) performs a convolution operation to interpolate the pixel data of the original image to generate pixel data of the interpolated image.
FIG. 2 is a diagram illustrating a configuration of an arithmetic device 1 that operates as an R digital filter.

As shown in FIG. 10, the arithmetic unit 1 includes a coefficient memory 100, registers 102 _{1 to} 102 ₄ , a multiplier 1
04 _1-104 comprised of ₄ and the adder 106.
Using these components, the arithmetic unit 1 uses a four-stage shift register to set two pixel data of the original image, two in the horizontal direction and two in the horizontal direction across the position of the interpolation pixel (interpolation point). The pixel data of the interpolated pixel is calculated by performing a convolution operation using an interpolation function (FIG. 9D) using the Cubic approximation method.

The components of the arithmetic unit 1 will be described below.

Coefficient Memory 100 The coefficient memory 100 stores a plurality of filter coefficient sets respectively corresponding to the interpolation points [phase P (FIG. 8)], and stores externally connected image equipment such as a VTR and editing equipment. A stored filter coefficient set is read from an image processing device (not shown; hereinafter, collectively referred to as an image processing device) in accordance with a filter selection signal synchronized with an input original image, and the read filter coefficient set is configured. The four filter coefficients FC1 to FC4 are multiplied by multipliers 104 _{1 to} 104
₄ Set each.

[0067] Register 102 _{1-102 4} registers 102 ₁ to 102 ₄ is connected in series to form a shift register of the four-stage structure, obtained the original image by the horizontal scanning, in words from an external image processing device Four consecutive pixel data of the image data sequentially input in time series are held in accordance with the logical value of the control signal. For example, a clock signal CLK synchronized with the pixel data of the original image has a logical value of 0
The shift is performed at the timing of rising from (L) to logical value 1 (H).

That is, each of the registers 102 _{1 to} 102 ₄ is connected to an external image processing device and the preceding registers 102 ₁ to 102 ₄ at the rising edge of the clock signal CLK only when the control signal has a logical value of 1 (H), for example. the pixel data of the original image input from 102 ₃ to hold the latch,
Perform a shift operation. On the other hand, registers 102 _{1 to} 102 ₄
Does not perform the shift operation even at the rising point of the clock signal CLK when the control signal has the logical value 0 (L).

[0069] Multiplier 104 ₁ to 1 04 ₄ multiplier 104 _{i (i} = 1~4) is the original image of the pixel data input from the register 102 _i, the coefficient memory 100
Is multiplied by the filter coefficient FCi input from the input unit 106, and the multiplication result is output to the adder 106.

The adder 106 calculates the sum of the multiplication results input from the multipliers 104 _{1 to} 104 _4, and outputs the result as pixel data (interpolated value) of the interpolated pixel.

The operation coefficient memory 100 of the arithmetic unit 1 stores the filter coefficients FC of a plurality of filter coefficient sets corresponding to the interpolation points [phase P (FIG. 8)] in accordance with the filter selection signal synchronized with the input original image.
1 to FC4 are set for each of the multipliers 104 _{1 to} 104 ₄ . The registers 102 _{1 to} 102 ₄ shift four consecutive pixel data in synchronization with the clock signal CLK in accordance with the logical value of the control signal, and transmit the held pixel data to the multipliers 104 _{1 to} 104 ₄ . Supply.

The multipliers 104 _{1 to} 104 ₄ output consecutive 4
Pixel data of two original images and filter coefficients FC1 to FC
Multiply by 4. The adder 106 includes multipliers 104 ₁ to 104 ₁
Calculating the 04 ₄ multiplication result sum, and outputs the calculated pixel data of the interpolation pixel.

As described above, the arithmetic unit 1 multiplies the pixel data of the original image and the filter coefficients input in time series to the arithmetic unit 1 by the multipliers 104 _{1 to} 104 ₄ and the adder 106. The filtering is performed, and the calculation result is output in time series as pixel data of the interpolation pixel.

A specific example of the operation of the arithmetic unit 1 The operation of the arithmetic unit 1 will be described below with a specific example.

Enlarging the original image length to (10/7) times
Processing Hereinafter, the operation of the arithmetic unit 1 (FIG. 10) will be described by taking as an example a case where the original image is enlarged by (10/7) times by Cubic approximation. In the enlargement process for increasing the length of the original image by (10/7) in the horizontal direction, the positional relationship between the interpolation pixel (interpolation point) and the pixel of the original image is set as described above with reference to FIG. hand,
This is realized by performing an interpolation filter operation.

FIG. 11 shows that the length of the original image is changed in the horizontal direction (1
Arithmetic unit 1 (FIG. 10) for performing an enlargement process of 0/7) times
5 is a table illustrating the data values of the respective components in each processing cycle (cycle). Actually, in the arithmetic unit 1 that performs image processing by hardware, the multiplier 1
04 _{1 to} 104 ₄ and the adder 106 perform multiplication and sum calculation by pipeline processing, which causes a delay (latency) for realizing a high-speed operation. For convenience of illustration and description, FIG. 1 shows a case where latency does not occur.

The arithmetic unit 1 sets the cycle in which the pixel data of the original image is input for one pixel as the processing cycle (cycle) for outputting the enlarged image for one pixel. The following filtering operation is performed. In addition,
Actually, the input cycle of the pixel data of the original image for one pixel is slightly shorter than the processing cycle (cycle).

First Cycle (FIG. 11) As shown in FIG. 11, in the first cycle, the value of the control signal takes a logical value of 1 (H), and the register 102 ₁ contains an external image processing device. From the first pixel data R1 of the original image. At the start of the first cycle, the registers 102 _{1 to} 102 ₄ store pixel data R1
The pixel data Rm0 to Rm3 of the original image input to the register 102 _{1 one} to four cycles before are held, and a shift operation is performed at the timing when the clock signal CLK rises after the start of the first cycle, and a new pixel Data R
1, Rm0 to Rm2 are held.

Second Cycle (FIG. 11) In the second cycle, the value of the control signal is a logical 1
(H), the register 102 ₁ receives the second pixel data R2 of the original image from an external image processing device.
At the start of the second cycle, the registers 102 ₁ to 102 ₁
Each 02 _4, pixel data R1, holds Rm0～Rm2, performs a shift operation at the timing when the clock signal CLK rises after the start of the second cycle, the newly holds the pixel data R2, R1, Rm0, Rm1 I do.

Third Cycle (FIG. 11) In the third cycle, the value of the control signal is a logical 1
(H), the third pixel data R3 of the original image is input to the register 102 ₁ from an external image processing device.
At the start of the third cycle, the registers 102 ₁ to 102 ₁
02 each ₄ pixel data R2, R1, Rm0, R
The shift operation is performed at the timing when the clock signal CLK rises after the start of the third cycle, and the pixel data R3, R2, R1, and Rm0 are newly held.

Fourth Cycle (FIG. 11) In the fourth cycle, the pixel data R of the next original image
4 is input to the register 102 ₁ . However, as described later, in the fourth cycle, the interpolation pixel data (Q
Since the pixel data of the original image used for generating 1) is used for generating the interpolated pixel data (Q2) in the fifth cycle as it is, the external image processing device (control device) controls the value of the control signal. Is changed to a logical value 0 (L), and the registers 102 _{1 to} 102 ₄ perform the third operation without performing the shift operation.
The same pixel data R3, R2, Rm0, Rm as the cycle of
Hold 1 Further, an externally connected image processing device (control device) controls the positional relationship between the pixels of the original image and the interpolated pixels (FIG. 3), that is, the pixels Ra and R of the original image shown in FIG.
The filter selection signal P0 corresponding to the phase P (FIG. 8) when b, Rc, Rd and the interpolated pixel Q are pixel data Rm0, R1 to R3 and interpolated pixel data Q1 shown in FIG. Output to

FIG. 12 is a table showing ten types of filter coefficient sets stored in the coefficient memory 100 of the arithmetic unit 1 shown in FIG. Note that FIG. 12 illustrates one example that may occur when performing an enlargement process to increase the length of the original image by (10/7) times.
By substituting 0 types of phases P (FIG. 3) into a variable x as a variable x,
The data length is limited to 8 bits (maximum amplitude 128), and the values of the filter coefficients represented by decimal points and represented by 8 bits are shown.

Enlargement processing of original image length to (10/7) times
In this case, as shown in FIG.
The positional relationship between the pixel and the interpolated pixel (phase P; FIG. 8) occurs
You. Therefore, the coefficient memory 100 stores the position relation shown in FIG.
10 kinds of filter coefficient sets corresponding to each member
(FIG. 12) is stored in advance, and each cycle after the fourth cycle is stored.
Filter selection signal Pk (k = 0)
To 9) based on the stored 10 filter coefficient sets.
Select one of the filters and the selected filter coefficient set
Is multiplied by four filter coefficients FC1 to FC4
Vessel 104₁~ 104 _FourSet for each.

That is, an external image processing device (control device)
Is obtained by dividing the sampling interval S (FIG. 8) into ten by dividing the positions of the pixels of the original image and the positions of the interpolation pixels (interpolation points).
When there is a relationship of the k-th phase P among the phases,
A filter selection signal Pk corresponding to the k-th phase P is output to the coefficient memory 100.
A filter coefficient set is selected according to a filter selection signal Pk input from an image processing device (control device), and filter coefficients FC1 to FC1 included in the selected filter coefficient set are selected.
FC4 is set for each of the multipliers 104 _{1 to} 104 ₄ .

In the fourth cycle, as illustrated in FIG. 11, the position of the pixel of the original image and the interpolation pixel (interpolation point)
Is in the relationship of the 0th phase P, and the external image processing device (control device) outputs the filter selection signal P0 to the coefficient memory 100. Coefficient memory 100
Is a filter coefficient set [0.0, 1.0, 0.0, 0.0] corresponding to the phase P0 shown in FIG. 12 according to the filter selection signal P0 input from an external image processing device.
(0, 128, 0, 0 in 8-bit representation)] and the four filter coefficients FC1 to FC4 (0.0, 1.0, 0.0, 0.0) constituting the selected filter coefficient set
Is output to each of the multipliers 104 _{1 to} 104 ₄ .

The multipliers 104 _{1 to} 104 ₄ multiply the pixel data of the original image input from the registers 102 _{1 to} 102 ₄ by the filter coefficients FC 1 to FC 4 input from the coefficient memory 100, respectively. Calculates the sum of the four multiplication results input from the multipliers 104 _{1 to} 104 ₄ . Thus, the multipliers 104 _{1 to} 104 ₄
The adder 106 performs the product-sum operation described above, and outputs the result of the product-sum operation as interpolated pixel data Q1.

Fifth cycle (FIG. 11) At the start of the fifth cycle, the registers 102 ₁ to 102 ₁
Each 02 ₄ holds the fourth pixel data R3, R2, R1, Rm0 held in cycle, the register 102 _1, the external image processing device (control device)
Thus, the fourth pixel data R4 of the same original image as in the fourth cycle is input.

In the fifth cycle, the pixel R
The value of the phase P of the interpolation pixel Q2 with respect to the position 1 is (7/1)
0), the external image processing device (control device)
For the coefficient memory 100, the seventh phase P (7/1
0) is output. The coefficient memory 100 stores a filter coefficient set corresponding to the filter selection signal P7 (FIG. 12; -0.147, 0.36).
3,0.847, -0.063 (-1 in 8-bit representation)
9, 46, 108, -8)] four filter coefficients FC
1 to FC4 are output to multipliers 104 _{1 to} 104 ₄ . Multipliers 104 _{1 to} 104 ₄ and adder 106
Performs the product-sum operation in the same manner as in the fourth cycle, and outputs the result of the product-sum operation as interpolated pixel data Q2.

As will be described later, in the sixth cycle, the next interpolated pixel data Q3 is calculated from the pixel data R4 to R1, so that in the fifth cycle, an external image processing device (control device) is used. Sets the value of the control signal to the logical value 1 (H) as shown in FIG.
Output to 2 _{1 to} 102 ₄ to enable shift operation. The registers 102 _{1 to} 102 ₄ perform the shift operation at the timing when the clock signal CLK rises after the product-sum operation processing by the multipliers 104 _{1 to} 104 ₄ and the adder 106 is completed according to the value of the input control signal. Do
The pixel data R4 to R1 are newly held.

Sixth cycle (FIG. 11) At the start of the sixth cycle, the registers 102 ₁ to 102 ₁
02 ₄ are respectively hold the pixel data R4～R1, the register 102 _1, pixel data R5 of the fifth is input from an external image processing device (control device). Also,
In the seventh cycle, since the interpolated pixel data Q4 is generated from the pixel data R5 to R2 of the original image as shown in FIG. 11, the external image processing device (control device) sets the value of the control signal to a logical value. 1 (H) as registers 102 ₁ to 102 ₁
And output to the 02 _4, to allow a shift operation.

The value of the phase P in the sixth cycle is originally the value of the phase P in the fifth cycle (7/1
0) and (7/10) further added (14/1
0). However, since the external image processing device delayed the phase of the pixel of the original image by one pixel data (10/10) in the fourth to fifth cycles, the sixth
Becomes the value (4/10) obtained by subtracting (10/10) from (14/10).

More specifically, if the phase relationship between the pixels of the original image and the interpolated pixels is as shown in FIG. 3, the phase P in the m-th cycle (m = 4, 5,...) Is [{mod (10,7 (m-4))} / 1
0]. That is, in the m-th cycle, the external image processing device (control device) converts the filter selection signal Pk corresponding to the phase P of a value obtained by dividing the result of the modulo 10 operation of 7 (m−4) by 1/10 by the coefficient This is set for the memory 100.

Therefore, an external image processing device (control device)
In the sixth cycle, the value of the phase P (4/1
0) is stored in the coefficient memory 10
Output for 0. The coefficient memory 100 stores a filter coefficient set corresponding to the filter selection signal P4 [FIG.
0.096, 0.744, 0.496, -0.144
(8-bit representation: -12, 95, 63, -18)]
One of the filter coefficients FC1～FC4, multipliers 104 ₁ to
Output to each of 104 ₄ . Multipliers 104 ₁ to
104 ₄ and the adder 106, the fourth, by performing product-sum operation in the same way as in the fifth cycle, and outputs the result of multiply-add operation as the interpolation pixel data Q3.

The registers 102 _{1 to} 102 ₄ operate at the timing when the clock signal CLK rises after the product-sum operation by the multipliers 104 _{1 to} 104 ₄ and the adder 106 is completed in accordance with the value of the input control signal. A shift operation is performed to newly hold pixel data R5 to R2.

Similarly, in each cycle k (7 ≧ k), the arithmetic unit 1 performs the processing as shown in FIG. 11 and converts the pixel data of the original image into the output data [interpolated pixel data Q (k−3). )] Is sequentially calculated and output to the outside.

As described above, the arithmetic unit 1 (FIG. 1)
0) can perform filtering on the original image and perform enlargement processing. That is, the arithmetic unit 1 can perform enlargement / reduction of the original image and conversion of the resolution using hardware, in other words, using an electronic circuit provided corresponding to each arithmetic processing. However,
Enlarge / reduce the original image using the arithmetic unit 1 (pixel number conversion)
When the processing is performed, the data rate of the original image input from the external image processing device and the data rate of the enlarged image output by the arithmetic device 1 fluctuate due to a change in the number of pixels.

That is, for example, as described above, when performing a conversion process of enlarging an original image and increasing the number of pixels using the arithmetic unit 1, the average value of the data rate of the enlarged image output by the arithmetic unit 1 Will inevitably be faster.

On the other hand, when the conversion processing for reducing the number of pixels by reducing the original image using the arithmetic unit 1 is performed, the data rate of the reduced image output by the arithmetic unit 1 becomes low. Therefore, in practice, the arithmetic unit 1 provides buffer memories on the input side and the output side, buffers the input image data of the original image and the image data of the enlarged / reduced image, and keeps the data rate constant. Configured to keep.

Further, using the arithmetic unit 1 to enlarge / enlarge the original image
When performing reduction processing or the like, it is desirable to perform various image processing, television signal processing, noise removal processing, and the like in parallel. However, the arithmetic unit 1 only performs enlargement / reduction processing and resolution conversion processing using dedicated hardware, and cannot perform noise removal processing or the like. Therefore, in order to perform these processes and other processes in parallel, it is necessary to separately use a plurality of devices each performing a noise removal process and the like in addition to the arithmetic unit 1, so that the scale of the entire processing device is reduced. It gets bigger.

SIMD parallel processor To address such a problem, for example, SIM
D (Single Instruction Stream Multiple Data strea
m) There is a method in which the enlargement / reduction processing of the original image and the noise removal processing are performed in parallel by software using a control type parallel processor.

Configuration of SIMD Parallel Processor 2 Hereinafter, the configuration of the parallel processor 2 will be described. FIG.
FIG. 2 is a diagram illustrating a configuration of a parallel processor 2 that performs image processing by software. As shown in FIG. 13, the parallel processor 2 includes an input pointer 21, an input SAM (serial access memory) unit 22, a data memory unit 23, and an ALU.
It comprises an array unit 24, an output SAM unit 25, an output pointer 26, and a program control unit 27.

Of these components, the input SAM unit 2
2. The data memory unit 23 and the output SAM unit 25 mainly include a memory. Input SAM unit 22, data memory unit 23, ALU array unit 24, and output SAM unit 2
Reference numeral 5 designates a plurality (more than the number of pixels H for one horizontal scanning period of the original image) of the element processors 30 parallelized in a linear array format. Each of the element processors 30 (single element) has an independent processor component, and corresponds to a hatched portion in FIG. In addition, the plurality of element processors 30 correspond to FIG.
3 and arranged in parallel in the horizontal direction to form an element processor group.

The components of the parallel processor 2 The components of the parallel processor 2 will be described below.

Program control unit 27 The program control unit 27 comprises a program memory, a sequence control circuit for controlling the progress of a program stored in the program memory, and an input SAM unit 22, a data memory unit 23, and an output SAM unit 25. It is composed of “ROW” address code data (both not shown) for the memory to be used.

The program control unit 27 stores a single program by these components and generates various control signals based on the stored single program for each horizontal scanning period of the original image. By processing all the element processors 30 in conjunction with each other via various control signals, processing for image data is performed. Controlling a plurality of element processors based on a single program in this manner is referred to as SIMD control.

Input Pointer 21 The input pointer 21 is a 1-bit shift register.
Each time pixel data for one pixel of the original image is input from an external image processing device (not shown), the logical value of 1 (H) is set to 1
By shifting the bit signal [input pointer signal (SIP)], the element processor 30 in charge of the input pixel data of one pixel is designated, and the input SAM unit 22 (input SAM cell) of the designated element processor 30 is designated. Then, the pixel data of the corresponding original image is written.

That is, the input pointer 21 is set to 1
For each horizontal scanning period, first, an input pointer signal to the leftmost element processor 30 in FIG.
The pixel data of the first original image input in response to the clock signal synchronized with the pixel data is input to the input SAM unit 2 of the leftmost element processor 30 of the parallel processor 2 shown in FIG.
2, and thereafter, every time the clock signal changes by one period, the input pointer signal of the logical value 1 to the element processor 30 on the right is sequentially shifted to the right,
The image data of the original image is written into the input SAM unit 22 of each of the element processors 30 by one pixel.

[0108] The processor elements 30 processor elements 30, respectively, a 1-bit processor, for each pixel data of the original image input from an external image processing device, performs a logical operation and an arithmetic operation processing, the processor elements 30 As a whole, horizontal and vertical filtering processes and the like by the FIR digital filter are realized. Since the SIMD control by the program control unit 27 is performed with the horizontal scanning period as a cycle, each element processor 30 determines the maximum number of steps obtained by dividing the horizontal scanning period by the cycle of the instruction cycle of the element processor 30. The program may be executed for each horizontal scanning period.

The element processor 30 is connected to the adjacent element processor 30 and has a function of performing inter-processor communication with the adjacent element processor 30 as necessary. That is, each of the element processors 30
According to the SIMD control of the program control unit 27, for example, the data memory unit 23 or the like of the element processor 30 on the right or the left can be accessed to perform processing. By repeating, the element processor 30 can access the data memory unit 23 of the element processor 30 that is not directly connected and read data. The element processor 30 utilizes a communication function between adjacent processors,
A horizontal filtering process is realized as a whole.

Here, for example, when arithmetic processing between pixel data separated by about 10 pixels in the horizontal direction is required, the number of program steps becomes extremely large when communication between processors is performed. The FIR filter processing hardly includes arithmetic processing between pixel data separated by as much as 10 pixels, and mostly includes arithmetic processing on continuous pixel data. Therefore, it is very unlikely that the number of program steps of the FIR filter processing for performing inter-processor communication increases and becomes inefficient.

Each of the element processors 30 always processes the pixel data at the same position in the horizontal scanning direction exclusively. Therefore, the write address of the data memory unit 23 to which the pixel data (input data) of the original image is transferred from the input SAM unit 22 is changed at each initial stage of the horizontal scanning period, and the input data of the past horizontal scanning period is held. Thus, the element processor 30 can also filter the pixel data of the original image in the vertical direction.

Input SAM unit 22 In each of the element processors 30, the input SAM unit 2
Reference numeral 2 denotes pixel data of one pixel (input data) input to the input terminal DIN from an external image processing device when the input pointer signal input from the input pointer 21 becomes a logical value 1 as described above. Is stored. That is, the input SAM unit 22 of the element processor 30 stores pixel data for one horizontal scanning period of the original image as a whole for each horizontal scanning period. Further, the input SAM unit 22 stores pixel data (input data) of the stored original image for one horizontal scanning period.
Is transferred to the data memory unit 23 as needed in the next horizontal scanning period under the control of the program control unit 27.

Data memory unit 23 The data memory unit 23 stores pixel data of the original image, data in the middle of calculation, constant data, and the like input from the input SAM unit 22 under the control of the program control unit 27. Output to the array unit 24.

ALU Array Unit 24 The ALU array unit 24 performs arithmetic operations on pixel data of an original image, data in the middle of calculation, constant data, and the like input from the data memory unit 23 under the control of the program control unit 27. Processing and logical operation processing are performed and stored at a predetermined address in the data memory unit 23. Note that A
The LU array unit 24 performs all arithmetic processing on the pixel data of the original image on a bit-by-bit basis, and performs arithmetic processing on one-bit data every cycle.

The processing time of the ALU array unit 24 will be described with a specific example. For example, when the ALU array unit 24 performs a logical operation process on two pixel data having an 8-bit configuration, a processing time of at least 8 cycles is required. When performing an addition process on two pixel data having an 8-bit configuration, At least nine cycles of processing time are required. Further, when the ALU array unit 24 performs a multiplication process on two pixel data of an 8-bit configuration, this multiplication process is equivalent to addition of 64 bits.
Cycle processing time is required.

Output SAM unit 25 The output SAM unit 25 receives the transfer of the processing result from the data memory unit 23 under the control of the program control unit 27 when the processing assigned to one horizontal scanning period is completed, and In the next horizontal scanning period, the signal is output via the output SAM unit 25.

Processing Format of Element Processor 30 The input processing (first processing) of writing the pixel data (input data) of the original image into the input SAM unit 22 in each of the element processors 30 and the input processing under the control of the program control unit 27 Transfer processing of input data stored in the SAM unit 22 to the data memory unit 23, ALU array unit 24
, The process of transferring the processing result (output data) to the output SAM unit 25 (second process), and the output SA
Output processing of output data from M section 25 (third processing)
Is executed in a pipeline format with a processing cycle of one horizontal scanning period.

Therefore, when focusing on the input data, each of the first to third processes for the same input data requires a processing time for one horizontal scanning period. Therefore, from the start to the end of these three processes, Processing time for three horizontal scanning periods is required. However, since these three processes are executed in parallel in a pipeline format, on average, processing of input data for one horizontal scanning period requires only a processing time for one horizontal scanning period.

Operation of Parallel Processor 2 The operation of the image processing linear array type parallel processor (parallel processor 2) shown in FIG. 13 will be described below. In the first horizontal scanning period (first horizontal scanning period), the input pointer 21 inputs the logical value 1 (H) to each element processor 30 in accordance with the clock synchronized with the input pixel data of the original image. The element processor 30 which sequentially shifts the signal and designates the element processor 30 which is in charge of each pixel data of the original image and performs arithmetic processing is designated.

The pixel data of the original image is input to the input SAM unit 22 via the input terminal DIN.
Stores pixel data for one pixel of the original image in each of the element processors 30 according to the logical value of the input pointer signal. When all the input SAM units 22 of the element processor 30 corresponding to the pixels included in one horizontal scanning period respectively store the pixel data of the original image and store the pixel data of one horizontal scanning period as a whole, the input processing ( (1st process) is complete | finished.

The program control unit 27 executes the input process (first
Is completed, the input SAM unit 22, the data memory unit 23, and the ALU array unit 2 of each of the element processors 30 according to a single program for each horizontal scanning period.
4 and the output SAM unit 25 are subjected to SIMD control to execute processing on pixel data of the original image.

That is, in the next horizontal scanning period (second horizontal scanning period), each of the input SAM units 22
The pixel data (input data) of the original image stored during the horizontal scanning period is transferred to the data memory unit 23.

In this data transfer processing, the program control unit 27 activates the input SAM read signal (SIR) [to a logical value 1 (H)] and sets a predetermined row (ROW) of the input SAM unit 22 to a predetermined row (ROW). Select and access data,
Further, the memory access signal (SWA) is activated,
The input SAM unit 2 writes the accessed data to a memory cell (described later) of a predetermined row of the data memory unit 23.
2 and the data memory unit 23.

Next, the program control unit 27 controls each element processor 30 based on the program, causes the data memory unit 23 to output data to the ALU array unit 24, and causes the ALU array unit 24 to perform arithmetic operation processing and A logical operation process is performed, and the processing result is written to a predetermined address of the data memory unit 23. When the arithmetic operation processing and the logical operation processing according to the program are completed, the program control unit 27 controls the data memory unit 23 to transfer the processing result to the output SAM unit 25 (the above is the second processing). Further, in the next horizontal scanning period (third horizontal scanning period), the output SAM unit 25 is controlled to output the processing result (output data) to the outside (third processing).

That is, the 1 stored in the input SAM unit 22
The input data for the horizontal scanning period is transferred to and stored in the data memory unit 23 as needed in the next horizontal scanning period, and is used for processing in the subsequent horizontal scanning period.

Second Embodiment Hereinafter, a second embodiment of the present invention will be described.

Problems of Parallel Processor 2 (FIG. 13) The parallel processor 2 (FIG. 1 ) described as the first embodiment
According to 3), a general FIR digital filter can be realized. However, enlargement / reduction processing of an image that requires interpolation processing or resolution conversion processing is performed by F
When using a type of IR digital filter, the input SA
Since the number of data stored in the M unit 22 is different from the number of data output from the output SAM unit 25,
Alternatively, in the output SAM unit 25, the pixel data (input data) Ri of the original image and the processing result (output data) Qi cannot be densely arranged. It should be noted that it is not possible to arrange them densely, for example, as described later with reference to FIG.
In the case of the enlargement processing, the input side is sparsely arranged like the pixel data Ri in the input SAM unit 22, and in the case of the reduction processing, the output side is sparsely arranged like the output data Q in the data memory unit 23. Or

That is, in the parallel processor 2, the positional relationship with the neighboring pixels in the horizontal direction required for the operation is different depending on the element processors 30, but all the element processors 30 are in accordance with the SIMD control of the program control unit 27. Since the same operation is performed, the address accessed by each of the element processors 30 cannot be individually set. Therefore, in the parallel processor 2, it is difficult to transfer data required for the interpolation processing between the plurality of element processors 30 by communication between the processors. The problems of the above-described parallel processor 2 will be further described with reference to specific examples. FIG. 14 shows a case where the length of the original image is enlarged (10/7) times by the parallel processor 2 (FIG. 13).
FIG. 3 is a diagram showing an array of data stored in an input SAM unit 22, a data memory unit 23, and an output SAM unit 25 of each of the element processors 30.

For example, when performing a filtering process using Cubic approximation, a convolution operation is necessary for pixel data (input data) of four consecutive original images as described above. Taking a specific example of an enlargement process for enlarging the length of the original image by (10/7) times, as shown in FIG. 14, the input data Ri is not densely arranged between the element processors 30. Of the input data R1 to R4 required when calculating the data Q3, the input data R1, R3, and R4 are processing results (output data)
With the element processor 30 for calculating Q3 as a base point, it is stored in each of the element processors 30 that are two on the left, one on the right, and three on the right.

On the other hand, of the input data R2 to R5 necessary for calculating the output data Q4, the input data R2, R4, R5
Are stored in the element processors 30 one to the left, two to the right, and three to the right starting from the element processor 30 that calculates the output data Q4.

The input data R2 to R5 required for calculating the output data Q5 are two points to the left of the element processor 30 starting from the element processor 30 for calculating the output data Q5.
The element processors 30 are stored next to each other, one to the left, one to the right, and two to the right.

FIG. 15 shows input data necessary for calculating each output data when performing the enlargement process of enlarging the length of the original image by (10/7) using the parallel processor 2 (FIG. 13). FIG. 6 is a diagram showing a stored data reference pattern between element processors 30. As shown in FIG. 15, the original image is converted to (10 /
7) When performing the enlargement processing twice, the element processor 30 storing the input data necessary for calculating each output data
The data reference relation between them is classified into five patterns.

As described above, in the parallel processor 2, the element processor 30 storing the input data Rk necessary for calculating the output data Q (k-3) and the output data Q (k-3) ) To calculate the element processor 30
Is not constant and changes for each output data Q (k−3).

Further, as described above, since the phase P (FIG. 8) differs for each pixel, it is necessary to set a different filter coefficient set for each element processor 30.

Object and Outline of the Second Embodiment The parallel processor described below as the second embodiment includes:
Parallel processor 2 shown as the first embodiment (FIG. 13)
It is made to solve the problem of.

The parallel processor shown as the second embodiment minimizes the number of patterns of the positional relationship between another element processor that stores image data to be processed by a predetermined element processor and the predetermined element processor. SIMD control by providing pixel data (input data) of the same original image to the element processors and outputting different filter coefficients to the element processors or calculating the filter coefficients in the element processors. Thus, the interpolation processing can be easily performed on the original image.

Configuration of Parallel Processor 3 Hereinafter, the configuration of the parallel processor 3 will be described. FIG.
Parallel processor 3 according to the present invention shown as a second embodiment
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 16, the same components as those of the parallel processor 2 shown in FIG. 13 among the components of the parallel processor 3 are denoted by the same reference numerals.

[0138] As shown in FIG.
Are an input pointer 21, an input SAM unit 22, a data memory unit 23, an ALU array unit 24, and an output SAM unit 2.
5. It is composed of a program control unit 27a and a memory 28. That is, the parallel processor 3 differs from the first embodiment in that the programs to be executed are different from each other. Among the components of the parallel processor 2 (FIG. 13), the program control unit 27 is replaced with the program control unit 27a, Sampling, input SAM unit 22, data memory unit 23, ALU
The array unit 24 and the output SAM unit 25 include, as in the parallel processor 2, a plurality of element processors that are equal to or more than the number of pixels in one horizontal scanning period of the original image (input data) and the image (output data) obtained as a processing result. 30.

The components of the parallel processor 3 The components of the parallel processor 3 will be described below.

Input Pointer 21 The input pointer 21 is a 1-bit shift register.
As in the parallel processor 2, the element processor 3
The input SAM 22 is controlled by selectively outputting an input pointer signal (SIP) for each of the 0s, thereby reading pixel data (input data) of an original image input from an external image processing device.

Input SAM Unit 22 The input SAM unit 22 is mainly a memory provided for each of the element processors 30 (an input buffer memory 302 described later with reference to FIG. 17), as in the parallel processor 2. And stores the pixel data (input data) of the original image input to each of the element processors 30 according to the logical value of the input pointer signal (SIP) input from the input pointer 21. The input SAM unit 22 outputs the stored input data to the data memory unit 23 when the transfer control signal SIR input from the program control unit 27a is activated.

Data memory unit 23 The data memory unit 23 mainly includes a memory (data memory 304 described later with reference to FIG. 17) provided corresponding to each of the element processors 30 as in the parallel processor 2. When the memory write access signal (SWA) input from the program control unit 27a to each of the element processors 30 is activated, data input from the input SAM unit 22 or the ALU array unit 24 is stored. When the memory read access signal (SRAA, SRBA) input from the program control unit 27a is activated, the data memory unit 23 outputs the stored data to the ALU array unit 24.

ALU Array Unit 24 The ALU array unit 24 includes an ALU [arithmetic unit (Arith
metic and Logical Unit) 306] and the like, and the ALU control signal (SALU-
In accordance with control via CONT, logical operation processing and arithmetic operation processing are performed in bit units.

Output SAM Unit 25 The output SAM unit 25 is mainly composed of a memory (output buffer memory 308 described later with reference to FIG. 17) provided for each of the element processors 30, and the program control unit 27a When the output SAM write signal (SOW) input to each of the element processors 30 is activated, the processing result (output data) input from the ALU array unit 24 is stored. The output SAM unit 25
When the output pointer signal (SOP) input from the output pointer 26 to each of the element processors 30 is activated, the stored data is output to the outside.

Output Pointer 26 The output pointer 26 is a 1-bit shift register.
The output pointer signal (SOP) is selectively activated and output to the output SAM unit 25 of each of the element processors 30, and the output of the processing result (output data) is controlled.

Program control unit 27a The program control unit 27a executes a program different from that of the first embodiment, and, like the program control unit 27 of the parallel processor 2, sends various control signals based on a single program stored in advance. Activate or deactivate to control the element processor 30 by SIMD.

[0147] Memory 28 memory 28 (storage means), startup, is input from the horizontal blanking period, an external control CPU in such a vertical blanking period (not shown) or the like, the filter operation in all the processor elements 30 Are held in the order of the numbers of the element processors 30. In the parallel processor 3, the filter coefficient set stored in the memory 28 is set at the time of activation, during the horizontal retrace period or the vertical retrace period.
The data is output to the data memory unit 23 of each element processor 30.

Detailed Description of Element Processor 30 The element processor 30 of the parallel processor 3 (FIG. 16) will be described in further detail with reference to FIGS. 17 and 18.

FIG. 17 is a diagram exemplifying the configuration of element processor 30 of parallel processor 3 shown in FIG. As shown in FIG. 17, the element processor 30 of the parallel processor 3 is a 1-bit processor, and has an input buffer memory (IQ) 302, a data memory (RF) 304, an operation unit (ALU) 306, and an output buffer memory (OQ).
308. Input SAM unit 22, data memory unit 23, ALU array unit 24, and output SAM unit 25
(FIG. 16) Each corresponds to the input buffer memory 302, the data memory 304, the arithmetic unit 306, and the output buffer memory 308 (FIG. 17), and constitutes one element processor 30.

That is, in the element processor 30,
Input SAM unit 22, data memory unit 23 and output SA
The M unit 25 forms a “column” of the memory.

In each of the element processors 30, the input buffer memory 302 temporarily stores the pixel data (input data) of the original image and transfers it to the data memory 304.

The operation unit 306 is a full adder (full adder)
And a program control unit 27
According to the control of a, the input data newly transferred to the data memory 304, the data stored in the past, the data stored in the middle of the processing, and the like are subjected to various arithmetic processing in units of 1 bit, and the data is again processed. It is stored in the memory 304. Note that, for example, the arithmetic unit 306 is different from a general-purpose processor for a personal computer that performs arithmetic processing in word units, and performs arithmetic processing in 1-bit units similarly to the ALU array unit 24 of the parallel processor 2. Therefore, the element processor 30 is a so-called bit processor. By using the bit processor as the element processor 30, the hardware scale of each element processor 30 is reduced to increase the degree of parallelism. Can be many.

The output buffer memory 308 receives and stores the processing result (output data) transferred from the data memory 304 under the control of the program control unit 27a, and outputs it to the outside.

[0154] Specifically circuit diagram 18 of the element processor 30 is a diagram illustrating a specific detailed circuit configuration of the processor element 30 of the parallel processor 3 shown in FIG. 16. FIG. 18 shows a very general circuit in order to facilitate understanding of the configuration of the element processor 30. For convenience of illustration, when there are a plurality of identical circuits, only one circuit is shown. is there.

[0155] As shown in the input SAM cell 22 _i Figure 18, the input SAM unit 22 (FIG. 16) 1
[Input buffer memory 302 (FIG. 17)] corresponding to one element processor 30 includes transistors Tr1 and T
input SAM cell 22 _i including r2 and capacitor C1
And stores 1-bit pixel data of the original image.

In practice, one element processor 3
0 (input buffer memory 3)
02) is composed of _ISB input SAM cells 22 _{1 to} 22 _ISB corresponding to each bit (bit number ISB) of the pixel data (input data) of the original image.
, The input SAM cell 22 _i (1 ≦ i ≦ ISB)
Is shown only once.

In the input SAM cell 22 ₁ , the gate terminal of the transistor Tr1 is connected to the input pointer 21, and the other two terminals of the transistor Tr1 are
It is connected to the input data bus 208 and one end of a capacitor C1 for storing 1-bit data.

The input SAM read signal (SIR) is input to the gate terminal of the transistor Tr2 from the program control unit 27a, and the other two terminals of the transistor Tr2 are connected.
Each of the two terminals is connected to the write bit line 204 and one end of the capacitor C1. The capacitor C
1 is connected to transistors Tr1 and Tr2,
The other end is grounded.

The portion of the data memory unit 23 _i corresponding to one element processor 30 of the data memory unit 23 [data memory 304 (FIG. 17)] includes transistors Tr11 to Tr14, a capacitor C11, and a resistor R. Read bit lines 200, 202 and 1
Three with three ports of write bit lines 204
Data memory cell 23 _{i having} a port configuration (1 ≦ i ≦ MB)
Consists of In practice, the portion of the data memory unit 23 corresponding to one element processor 30 (data memory 304), MB number of data memory cells 23 ₁ corresponding to the bit number MB required as data memory
Has a 23 _MB, 18 are shown only one data memory cell 23 _i.

[0160] In the data memory cells 23 _i, to the gate terminal of the transistor Tr11, the program control unit 2
A memory access signal (SWA) is input from 7a, and the other two terminals of the transistor Tr11 are connected to the write bit line 204 and one end of a capacitor C11 for storing 1-bit data, respectively.

One end of the capacitor C11 is connected to the gate terminal of the transistor Tr12 and the transistor Tr11, and the other end is grounded. Two terminals other than the gate terminal of the transistor Tr12 are connected (grounded) to a negative power supply (ground), and are connected to a positive power supply (not shown) via a resistor R, respectively. The resistance R
Can be omitted.

The gate terminal of the transistor Tr13 has
The memory read access signal SRAA signal is input from the program control unit 27a, and the other two terminals of the transistor Tr13 are connected to the transistor Tr12 and the resistor R
And the read bit line 200 are connected to each other.
A memory read access signal SRBA is input to the gate terminal of the transistor Tr14 from the program control unit 27a, and the other two terminals of the transistor Tr14 are connected to the transistor Tr12, the resistor R, and the read bit line 202, respectively. .

ALU cell 24 _{i A} part of the ALU array unit 24 corresponding to one element processor 30 [arithmetic unit 306 (FIG. 17)] is the ALU circuit 2
30, flip-flops (FF) 232 ₁ to 23
2 _3, 238 and a selector (SEL) 234, 236
Composed of ALU cell 24 _i having _{1-236 3.}

In ALU cell 24 _i , ALU circuit 2
Reference numeral 30 denotes a 1-bit ALU configuration including a full adder circuit and the like, and flip-flops 232 _{1 to} 232
Logical operation processing and arithmetic operation processing are performed on the 1-bit data input from ₃ , and the operation processing result is output to the selector 234.

The portion of the output SAM cell 25 _i ALU array unit 24 corresponding to one element processor 30 [output buffer memory 308 (FIG. 17)]
An output SAM cell 25 _i (1 ≦ i ≦ OSB) having transistors Tr7 and Tr8 and a capacitor C4 and operating under the control of the output pointer 26.
The number of output SAM cells 25 _i is actually OSB corresponding to the number of bits (OSB) of the processing result (output data).
FIG. 18 shows only one (output SAM cell 25 _i ) of these output SAM cells 25 _{1 to} 25 _OSB for simplification of illustration.

In the output SAM cell 25 _i , the program control unit 27 is connected to the gate terminal of the transistor Tr 7.
The output SAM write signal SOW is input from a, and the other two terminals of the transistor Tr7 are connected to the write bit line 204a and one end of a capacitor C4 for storing 1-bit data, respectively. One end of the capacitor C4 is connected to the transistors Tr7 and Tr8, and the other end is grounded.

A gate terminal of the transistor Tr8 is connected to the output pointer 26, one of the other two terminals is connected to the capacitor C4 and the transistor Tr7, and the other is connected to the output data bus 210.

Word lines, signal lines, and data buses All word lines of the element processor 30 shown in FIG. 18 are also connected to other element processors 30, and are subjected to address decoding inside the program control unit 27a (FIG. 16). Input SAM read signal SIR, memory write line SWA, memory read access signals SRAA, S
RBA, output SAM write signal SOW, etc. are transmitted to all element processors 30. The input data bus 208 is connected to the input SAM cell 22 ₁ of all processor elements 30, output data bus 210 is connected to the output SAM cell 25 _i of all the processor elements 30.

Data transfer by element processor 30 and
Fine operation will be described transfer and processing operations of the data by the processor element 30 of the parallel processor 3.

When the input pointer 21 designates the input SAM cell 22 _i of the element processor 30, the designated input S
Transistor Tr1 of AM cell 22 _i is turned on, the terminal voltage of the capacitor C1, the input data bus 20
8 and a voltage corresponding to the pixel data (input data) of the original image input via the buffer 220. By this operation, the input SAM unit 22 (input buffer memory 30) of the element processor 30 designated by the input pointer 21
2) stores pixel data (input data) of the original image.

Next, the program control unit 27a receives the input S
Activate AM read signal SIR to input SAM cell 2
2 Select _i . The transistor Tr2 of the selected input SAM cell 22 _i is turned on, and the transfer data signal corresponding to the voltage of the capacitor C1 is written to the bit line 204.
Is caused. Further, the program control unit 27a activates the write bit line source switching signal SBC (logical value 1; H) to permit the output of the buffer 222, and further activates the memory access signal SWA (logical value 1;
H), the transistor Tr11 of the data memory cell 23 _i is turned on, and the terminal voltage of the capacitor C11 is set to a voltage corresponding to the data stored in the capacitor C1 of the input SAM cell 22 _i . When data is input from ALU cell 24 _i to data memory cell 23 _i , another write bit line source switching signal SBCA is output to buffer 224.

The data transfer from the input SAM cell 22 _i or the ALU cell 24 _i to the data memory cell 23 _i is performed one bit at a time in one cycle in accordance with the activation of the word line signal. Done through.

Next, ALU cell 24 _i is assigned to ALU cell 2
4 _i or input SAM cell 22 _i to data memory unit 2
3, the pixel unit (input data) of the original image stored therein, the data in the middle of the calculation, and / or the data stored in the flip-flops 232 _{1 to} 232 ₃ sequentially perform the bit-wise calculation processing. ,Run.

The first data in data memory cell 23 _i corresponding to a predetermined bit in data memory section 23 and the second data in data memory cell 23 _i corresponding to other bits are added, and As a specific example, a case where the addition result is written to the data memory cell 23 _i corresponding to the 3 bits
The operation of the ALU cell 24 _i will be further described.

The program control unit 27a operates the data memory cell 23 corresponding to a predetermined bit of the data memory unit 23.
Activate and output an access signal SRAA for the first read bit 200 of the data memory unit 23 for _i ,
With the transistor Tr13 turned on, the capacitor C
The first data stored in 11 is output to one read bit line 200. At the same time, the program control unit 27a sets the data memory cells 23 corresponding to the other bits.
_j (i ≠ j), the access signal SRBA signal for the first read bit 200 of the data memory unit 23 is activated and output, and the transistor Tr14 is turned on to store the access signal SRBA signal in the capacitor C11. 2 is output to the other read bit line 202.

The first data and the second data read from the capacitor C11 of the data memory cells 23 _i and 23 _j are supplied to the selectors 236 ₁ to 236 of the ALU cell 24 _i.
6 ₃ via the output against ALU230. ALU
The circuit 230 performs predetermined arithmetic processing on the first data and the second data input from the data memory cells 23 _i and 23 _{j under the} control of the program control unit 27a, and outputs the arithmetic processing result to the selector The data is output to the flip-flop 238 via the 234 and held.

[0177] Then, the program control unit 27a is a second write bit line source switching signal SBCA activated print to ALU cell 24 _i, the bit line write the operation result held in the flip-flop 238 204, and further activates a memory write bit line access signal SWA, and outputs a data memory cell corresponding to a predetermined third write address (usually a sum, but a MSB may use a carry). 23 _i
, The transistor Tr11 is turned on, and the terminal voltage of the capacitor C11 is set to a voltage corresponding to the result of the arithmetic processing.

[0178] The calculation processing operation in ALU cell 24 _i is by program control unit 27a, is controlled via the ALU control signal (SALU-CONT). Also,
Calculation result in the ALU cell 24 _i is written into the data memory section 23 as described above, or is stored in the flip-flop 232 ₃ of the ALU cell 24 _i as needed. When the arithmetic processing in the ALU 230 is addition, the ALU cell 24 _i outputs the carry obtained as a result of the addition processing to the flip-flop 232 _3.
And the addition result (sum) is stored in the data memory unit 23.

Next, when outputting data from the data memory cell 23 _i , the program control unit 27 a sends the memory access signal SRAA or the memory access signal SRBA to the data memory cell 23 _i storing the operation processing result. Is activated and output, and the transistor Tr1
3 or Tr14 is turned on, and the capacitor C11
Is output to the read bit line 200 or the read bit line 202.

[0180] Further, the program control unit 27a is a predetermined control signal (SALUCONT) and outputted to the ALU cell 24 _i, the output from the data memory cell 23 _i SA
To transfer data to M cells 25 _i, to activate the output SAM write signal SOW, specified output SAM cell 25
_i , the transistor Tr17 is turned on, the terminal voltage of the capacitor C4 is set to a voltage corresponding to the transferred data, and the data is held.

The data is written to the write bit line 204
Are transferred one bit at a time from the data memory cell 23 _i to the output SAM cell 25 _i . ALU circuit 2
The data processing unit 30 can also perform some kind of arithmetic processing on the data being transferred when transferring the data.

Next, the output pointer 26 is supplied to the leftmost element processor 30 (FIG. 1) by the output pointer signal SOP.
From the output of 6), to the output of the rightmost element processor 30, and sequentially activated in accordance with an output clock signal, the transistor Tr8 of the respective output SAM cell 25 _i is turned on, the processing result corresponding to the potential of the capacitor C4 (Output data) is output to the output terminal DOUT via the output data bus 210.

Since the number of the element processors 30 is equal to or more than the number of pixels H in one horizontal scanning period of the original image and the converted image, the output control by the output pointer 26 described above causes the respective element processors 30 of the parallel processor 3 to be controlled. from the output SAM cell 25 _i, 1 horizontal scanning period of the conversion results for each horizontal period (output data) is output.

Note that, as described above, the parallel processor 3
In, the filter coefficient set is output from the memory 28 to the data memory unit 23 of each element processor 30 at the time of startup or the like. When the filter coefficient set is output from the memory 28 to the data memory unit 23, the filter coefficient set is output from the memory 28 to the input data bus 20.
8 (a predetermined number of bits) through the input SAM unit 22
And transferred to the data memory unit 23.

As described above, each element processor 30 of the parallel processor 3 performs processing such as data input, data transfer, operation, and data output according to various control signals input from the program control unit 27a. Then, a filtering process or the like is performed on pixel data (input data) of the original image by a combination of these processes.

Enlarging Process by Parallel Processor 3 Hereinafter, referring to FIGS. 19 to 24, a case where the length of pixel data of an original image is enlarged by (10/7) times as a specific example will be described. Will be described. FIG.
9 is a flowchart showing an image enlargement process by the parallel processor 3 shown in FIG.

FIG. 20 is a diagram showing data stored in each component of the parallel processor 3 (FIG. 16) when performing the image enlarging process shown in FIG. In FIG. 20, each column of the input SAM unit 22 and the like corresponds to one bit. However, the input data Ri and the output data Qi are actually 8 bits, for example, but are represented as 4-bit data in FIG. 20 for simplicity of illustration, and in FIG. Only the contents of the memory necessary for the following description are shown.

As shown in FIG. 19, in step S100, predetermined L-bit input data Ri (= { _ri0- ri _(L-1) }) of one horizontal scanning period is input to the input SAM unit 22. Is done. Note that the process of S100 is not a target of the program process of the program control unit 27a.

When the length of the original image is enlarged by (10/7), the pixel data (input data) of the original image necessary for calculating the pixel data (output data) of the enlarged image is calculated as described above. The element processor 30 that stores the data, and the element processor 3 that calculates pixel data (output data) of the enlarged image.
The positional relationship with 0 changes for each pixel data (output data) of the enlarged image. For example, when calculating the output data of 10 pixels corresponding to the input data of 7 pixels, the pattern of the data reference relationship between the element processors 30 holding the input data necessary for calculating each output data is shown in FIG. And limited to five types as described later with reference to FIG.

As described above, by utilizing the fact that the pattern of the reference relation of the input data between the element processors 30 is limited to five types, as shown in FIG. 20, seven input data (for example, input data R1 to R7) are used. Are output data Q1 to Q10
, And any of the input data R1 to R7) is stored in the ten element processors 30 in a dense array. That is, the element processor 30 to which no input data is supplied (for example, PE1, PE4,
PE5), the same input data as the element processor 30 on the left side is arranged.

Hereinafter, a method of arranging data in element processor 30 will be described with reference to FIGS. 21 and 22. FIG. 21 is a diagram showing four neighbors necessary for Cubic interpolation.
FIG. 17 is a diagram showing five types of access patterns of one input image data [reference relation of input data arranged in each element processor 30 of the parallel processor 3 (FIG. 16)]. 20 and FIG. 21, for example, the output data Q3 is
Input data R1 in PE0, PE2, PE3, PE5
There is a correspondence that is calculated from the data of ~ R4,
The output data Q4 is calculated from the input data R2 to R5 in PE2, PE3, PE5, PE6, and the output data Q5 is PE2, PE3, PE5, PE6 (PE
2, PE4, PE5, PE6).
There is a correspondence that it is calculated from R4. FIG.
Each element processor 30 of the parallel processor 3 (FIG. 16)
In the case where input data is arranged as shown in FIG. 20, two types of reference relationships obtained by organizing the five types of reference relationships shown in FIG. FIG. 11 is a diagram illustrating a reference relationship in a case where access to image data is eliminated and reduced.

As described above, as shown in FIG. 20, each of the element processors 3 of the parallel processor 3 supplies the same input data as the element processors 30 to which no input image data is allocated.
By arranging the input data in 0, for example, when the reference relation of the input data between the element processors 30 adopts the first pattern shown in FIG. Next element processor 30, own element processor 30, right next element processor 3
0 and the input image data to be input to each of the right adjacent element processors 30 is to be accessed. However, the access to the left two adjacent element processors 30 is the same as the access to the left adjacent element processor 30. , And right 2
Since the access to the next adjacent element processor 30 is the same as the access to the next right adjacent element processor 30, the type 1 pattern can be handled (interpolated) in the same manner as the type 2 pattern. . That is, if the mark shown in FIG. 21 is located at the tip of the arrow, the pattern of the mark becomes the same.

When the memory access for the interpolation operation of the element processor 30 adopts the third pattern shown in FIG. 21, the element processor 30 (self) does not refer to the element processor 30 on the left side, but The third pattern can be handled in the same way as the fourth pattern, since the same applies even when the input image data in the own element processor 30 is accessed.

Further, when the memory access for the interpolation operation of the element processor 30 adopts the fifth pattern shown in FIG. 21, the element processor 30 (self) can read the element processor 30 on its right and its own element processor. 30,
Reference is made to the element processor 30 immediately next to the right and the element processor 30 immediately next to the right. However, when the reference pattern adopts the fifth pattern, the memory access to the same input data as the second pattern may be performed.
The fifth pattern can be handled in the same way as the second pattern.

Therefore, by inputting the input data to each element processor 30 as shown in FIG. 20, the five types of patterns of the reference relation shown in FIG.
They are arranged in types of patterns (type 2 and type 4) and degenerated. In the case where the pixel data (input data) of the original image is enlarged or reduced at a conversion ratio other than (10/7), a method of supplying the input data that minimizes the number of reference-related patterns is determined in advance. In addition, the pattern of the reference relation can be degenerated.

As described above, the data reference relation patterns of the five types of element processors 30 shown in FIG. 21 can actually be reduced to two types. 2 shown in FIG.
One-bit data (reference relation data; 0, 1) indicating which of the patterns is to be specified must be specified for each element processor 30, which is input in the same manner as the image input data. It is provided by a method, a method generated by the element processor 30 by a program operation, or a method similar to the filter count, as described later in the third embodiment.

As a method of supplying input data to the element processors 30 in the array shown in FIG. 20, the input data is supplied to each element processor 30 from the beginning so as to form the array shown in FIG. In addition to the method, for example, similarly to the arithmetic unit 1 and the parallel processor 2 (FIGS. 10 and 14) shown in the first embodiment, first, input data is arranged in a sparse array in each element processor 30. After that, according to the control of the program control unit 27a,
There is a method of copying necessary input data from another element processor 30.

Referring again to FIG. Step S102
In step S108, the program control unit 27a
Controls each of the element processors 30 to transfer the supplied input data Ri from the input SAM unit 22 to the data memory unit 23,
Through the write bit line 204, all of the element processors 30 work together to transfer one bit at a time. As illustrated in FIG. 20, the input data Ri has 4 bits, and each bit of the input data Ri is the address 0 of the input SAM unit 22.
4, these data are transferred to addresses 8 to 11 of the data memory unit 23, respectively.

In step S110, each element processor 30 performs signal processing described later with reference to FIGS.

At steps S112 to S118, the program control unit 27a
The calculation result (output data Qi) calculated by the data processor 23 is output from the data memory unit 23 to the output SAM unit 25 via the read bit lines 200 and 202 and the ALU cell 24 _i , one bit at a time by the respective element processors 30. Transfer.
As illustrated in FIG. 20, the output data Qi (= c
_i0 to q ₁₃₎ is 4 bits, the data memory unit 23
If the output data Qi stored in the addresses 16 to 19 of the data memory unit 23 are stored in the addresses 2 to 19 of the output SAM unit 25, respectively.
Transferred to 0-23.

At step S120, the calculated 1
The output data Qi for the horizontal scanning period is output from the output SAM unit 25. Note that the process of S120 is not a program process by the program control unit 27a.

The parallel processor 3 performs a filtering process on pixel data (input data) of the original image for one horizontal scanning period. The parallel processor 3 performs (1) the processing of step S100, (2) the processing of steps S102 to S118, and (3) the processing of (1) to (3) of step S120 in parallel. That is, the parallel processor 3 performs the processing of step S120 on the input data of the immediately preceding horizontal scanning period while performing the processing of steps S102 to S118 on the input data of the predetermined one horizontal scanning period. And step S10 for image data for one horizontal scanning period after one line
0 is performed in parallel.

Processing in step S110 The signal processing in step S110 shown in FIG. 19 will be described below in detail with reference to FIGS.
FIGS. 23 and 24 respectively show S11 shown in FIG.
0 and 1 are a first flowchart and a second flowchart showing detailed processing of the first step.

In the vertical flyback period and the like, a filter coefficient set is received in advance from the data input terminal by the input pointer 21, for example, from the left end side, and stored in the input SAM section of the element processor 30. Transfer to the data memory and set. Note that the filter coefficient set is set in each of the element processors 30 in order, while the pixel data (input data) Ri of the original image is set as shown in FIG.
As shown in FIG. 0, the data is stored in the input SAM unit 22 of each element processor 30 in a pattern different from the order of the element processors 30.

Therefore, for example, a circuit for performing pointer control when the input data Ri is stored in the input SAM unit 22 includes:
The input SAM unit 22 includes two circuits for performing pointer control when storing a filter coefficient set,
, It is necessary that the input pointer 21 can perform independent pointer control in each of these two cases.

As shown in FIG. 23, in step S130, the data memory unit 23 of each element processor 30
Stores the supplied input data, copies the input data stored in the element processor 30 on the left side, and realizes the input of un-tuna data. However, at the time of copying, FIG.
In the input SAM section shown in (1), only the blank spaces are copied. Hereinafter, the predetermined element processor 30, the left adjacent to the predetermined element processor 30, the two adjacent left, the right adjacent,
Element processor 30 next to right and next to right three
Are respectively stored in the input data R ₀ ,
_These are described as R _-1 , R _-2 , R ₊₁ , R ₊₂ , and R ₊₃ .

In step S132, the predetermined element processor 30 calculates the product of the input data R _-1 of the element processor 30 on the left and the filter coefficient FC1 previously input from the memory 28 and stored in the data memory unit, and multiplies the result. The result is a numerical value Y- _A ( _Y1A = R- ₁ * FC1). In addition, AL
The multiplication processing by the U cell 24 _{i is performed} by each of the element processors 30.
ALU cell 24 _i is executed by repeating the bit operation under the control of program control unit 27a.

At step S134, the element processor 30 sets the input data R0 and the filter coefficient FC
2 and the result of the multiplication is set to a numerical value Y _2A (Y _2A = R ₀
× FC2).

In step S136, the element processor 30 adds the numerical values Y _1A and Y _2A and outputs the addition result as the numerical value Y
_1A (Y _1A = Y _1A + Y _2A ). The ALU cell 24
Also in the addition processing by _i, the ALU cell 24 _i of each element processor 30 is controlled by the program control unit 27 similarly to the multiplication processing.
This is executed by repeating the bit operation according to the control of a.

[0210] In step S138, the element processor 30 multiplies the input data R _{+ 2} of the element processor 30 adjacent to the right two by the filter coefficient FC3, and sets the multiplication result to a numerical value _Y2A ( _Y2A = R _{+ 2).} × FC3). Step S14
At 0, the element processor 30 adds the numerical values Y _1A and Y _2A and sets the addition result to the numerical value Y _1A (Y _1A = Y _1A +
Y _2A ).

In step S142, the element processor 30 determines the data R of the next three
₊₃ is multiplied by a filter coefficient FC4, and the multiplication result is set to a numerical value Y _2A (Y _2A = R ₊₃ × FC4).

In step S144, the element processor 30 adds the numerical values Y _1A and Y _2A and outputs the addition result as the numerical value Y
_1A (Y _1A = Y _1A + Y _2A ). Note that the value of the numerical value Y _1A calculated in the process of S144 is R ₋₁ × FC1 + R ₀
× FC2 + R ₊₂ × FC3 + R ₊₃ × FC4, and FIG.
Corresponds to the second pattern shown in FIG.

[0213] In step S146, the processor element 30 includes an input data R _-2 processor elements 30 of the left two neighboring multiplies the filter coefficients FC1, a numerical value Y _1B multiplication result (Y _1B = R _{- 2} x FC1).

In step S148, the element processor 30 multiplies the input data R ₀ stored therein by the filter coefficient FC2, and sets the multiplication result to a numerical value Y _2B (Y _2B = R ₀ × FC2).

Further, as shown in FIG.
At 150, the element processor 30 determines that the values Y _1B , Y
_2B is added, and the addition result is set to a numerical value Y _1B (Y _1B = Y _1B +
_Y2B ).

In step S152, the element processor 30 receives the input data R of the element processor 30 on the right.
₊₁ is multiplied by the filter element FC3, and the multiplication result is set to a numerical value Y _2B (Y _2B = R ₊₁ × FC3).

In step S154, the element processor 31 adds the numerical values Y _1B and Y _2B and outputs the addition result as the numerical value Y
_1B (Y _1B = Y _1B + Y _2B ).

In step S156, the element processor 30 sets the data R
₊₂ is multiplied by the filter element FC4, and the multiplication result is set to a numerical value Y _2B (Y _2B = R ₊₂ × FC4).

In step S158, the element processor 30 adds the numerical values Y _1B and Y _2B and outputs the addition result as the numerical value Y
_1B ( _Y1B = _Y1B + _Y2B ). The value of the numerical value Y _1B calculated by the processing of S158 is R ₋₂ × FC1 + R ₀ × FC
2 + R + 1 ₊ 1FC3 + R ₊ 2.times.FC4, which corresponds to the fourth pattern shown in FIG.

In step S160, the element processor 30 refers to the reference relation data (0, 1) shown in FIG. 22 and sets the value of the reference relation data to the second pattern (FIG. 2).
It is determined whether it is the first value indicating 2). The element processor 30 selects the result of the processing in step S162 when the reference relation data takes the first value, and when the reference relation data is not the first value, that is, corresponds to the fourth pattern shown in FIG. If it is a value, the result of the process of S164 is selected.

[0221] In step S162, the processor element 30, and the numerical value Y _1A calculated by the processing in step S144 the processing result (output data). Step S16
In step 4, the element processor 30 determines in step S158
The numerical value Y _1B calculated in is set as a processing result (output data). As described above, the element processor 30 includes two
Based on the type reference relationship (FIG. 22), a filtering process is performed using input data stored in the neighboring element processors 30.

The parallel processor 3 has a memory 28
(FIG. 16) shows that, as described above, all the element processors 3
0, the element processor 30 that calculates the pixel data (output data) of the enlarged image having the same phase even if the filter coefficient sets corresponding to the respective 0s are stored in advance.
Focusing on performing arithmetic processing using the same filter coefficient set, only the number of filter coefficient sets corresponding to the type of phase may be stored, and the storage capacity of the memory 28 may be reduced.

That is, for example, when the pixel data of the original image is enlarged by a factor of (10/7), there are ten types of phases indicating the positional relationship of the pixel data as the interpolation result with respect to the pixel data of the original image. 28, only 10 types of filter coefficient sets respectively corresponding to 10 types of phases of the pixel data of the original image are stored in advance, and the stored 10 types of filter coefficient sets are stored in the element according to the value of the filter selection number Pi. The parallel processor 3 can be configured so as to be repeatedly set in the processor 30.

Further, a selector circuit for selecting one of the filter coefficient set output from the memory 28 and the pixel data (input data) of the original image is provided on the input side of the input SAM unit 22 to select the filter coefficient set or the input data. For example, the filter coefficient set is set to each of the element processors 30 during a period in which the input SAM unit 22 is not used for supplying the input data Ri, such as a vertical blanking period, for example. The parallel processor 3 can be configured.

As described above, when the parallel processor 3 is configured to selectively set the filter coefficient set using the selector, the bus 208 having the same bit width as the input data is provided.
Can be used to input a filter coefficient set, so that the program control unit 27a can set a filter coefficient set having a large bit width or a filter coefficient set having a long word length to the element processor 30 in a short time. .

Specific examples will be described. For example, the bit width of the filter coefficient is 10 (the total of the set of four filter coefficients is 40 bits), and the input data bus 208 (FIG. 18)
Is a 16-bit width, for example, by separating and transferring FC1 to FC4, a filter coefficient set is stored in the data memory unit 23 via the input SAM unit 22 using four horizontal operation periods, Can be set to

Further, once all the filter coefficient sets have been supplied, for example, four of the input data bus 208
The parallel processor 3 may be configured to gradually change the filter coefficient using a bit width of about a bit. However, when this method is adopted, the filter coefficient set before the change needs to be used as it is in several horizontal scanning periods until the transfer of the filter coefficient set is completed in order to ensure continuity of the filtering process.

Third Embodiment Hereinafter, a third embodiment of the present invention will be described.

[0229] block diagram 25 of the parallel processor 4, a third embodiment of the present invention (parallel processor 4)
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 25, among the components of the parallel processor 4, the parallel processors 2, 3
The same components as those in FIGS. 13 and 16 are denoted by the same reference numerals. Parallel processor 4 shown in FIG.
Is an improvement of the parallel processors 2 and 3 (FIGS. 13 and 16) so that the filter coefficient set is supplied through a different path from the input data Ri.

[0230] As shown in FIG.
Are input pointer 21, input SAM unit 22, data memory unit 23, ALU array unit 24, output SUM cell 2
5 _i , an output pointer 26, a program control unit 27b, and memories 28a and 29. That is, the parallel processor 4 replaces the program control unit 27a of the parallel processor 3 (FIG. 16) with the program control unit 27b, replaces the memory 28 with the memory 28a,
Is adopted.

Components of the Parallel Processor 4 Hereinafter, of the components of the parallel processor 4, those different from the components of the parallel processors 2 and 3 will be described.

Memory 29 The memory 29 stores a filter coefficient set which is input in advance from an external control device (not shown) or the like and corresponds to each phase of a pixel of a processing result (output data). Also, memory 2
Reference numeral 9 denotes a data memory of the element processor 30 that calculates the stored filter coefficient set and the pixels of the output data of the corresponding phase during startup, a horizontal retrace period, a vertical retrace period, or the like, under the control of the program control unit 27b. The data is stored in the unit 23 via the ALU array unit 24.

Memory 28a Memory 28a is input in advance from an external control device or the like,
A filter selection number i indicating the phase of each pixel of the output data calculated by each element processor 30 with the pixel of the input data
(Corresponding to the filter selection signal Pi shown in FIG. 12). The memory 28a also stores the stored filter selection number i via the input data bus 208 via the input data bus 208, similarly to the filter coefficient set in the parallel processor 3.
Output to the data memory unit 23 together with i.

Note that, like the above-described filter selection signal Pi, the filter selection number i can be expressed by 4 bits, so that the memory 28a stores 4-bit data as the filter selection number i. The filter selection number i stored in the memory 28 is, for example, 10 when the phase of the pixel of the output data and the phase of the pixel of the input data are 10 irrespective of the number H of pixels included in one horizontal scanning period. Become.

Further, for example, even if the filter selection number i is 1,000 types, there is no practical problem since it can be expressed as 10-bit data.

Program control unit 27b The program control unit 27b controls each component of the parallel processor 4 in the same manner as the program control unit 27a in the parallel processor 3, and performs the operation described later.

FIG. 26 shows the filter selection number i (= ｛φ) stored in the data memory unit 23 of each element processor 30.
_{i0 ~φ i3; φ} denotes a 1,0 in the case of bit resolution})
FIG. As shown in FIG. 26, the data memory unit 23 of the parallel processor 4 stores i × 10 types of filter selection numbers i (i = 0 to 9) as 4-bit data. In other words, a specific example, the data memory unit 23 of the sixth element processor 30 of (No. 6), the filter selection number i of data; storing _{{i = 2 φ 20 ~φ 23} }.

The filter coefficient set to the data memory unit 23 is
Hereinafter, the operation of each component of the parallel processor 4 when the filter coefficient set is supplied to the data memory unit 23 of each element processor 30 will be described with reference to FIG. FIG.
7 is a flowchart showing the operation of the parallel processor 4 when supplying the filter coefficient set of the memory 29 to the data memory unit 23 of each element processor 30.

As shown in FIG. 27, in step S170, the program control section 27b sets the count value of the counter j for counting the filter selection number i corresponding to the supplied filter coefficient set to 0.

In step S172, the program control section 27b sets the count value of the counter m used for supplying the count value of the counter j in bit units to 1. In step S174, the program control unit 27b is the ALU cell 24 _i of all the processor elements 30, and outputs the m-th bit of the count value of the counter j. ALU cell 24 _i of each element processor 30 receives data input from the program control unit 27b.

At step S176, program control unit 27b determines whether or not the count value of counter m is equal to or greater than the bit length of counter j. Program control unit 2
7b, when the count value of the counter m is equal to the bit length of the counter j, it means that the last bit of the filter selection number i has been supplied. If the bit length is equal to or less than the bit length of the counter j, the process returns to step S174.

In step S178, the program control section 27b increases (increments) the count value of the counter m by 1, and returns to the processing in step S174. Steps S170 to S178 described above
, The count value of the counter j is output to each element processor 30 bit by bit.

In step S180, each element processor 30 determines whether or not the count value of the input counter j is equal to the value of the filter selection number i previously input from the memory 28a. In some cases, j and m are given to the memory 29 to receive the read j-th filter coefficient set, and further set a predetermined flag. If the count value of the counter j is not the same as the filter selection number i, the element processor 30 does not receive the filter coefficient set from the memory 29 and returns to steps S182 to S182.
The process of step S188 is skipped.

In step S182, each element processor 30 sets the count value of the counter k for counting the total number of bits of the filter coefficient set to 1, according to the value of the flag.

In step S184, each element processor 30 sends the ALU array unit 24 (AL
U-cell 24 _i ; the k-th bit of the filter coefficient set received by FIG.
Remember. The memory 29 stores each filter coefficient set corresponding to each phase (filter selection number i)
Most significant bit (MSB) or least significant bit (LSB)
, And the stored filter coefficient sets are stored in a 1-bit wide line (from memory 29 to AL
A of the element processor 30 via the wiring to the U array unit)
The bits are sequentially output to the LU cell 24 _i one bit at a time.

[0246] In step S186, each element processor 30 determines whether or not the count value of the counter k is equal to or greater than the total bit length of the filter coefficient set. If the count value of the counter k is smaller than the total bit length of the filter coefficient set, the process proceeds to S188. If the count value of the counter k is equal to or greater than the bit length of the filter coefficient set, the Since the input of the filter coefficient set corresponding to the count value of has been completed,
Proceed to step S190.

[0247] In step S188, the element processor 30 increases (increments) the count value of the counter k by 1, and returns to the processing in step S184.

In step S190, the program control unit 27b determines that the count value of the counter j is equal to or greater than the value (N-1) obtained by subtracting 1 from the number N of the types of phases of the output data pixels and the input data pixels. If the count value of the counter j is equal to or more than (N-1) (j≥N-1), it is determined that all of the N filter coefficient sets have been supplied to each element processor 30. Then, the process of supplying the filter coefficient set ends. Also, the program control unit 27b
Indicates that the count value of the counter j is smaller than (N-1) (j <
In the case of (N-1), the process proceeds to step S192.

At step S192, the program control section 27b increases (increments) the count value of the counter j by 1 and returns to the process at step S172 to supply the filter coefficient set corresponding to the next filter selection number i. I do.

By the processing shown in steps S170 to S192 in FIG. 27, each element processor 30 of the parallel processor 4 receives the filter coefficient set corresponding to the preset filter selection number i from the memory 29, and The information is stored in the unit 23.

The operation other than the operation of the parallel processor 4 for supplying the filter coefficient set, for example, the image processing operation,
This is the same as the image processing operation of the parallel processors 2 and 3 (FIGS. 13 and 16) shown as the first and second embodiments.

As described above, according to the parallel processor 4, the filter coefficient set can be selectively supplied to the element processor 30 by supplying the filter coefficient set through a path different from the input data Ri. .

According to the parallel processor 4, the process of supplying the filter coefficient set to the element processor 30 is easy, and the number of steps of the program used for supplying the filter coefficient set is small. Further, according to the parallel processor 4, the filter coefficient set is supplied to the data memory unit 23 of each element processor 30 through a different path from the input data.
The filter coefficient set can be supplied at an arbitrary timing irrespective of the operation status of the.

The features of the parallel processor 4 will be further described with reference to specific examples. According to the processing shown in FIG. 27, for example, when ten types of filter coefficient sets stored in the memory 29 are supplied to each element processor 30, one filter coefficient set is used for all the element processors 30.
Are supplied to about one-tenth of the element processors 30 at the same time. Therefore, a filter coefficient set having a data amount of 40 bits is set to 400 (4
It can be supplied to all the element processors 30 by the program processing of (0 bits × 10) steps.

Fourth Embodiment Hereinafter, a fourth embodiment of the present invention will be described. The fourth embodiment is different from the parallel processor 3 shown in FIG.
6), the memory 28 is executed by the parallel processor 4 (FIG. 2).
The filter selection number is stored in advance similarly to the memory 28a of 5), and each element processor 30 is modified so as to calculate a filter coefficient set according to the filter selection number i.

Filter in Parallel Processor 3 (FIG. 16)
Several sets of calculation operation below with reference to FIGS. 28 and 29, in the fourth embodiment, when the parallel processor 3 is to scale the pixel data of the original image, the filtering process by Cubic approximation method (Equation 4) The operation of each component at the time of calculating the filter coefficient set used for will be described. FIG. 28 and FIG.
9 are the parallel processors 3 in the fourth embodiment, respectively.
17A and 17B are first and second diagrams illustrating a filter coefficient set calculation operation of FIG.

As shown in FIG. 28, in step S200, the element processor 30
a, based on the numerical values K and L indicating the image conversion ratio (K / L) and the value of the filter selection number i supplied in advance, the pixel of the enlarged / reduced image (output data) and the original calculating the phase i / K of a pixel of the image (input data) is stored as a numerical value X _0.

At step S202, the element processor 30 substitutes the numerical value X ₀ for the numerical value X. Step S2
At 04, the element processor 30 calculates the square value (X ² ) of the numerical value X and stores the calculation result as the numerical value X ₂ . In step S206, the element processor 30
Multiplies the numerical value X ₂ by the numerical value X and stores the multiplication result (X ³ ) as the numerical value X ₃ .

In step S208, the element processor 30 calculates the numerical values X, X ₂ , and X ₃ by using Expression 4.
The filter coefficient FC3 is calculated according to the following equation.

[0260]

Equation 5 FC3 = −X ₃ −2X ₂ +1 (5)

In step S210, the element processor 30 adds 1 to the numerical value X ₀ (i / K) and substitutes it for the numerical value X. In step S212, the element processor 30 calculates a square value (X ² ) of the numerical value X, and substitutes the calculation result into X ₃ . In step S214, the processor element 30 multiplies the numerical value X ₂ and numeric X, assigns the result of the multiplication (X ³⁾ to the numerical X _3.

In step S216, the element processor 30 calculates the filter coefficient FC4 from X, X ₂ and X ₃ according to the following equation, using equation (4).

[0263]

FC4 = −X ₃ + 5X ₂ −8X + 1 (6)

As shown in FIG. 29, in step S218, the element processor 30 subtracts the numerical value X ₀ from 1 and substitutes the subtracted value (1−X ₀ ) for the numerical value X.

In step S220, the element processor 30 calculates the square value of the numerical value X, and substitutes the calculated value (X ² ) for the numerical value X ₂ . In step S222, the processor element 30 multiplies the numerical value X ₂ and numeric X, is substituted multiplied value (X ³⁾ to the numerical X _3.

In step S224, the element processor 30 calculates the numerical values X, X ₂ , and X ₃ based on the equation (4).
The filter coefficient FC2 is calculated according to the following equation.

[0267]

Equation 7 FC2 = X ₃ −2X ₂ +1 (7)

In step S226, the element processor 30 adds 1 to the numerical value X, calculates the added value, and substitutes the addition result (X + 1) for the numerical value X.

In step S228, the element processor 30 calculates the square value of X, and substitutes the calculation result (X ² ) for the numerical value X ₂ . In step S230, the processor element 30 multiplies the numerical value X ₂ and numeric X, assigns the result of the multiplication (X ³⁾ to the numerical X _3.

[0270] In step S232, the element processor 30 calculates the numerical values X, X ₂ , and X ₃ based on equation (4).
The filter coefficient FC1 is calculated according to the following equation.

[0271]

Equation 8 FC1 = −X ₃ + 5X ₂ −8X + 4 (8)

As described above, by the processing of steps S200 to S232 shown in FIGS. 28 and 29, the element processor 30 of the parallel processor 3 sets the filter selection number i
Filter coefficient sets (FC1 to FC4) are calculated according to.

According to the filter coefficient calculating operation of the parallel processor 3 shown as the fourth embodiment, each element processor 30 calculates a filter coefficient set. Therefore, an external memory (memory 28, 29 etc)
It is not necessary to supply the filter coefficient set from, and there is no need to adjust the timing of image processing and the timing of supplying the filter coefficient set.

FIGS. 28 and 29 show Cubi
Although the operation of the parallel processor 3 when calculating the filter coefficient set using the c-approximation method has been described, it is possible to calculate the filter coefficient set used for the filtering process by another approximation method by appropriately changing the operation. It is possible.

Fifth Embodiment Hereinafter, a fifth embodiment of the present invention will be described.

Configuration of Parallel Processor 5 FIG. 30 shows a fifth embodiment (parallel processor 5) of the present invention.
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 30, among the components of the parallel processor 5, the same components as those of the parallel processors 2 to 4 shown as the first to third embodiments are denoted by the same reference numerals. It is.

As shown in FIG. 30, the parallel processor 5
Are input pointer 21, input SAM unit 22, data memory unit 23, ALU array unit 24, output SUM cell 2
5 _i , an output pointer 26, a program control unit 27 c and a memory 29. That is, the parallel processor 5 deletes the memory 28a of the parallel processor 4 (FIG. 25) shown as the third embodiment, and
A configuration is adopted in which b is replaced with a program control unit 27c.

The parallel processor 5 includes the element processor 30
Is an improvement of the operation of the parallel processor 4 (FIG. 25) so as to calculate the filter selection number i. Each process other than the process of calculating the filter selection number i of the parallel processor 5 (image processing, supply of a filter coefficient set, etc.)
Are the same as those of the parallel processor 4 (FIG. 25).

[0279] Operation of the program control unit 27c program control unit 27c, compared with the operation of the program control unit 27b of the parallel processor 4 (Fig. 25), has been modified as described below with reference to FIG. 31 or the like.

The operation of the parallel processor 5 when calculating the filter selection number will be described below with reference to FIG. FIG. 31 is a flowchart illustrating the operation of calculating the filter selection number i by the parallel processor 5.

As shown in FIG. 31, in step S240, element processor 30 secures registers ZA ₀ , ZB ₀ , and ZC ₀ as work spaces, respectively.

[0282] In step S242, the processor elements 30, numeric register _{ZA 0, ZB 0, ZC 0} 0
Is stored.

[0283] In step S244, each element processor 30 registers the register Z of the element processor 30 on the left.
The stored value ZA _{-1 of} A ₀ and the numerical value L of the numerical values K and L input from the program control unit 27c and indicating the conversion ratio K / L when the image length of the original image is scaled up / down. Add
The addition result (ZA _-1 + L) is stored in the register ZA ₀ .
Note that the leftmost element processor 30 in the parallel processor 5 does not have the element processor 30 on the left side, and therefore performs the process of step S244 with the stored value of the register ZA- ₁ set to 0.

[0284] In step S246, the processor elements 30, stored value of the register ZA ₀ is determined whether the number greater than K, when the stored value of the register ZA ₀ is a number greater than K, the processing of step S248 advances to, when the stored value of the register ZA ₀ is not larger than the value K, the process proceeds to step S250.

In step S248, each element processor 30 calculates a remainder when the storage value of the register ZA ₀ is divided by the numerical value K, and stores the remainder value in the register ZA ₀ . The element processor 30 determines in step S248
Is calculated by repeating the subtraction. Although the process of calculating the remainder has many processing steps, the process of calculating the filter selection number i is performed in advance before performing real-time image processing, or performed during a vertical blanking period or the like. Does not occur.

In step S250, each element processor 30 determines whether or not the processing in steps S244 to S248 has been repeated more than the number of element processors, and determines whether the operation in step S244 to step S248 is equal to or less than the number of element processors. If only this has been repeated, the process returns to step S244. In addition, each element processor 30 performs steps S244 to S248.
Is repeated more times than the number of element processors, the process proceeds to step S252.

[0287] In step S252, each element processor 30 registers the register Z of the element processor 30 on the left.
The stored value ZB _{−1 of} B ₀ and the numerical value L are added, and the addition result (Z
B _-1 + L) in the register ZC ₀ . Note that the leftmost element processor 30 does not have the element processor 30 on the left side, so the storage value ZB _{−1 is set} to 0 and the processing of step S252 is performed.

[0288] In step S254, the processor element 30 determines whether or not the stored value of the register ZC ₀ is greater than 2 times the value of the numerical K, than twice the value of the stored value is numeric K registers ZC ₀ If larger, step S25
Then, the process proceeds to step 6, where the stored value of the register ZC ₀ is 2
If the value is not larger than the double value, the process proceeds to step S258.

In step S256, element processor 30 subtracts numerical value K from the stored value of register ZB ₀ and stores the subtracted value (ZB ₀ -K) in register ZB ₀ . In step S258, the element processor 30
Subtracts the numeric value K from the stored value of the register ZC ₀ and stores the subtracted value (ZC ₀ −K) in the register ZB ₀ .

In step S260, each element processor 30 determines whether or not the processing in steps S252 to S258 has been repeated more than the number of element processors, and determines the operation in step S252 to step S258 based on the number of element processors. If not, the process returns to step S252. If the element processor 30 repeats the operations of steps S252 to S258 more than the number of pixels of the enlarged / reduced image (output data) in the horizontal direction, the process proceeds to step S262.

In step S262, each element processor 30 determines whether or not the numerical value K is larger than the numerical value L, that is, whether or not image enlargement processing is being performed. The process proceeds to step S266, and if the value K is not greater than the value L, the process proceeds to step S264.

[0292] In step S264, the processor element 30 using the storage value of the register ZB ₀ as the filter selection number i. In step S266, the element processor 30 sets the register Z as the filter selection number i.
The stored value of A ₀ is used.

As described above, each element processor 30 of the parallel processor 5 calculates the filter selection number i by the processing shown in FIG.

Note that step S246 and step S246
In response to the determination at 254, the correspondence between input data or output data and the element processor 30 (how to input Ri in FIG. 14) may be set. That is, in step S248, since the same processing as the above-described modulo operation of the phase is performed, step S2
By comparing the number of the pixel on which the modulo operation is performed and the number of the pixel calculated by the element processor in accordance with the determination at 46, input data assigned to the element processor 30 can be determined.

Sixth Embodiment Hereinafter, a sixth embodiment of the present invention will be described.

Configuration of Parallel Processor 6 FIG. 32 shows a sixth embodiment (parallel processor 6) of the present invention.
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 32, among the components of the parallel processor 6, the parallel processors 2 to 5 (FIGS. 13, 16 and 2) shown as the first to fifth embodiments are shown.
5, the same components as those of FIG. 30 are denoted by the same reference numerals.

[0297] As shown in FIG.
Are input pointer 21, input SAM unit 22, data memory unit 23, ALU array unit 24, output SUM cell 2
5 _i , output pointer 26 and program control unit 27d
Consists of That is, the parallel processor 6 adopts a configuration in which the program control unit 27 of the parallel processor 3 (FIG. 13) is replaced with a program control unit 27d.

The parallel processor 6 selects the filter selection number i
And the filter coefficient sets corresponding to the parallel processors 3 and 5 (FIG. 1) shown in the fourth and fifth embodiments.
3, FIG. 30), the memory 28, 28a, 2
9 is unnecessary.

Program control unit 27d The program control unit 27d controls each element processor 30, and controls the program control units 27 and 27 of the parallel processors 3 and 5 (FIGS. 16 and 30) shown in the fourth and fifth embodiments. 2
Similarly to 7c, a filter selection number i and a corresponding filter coefficient set are calculated. The operation of the parallel processor 6 when performing the filter selection number i and filter coefficient set calculation processing and other processing (image processing and the like) is the same as that of the parallel processor 3 shown in the fourth and fifth embodiments. , 5 (FIGS. 16 and 30).

As shown in FIG. 12, among the 8-bit filter coefficient sets corresponding to the phases of the pixel data (input data) of the original image and the pixel data (output data) of the enlarged / reduced image, Phases P1, P2, P3, P8, P
The sum of the nine filter coefficient sets does not become 128 (1,0 in real number representation), and an error occurs. This error is generated when the filter coefficient set is quantized to 8 bits. If these filter coefficient sets are used as they are, for example, an output obtained by enlarging / reducing input data having a large DC component is obtained. A pulsating flow may occur in the data, and the image may be degraded. Therefore, it is preferable to correct the filter coefficients FC1 to FC4 so that the above-mentioned sum becomes 128.

When correcting the filter coefficients, the filter coefficients FC1 and FC4 are better than the filter coefficients FC2 and FC3.
It is more preferable to correct the filter coefficients FC1 and FC4, since correcting the correction has less influence on the characteristics of the interpolation filtering. For example, by changing the value of the filter coefficient FC1 corresponding to the phase P1 shown in FIG. 12 from -1 to -2, the total sum of the filter coefficients becomes 128.

[0302] The one having the largest error when the filter coefficient set is quantized to 8 bits may be corrected. Explaining with a specific example, for example, the filter coefficient FC3 of the phase P3 shown in FIG. 12 is 0.368 in the real number representation and 46 in the 8-bit representation. The error is 0.464 (= 0.363 × 128−
46). Therefore, the filter coefficient FC of the phase P3
By changing the value of 3 from 46 to 47, the sum of the filter coefficients can be made 128, and the influence on the characteristics of the interpolation filtering can be minimized.

[0303] In each of the above-described embodiments, the image enlarging process is mainly described as an example. However, it is needless to say that the image can be reduced. However,
When performing image reduction processing, the input SAM unit 22 is supplied with input data densely in order, and the output SAM unit 25
, Output data is sparsely output.

In each of the above-described embodiments, another element processor 30 for storing data necessary for interpolation filtering exists around the right and left element processors 30 for processing pixel data at the end of an image. In the case where the image data does not exist, the processing using the numerical value 0 instead of the non-existing data is described. For example, the pixel data at the end of the image is continuous outside the image, or the pixel data is symmetrical around the end. For example, various methods can be adopted for the processing at the edge of the image, for example, assuming that the above-mentioned condition is satisfied. Any of the methods can be adopted by changing the program.

In each of the embodiments described above, each element processor 30 performs only a filter operation corresponding to pixel interpolation. For example, various filter processes, color operations, and data of a predetermined transmission method may be used. By changing or adding the program of the program control unit to various image processing and TV (television) signal processing that you want to execute simultaneously with the conversion of the number of pixels, such as conversion to noise, noise reduction, and contour enhancement, These processes can be performed without changing the hardware configuration. Further, by changing the program of the program control unit, the conversion ratio of the image can be changed.

The storage capacities of the memories 28, 28a, 29 (FIGS. 16, 25, 30, etc.) of the respective parallel processors shown in the respective embodiments described above are equal to those of the pixels of the original image.
The number is relatively small in proportion to the number of phases of the pixels of the reduced image. Therefore, the provision of the memories 28, 29 and the like has a very small effect on the hardware scale of the parallel processor.

Seventh Embodiment Hereinafter, a seventh embodiment of the present invention will be described. FIG. 33 is a diagram showing the configuration of the seventh embodiment (image data processing device 7) of the present invention. As shown in FIG. 33, the image data processing device 7 includes a selector circuit (SEL) 60 and a memory circuit 62, and performs non-linear processing of an image by a so-called memory mapping method under the control of a control system.

In the image data processing device 7, when performing a non-linear process on the components of the color signal, the control system (not shown) controls the selector circuit 60 to select the component of the input color signal. When the control is performed and the non-linear data is stored in the memory circuit 62, the selector circuit 60 selects the data to be output by the control system.
Control.

The selector circuit 60 controls the components (R, G, B, and R) of the data input from the control system or the color signal input from the outside according to the control by the control system.
Y, I, Q, etc.) are selected and output to the address input section of the memory circuit 62.

As described above, the memory circuit 62 previously stores non-linear data output from the control system and defining the non-linear characteristics between each component of the color signal and the output data. And outputs nonlinear data set at an address corresponding to the value of each component of the color signal, and performs nonlinear processing.

To change the content of the nonlinear processing by the image data processing device 7, the control system may change the nonlinear data stored in the memory circuit 62.
That is, the control system can freely change the content of the nonlinear processing only by changing the value of the data stored in the address of the memory circuit 62 corresponding to the value of the component of the input color signal.

Eighth Embodiment Hereinafter, an eighth embodiment of the present invention will be described. The image data processing device 7 (FIG. 33) shown in the seventh embodiment performs non-linear processing by associating the values of input data (components of color signals) with the values of output data via the memory circuit 62. Can be. Moreover, according to the image data processing device 7, the content of the nonlinear processing can be changed only by the control system changing the content of the nonlinear data stored in the memory circuit 62.

Here, also in the image data processing device 7, the contents of the nonlinear data stored in the memory circuit 62 are as follows:
The editor who uses the image data processing device 7 needs to create it. The creation of this non-linear data, for example,
It is convenient if it can be performed by an operation applying I. However, a method of designating the processing content of the GUI application has not been established.

Further, the confirmation of the image processed by the image data processing device 7 is performed, for example, by reproducing and displaying the image data once recorded on a VTR tape or the like.
It is very time-consuming. The eighth embodiment of the present invention has been made in order to solve such a problem, and it is possible to specify the content of nonlinear processing on image data by using a GUI. Is configured so that the image obtained as a result of the above can be immediately confirmed on the GUI screen.

Structure of Image Data Processing System 8 FIG. 34 is a diagram showing the structure of the eighth embodiment (image data processing system 8) of the present invention. In FIG. 34, among the components of the image data processing system 8, FIG.
The same components as those of the image data processing device 7 shown in FIG. As shown in FIG. 34, the image data processing system 8 includes an input device 70, a personal computer 72, an image source 74, an image data processing device 7, and an image monitor 76.

The personal computer 72 of the image data processing system 8 includes a computer, a hard disk drive (HDD) and a monitor. The CPU bus of the personal computer 72 is connected to the input device 70 and the image data via a predetermined interface board. It is connected to the processing device 7. Personal computer 7
2 controls the selector circuit 60 of the image data processing device 7 and generates non-linear data based on the non-linear characteristics input from the input device 70, similarly to the control system described in the seventh embodiment. The generated non-linear data is set in the memory circuit 62, and a GUI image for inputting the non-linear characteristic is displayed on the monitor and displayed to the user.

The input device 70 is operated by a user of the image data processing system 8 on a GUI screen of a monitor of the personal computer 72 such as a mouse, a keyboard, a tablet, a trackball, and an accu point.
The non-linear characteristics of the components of the color signal input to the image data processing system 8 and the output data are accepted and output to the personal computer 72.

The image source 74 is, for example, a digital camera or a digital VTR, and supplies each component of a color signal to the selector circuit 60. When processing each component of the color signal in parallel, the image data processing device 7 is actually provided with a plurality of image data processing devices 7 corresponding to the components of these color signals, respectively, as in the seventh embodiment. Using the non-linear data set by the personal computer 72, the components of the input color signal are non-linearly processed and output to the image monitor 76. The image monitor 76 displays image data input from the image data processing device 7.

When an image is displayed on the image monitor 76, it is necessary to convert the image data into an analog image signal for display. Therefore, a D / A conversion circuit is actually required. When an analog VTR device is used, an A / D conversion circuit is required to supply digital image data to the image data processing device 7, but in FIG.
6 and the image source 74 include D / A
The conversion circuit and the A / D conversion circuit are omitted.

GUI Screens FIGS. 35A to 35D show a personal computer 72.
Is a view showing a GUI image displayed on the monitor.
Actually, a plurality of windows of the GUI screen are provided corresponding to the types of color signals (RGB, YIQ, and YCrCb) and the components of each color signal. That is, for example, the image data processing system 8
However, when nonlinear processing is performed on each component of the RGB signal and each component of the YIQ signal, six windows corresponding to each of these components are displayed on the GUI screen. However, for simplicity of description and illustration, FIGS. 35A to 35D show only the window of the GUI image corresponding to one component signal of one type of color signal.

As shown in FIGS. 35A to 35D, the GU
The window of the I-screen occupies a large portion at the top of the window, and a function graph portion for displaying a function indicating a nonlinear characteristic in a graph format, and for switching between Add (add), Move (move), and Delete (delete) modes. And a mode switching portion for displaying a radio button of

The horizontal axis of the function graph portion indicates the value of the component of the input color signal, and the vertical axis indicates the value of the output data. In other words, a perpendicular is drawn to the component signal value on the horizontal axis, and a straight line that passes through the intersection of this perpendicular and the curve of the graph and is parallel to the horizontal axis is drawn. Indicate the value of output data corresponding to the value of the input component.

As described above, the mode switching portion includes
Radio buttons for Add (add), Move (move), and Delete (delete) are displayed.
By clicking these radio buttons with the mouse of the input device 70, one of the modes is designated for the personal computer 72. Note that even when the user does not select any mode, the personal computer 72 displays a window in any mode on the monitor.

[0324] Among these modes, the Add mode is, as shown in FIG. 35 (A), the position of the graph designated by the user clicking on the input device 70 with the mouse in the function graph portion. It is used when performing an operation of adding a point (passing point) through which a curve passes.

In the Move mode, as shown in FIG. 35B, the user designates the point on the curve of the function graph closest to the position designated by clicking with the mouse by dragging the mouse. Used when performing an operation of moving to a position. In the Delete mode, FIG.
As shown in FIG. 5 (C), this is used when the user performs an operation of deleting a passing point specified in the Add mode or the like.

Operation of Image Data Processing System 8 The operation of the image data processing system 8 will be described below. FIG. 36 is a flowchart showing the processing of the image data processing system 8 shown in FIG. First, the personal computer 72 displays a window in one of the modes shown in FIGS. 35A to 35C on a monitor in response to a user operation on the input device 70. FIG. 35 (A)-
The initial function displayed in the function graph portion of (C) is, for example, y = x (where x is the value of the component input to the image data processing device 7, and y is the value of the output data of the image data processing device 7) ), And the graph showing this initial function is a straight line rising to the right.

Next, as shown in FIG. 36, step S3
At 00, the user appropriately uses the mouse or the like of the input device 70 to appropriately specify the non-linear characteristic of each component (for example, Y, Cr, Cb, R, G, B) of each color signal. , Mode setting and addition, movement, and deletion of passing points, and setting of nonlinear characteristics (γ correction function) for each of these components independently. The personal computer 72 sequentially displays, on a monitor, a curve (polyline) of a graph of a function passing through each passing point according to a user operation.

When the user clicks the execution button (not shown) in the GUI screen using the mouse of the input device 70, for example, the personal computer 72 is notified of the end of the designation of the nonlinear characteristic. In step S302, the personal computer 72 extracts a line function of the final nonlinear characteristic of each component specified by the user.

In step S304, the personal computer 72 calculates the non-linear data (memory data) of each component stored in the memory circuit 62 of the image data processing device 7 based on the polygonal line function extracted according to the user's designation. I do. In step S306, the personal computer 72 stores the calculated nonlinear data in the memory circuit 62 of the image data processing device 7 that processes each component.

When the above operations are completed, the personal computer 72 controls the selector circuit 60 of each image data processing device 7 to process each component of each color signal input from the image source 74 and process these components. Output to each of the image data processing devices 7 to be executed.

Each of the image data processing devices 7 performs nonlinear processing on the input component as described in the seventh embodiment, and outputs output data to the image monitor 76. The image monitor 76 converts the components of the color signals output by the respective image data processing devices 7 into video signals in an analog format, and displays and displays them to the user.

Ninth Embodiment Hereinafter, a ninth embodiment of the present invention will be described. According to the image data processing system 8 shown as the eighth embodiment, the contents of the non-linear processing are converted into the components (Y, Cr,
Cb, R, G, B, etc.) can be arbitrarily set using the GUI, and the processing result can be immediately confirmed on the monitor.

However, the image data processing system 8
(FIG. 34) is configured exclusively for non-linear processing such as color correction and gamma correction. Further, if another processing such as imparting a special effect is to be performed, another processing apparatus is added to the image data processing system 8. It needs to be added. The ninth embodiment of the present invention is configured to perform non-linear processing on image data using a DSP in order to solve the above-described problem.

Structure of Image Data Processing System 9 FIG. 37 is a diagram showing the structure of the ninth embodiment (image data processing system 9) of the present invention. Note that among the components of the image data processing system 9 shown in FIG. 37, the same components as those of the image data processing system 8 shown in FIG. 34 are denoted by the same reference numerals. As shown in FIG. 37, the image data processing system 9 adopts a configuration in which the image data processing device 7 of the image data processing system 8 (FIG. 34) described in the eighth embodiment is replaced with a DSP 80.

DSP80 SIMD control linear array type multi-parallel type DSP80
For example, the parallel processors 2 to 6 shown in the second to sixth embodiments (FIGS. 13, 16, 25, 30, and 3)
In 2), the components of the color signal input by the SIMD control are processed in parallel and output to the image monitor 76.

Operation of Image Data Processing System 9 The operation of the image data processing system 9 will be described below. FIG. 38 is a flowchart showing the processing of the image data processing system 9 shown in FIG. FIG. 39 is a diagram illustrating a polygonal line function extracted by the personal computer 72 of the image data processing system 9 shown in FIG.

In the image data processing system 9, first, as in the image data processing system 8 (FIG. 34), the personal computer 72 responds to a user's operation on the input device 70 in FIGS. One of the windows in the mode shown in C) is displayed on the monitor.

Next, as shown in FIG. 36, step S3
In 10, the user appropriately uses a mouse or the like of the input device 70 to a window for designating the nonlinear characteristics of each component (for example, Y, Cr, Cb, R, G, B) of each color signal. , Mode setting and addition, movement, and deletion of passing points, and setting of nonlinear characteristics (γ correction function) for each of these components independently. As in the image data processing system 8, the personal computer 72 sequentially displays, on a monitor, a curve (polyline) of a graph of a function passing through each passing point according to a user operation.

When the user clicks the execution button (not shown) in the GUI screen using the mouse of the input device 70, for example, the personal computer 72 is notified of the end of the designation of the nonlinear characteristic. In step S312, the personal computer 72 operates as shown in FIG.
9 is displayed in the window of each component [FIG. 35].
(D)].

In step S314, the personal computer 72 generates a program for the linear array type multi-parallel processor (DSP80) to execute the nonlinear processing indicated by the extracted broken line function. Step S
At 316, the personal computer 72 downloads the generated program to the DSP 80.

By the operations described in the second to sixth embodiments,
The DSP 80 performs nonlinear processing on the input components as described in the second to seventh embodiments, and outputs output data to the image monitor 76. The image monitor 76 converts the components of the color signal output by the DSP 80, as in the image data processing system 8,
The video signal is converted into an analog video signal, displayed and shown to the user.

Example of Program of DSP 80 An example of a program that the personal computer 72 downloads to the DSP 80 will be described below. S in FIG.
By the processes of 312 and S314, the personal computer 72 sets the non-linear characteristic to, for example, as shown in FIG. 39, in each of N regions, a set of linear functions defined by the following equations (N-line function) Extract as Therefore, the non-linear processing can be realized by performing a linear operation for each of these N regions.

[0343]

Y = a ₁ x + b ₁ [0 (minimum value) <x ≦ 30; x ₁ = 30] y = a ₂ x + b ₂ [30 <x ≦ 80; x ₂ = 80] y = a ₃ x + b ₃ [80 <x ≦ 120; x ₂ = 120] y = a _N x + b _N [200 <x ≦ 255 (maximum value); x ₂ = 255] (9)

Referring to FIG. 40, the processing contents of the program downloaded by personal computer 72 to DSP 80 will be described below. FIG. 40 illustrates the non-linear processing by N
DS realized by performing a linear operation for each area
FIG. 38 is a flowchart showing a program of P80 (FIG. 37).

First, the DSP 80 secures an area in the memory for storing the coefficient of each linear function shown in Expression 5. In step S320, the DSP 80 sets the component value x of the input color signal to the first boundary value x of the region.
_It is determined whether it is greater than ₁ or not.
If not, the process proceeds to S334.

At step S322, the DSP 80
Substitutes coefficient a ₂ [a (2)] shown in equation 5 for variable A, and substitutes coefficient b ₂ [b (2)] for variable B. In step S334, the DSP 80 substitutes the coefficient a ₁ [a (1)] shown in Expression 5 for the variable A, and substitutes the coefficient b ₁ for the variable B.
[B (1)] is substituted.

[0347] In step S323, the DSP 80
Substitutes a numerical value 2 for a variable i. In step S324, the DSP 80 determines whether or not the variable i is smaller than the number N of areas. If i <N, the process proceeds to step S326, where i <
If it is not N, the process proceeds to S332. Step S3
In the process of 26, the DSP 80 determines whether or not the component value x is greater than x _i [x (i)] of each expression of Expression 5, and if x> x _i , proceeds to the process of S328. . If not, x> x _i proceeds to a process of S330.

[0348] In step S328, the DSP 80
Are the coefficients a _{i + 1} , b shown in Equation 5 for variables A and B, respectively.
_{i + 1} is substituted and stored, and the process proceeds to S335. In step S330, the DSP 80 stores the values of the variables A and B, and proceeds to the processing of S335. In step S335, the DSP 80 adds the numerical value 1 to the variable i, and in S330
Proceed to processing. In step S332, the DSP 80
Calculates the value of output data y (y = Ax + B) by multiplying the component value x by variables A and B and further adding variable b.

In other words, the DSP 80 performs the above-described S3
The following processes are performed instead of the processes of 26 to S332 and S335. In the process of step S326, the DSP 8
0 means that the component value x is x _i [x
(2)] to determine greater or not, proceeds to the processing of S328 in the case of x> x _2, if not x> x ₂ in the S3
Proceed to step 30.

[0350] Further, the DSP 80 performs the processing in steps S326 and S32.
8, S330 process of, while changing the values of x ₂ and the variable a _3, b ₃ components, repeated until the value x _N-1 and variables a _N, b _N of the component. In step S332, the DSP 80 finally multiplies the component value x by the variable A, and further adds the value of the variable B to obtain output data y.

According to the image data processing systems 8 and 9 shown as the eighth and ninth embodiments of the present invention,
Conventionally, the input method by GUI which was not considered,
Data indicating characteristics of the non-linear processing can be input. According to the image data processing system 9 shown as the ninth embodiment of the present invention, the DSP 80 (parallel processors 2 to 6) is used instead of the image data processing device 7 (FIG. 34).
Is used for the components of the color signal,
In addition to the non-linear processing, other processing such as special effects can be collectively performed by software. Also, the eighth aspect of the present invention.
According to the image data processing systems 8 and 9 shown as the ninth embodiment, output data obtained as a processing result can be immediately confirmed, and the nonlinear characteristics can be optimized while confirming the output image. .

Tenth Embodiment The chroma key processing is indispensable in a system for adding a special effect to an image such as a TV, a camera, a video, an image editing device, and a special effect device irrespective of an application for a consumer or a broadcasting station. It has been. For example, when an image of a person standing in front of a building is created by chroma-keying an image of a person standing in front of a blue wall and an image of a building to create an image in which a person is standing in front of a building, The image of the building is called a background image (base image), and the blue portion outside the person is called a background color (key color or background color). That is, the pixels of the color designated as the background color in the foreground image are replaced with the pixels of the background image by the chroma key processing.

FIG. 41 is a diagram showing a configuration example of a chroma key device for performing analog processing. FIG. 42 is a diagram illustrating a configuration example of a chroma key device that performs digital processing. Generally, a chroma key device that performs chroma key processing on an image in an analog or digital manner is shown in FIG.
As shown in FIG. 42, a configuration in which a number of multipliers, adders and the like are connected is employed.

However, if chroma key processing is performed by the analog chroma key device shown in FIG. 41, the quality of the processed image will be degraded. The digital chroma key device shown in FIG. 42 has a large circuit scale and can specify only a certain color (for example, blue) as a background image.

An image data processing system 10 described below as a tenth embodiment of the present invention has been made in order to solve the above-described problems of the general chroma key apparatus, and has been described in detail. Is configured to prevent deterioration of the image, specify an arbitrary color as the background image, and specify the content of the chroma key processing by the GUI.

Structure of Image Data Processing System 10 FIG. 43 is a diagram showing the structure of the tenth embodiment (image data processing system 10) of the present invention. Note that among the components of the image data processing system 10 shown in FIG. 43, the same components as those of the image data processing systems 8 and 9 shown in FIGS. It is. FIG. 44 is a diagram showing data input or output to the DSP 80 shown in FIG.

As shown in FIG. 43, the image data processing system 10 includes an input device 70, a personal computer 7
2. Image monitor 76, DSP 80, foreground image source 78
₁ and a background image source 78 ₂ . That is, the image source 74 of the image data processing system 9 (FIG. 37) is changed to the foreground image source 78 ₁ and the background image source 7.
8 ₂ take the configuration substituted with, as shown in FIG. 44, DS
In P80, as input data 1, foreground image source 78
Foreground image data to be subjected to chroma key processing is input from _1, and background image data is similarly input from a background image source 78 ₂ as input data 2.

Components of the image data processing system 10 The following describes operations that are different from those of the image data processing systems 8 and 9 of the components of the image data processing system 10.

Input device 70 FIG. 45 shows a GUI image for setting a background color of chroma key processing displayed on a monitor for computer (or image monitor 76) by personal computer 72 of image data processing system 10 (FIG. 43). FIG. The input device 70 is connected to the image data processing systems 8 and 9 (FIG. 34,
As in the case of FIG. 37), an image portion including a keyboard, a tablet, a trackball, an accu point, and the like, accepting a user's setting operation on the GUI image shown in FIG. 45, and replacing the foreground image of the chroma key processing with the background image Is output to the personal computer 72.

The foreground image source 78 ₁ and the background image source 7
8 ₂ foreground image source 78 _1, the background image source 78 _2, like the image source 74 in the image data processing system 9, a video camera or a VTR device. The foreground image source 78 ₁ outputs a background image and foreground image data superimposed on the background image to the DSP 80. The background image source 78 ₂ outputs a foreground image and background image data superimposed on the foreground image to the DSP 80.

The personal computer 72 displays, for example, a color image (Cr-Cb space) of the background color shown in FIG. 45, and displays a GUI image used for setting the background color of the chroma key processing. The DSP 80 is controlled based on the background color data input via the input device 70.

[0362] Background color setting GUI image and its use
In the following, the contents of the background color setting GUI image shown in FIG. 45 and the background color setting processing by the personal computer 72 will be described. The range a of the background color setting GUI image indicates a color (Cr-Cb) space. For example, the horizontal (x) axis of the range a indicates the chroma signal Cr, the vertical (y) axis indicates the chroma signal Cb, and x The coordinates of the axis and the y-axis correspond to the intensity (value) of the chroma signals Cb and Cr, respectively. further,
Inside the rectangle of the range a, the colors represented by the chroma signals Cb and Cr having values corresponding to the respective coordinates of the x-axis and the y-axis, that is, the range a of the background color setting GUI image,
All the foreground image source 78 ₁ color included in the foreground image data is output to the image monitor 76 (colors that can be displayed on the image monitor 76) is displayed gradations.

For example, the user moves the cursor using the mouse of the input device 70 within the range a of the GUI image for setting the background color displayed on the monitor of the computer of the personal computer 72, and clicks the mouse. Move the cursor while holding down the button (drag)
Then, the personal computer 72 first pressed the mouse button within the range a in accordance with the user's operation on the screen of the computer monitor as shown in FIG. 45 according to the predetermined setting for the mouse. An arrow (drag) and an ellipse b corresponding to the position to the dragged position are displayed.

When the user releases the mouse button, the personal computer 72 releases the mouse button (x ₂ , y ₂ ) centering on the first click position (x ₁ , y ₁ ). Is defined as a point on the circumference, an ellipse b (graphic) having two axes parallel to the x-axis and the y-axis is determined, and all colors included in the range of the determined ellipse b (graphic) are set as background colors of chroma key processing. (Key color).

Alternatively, the personal computer 72
According to other settings for the mouse, for example, the position (x ₁ , y ₁ ) where the mouse is clicked _first and the position (x ₂ , y ₂ ) where the mouse button is released are set as diagonal lines, and each side is the x-axis. Alternatively, a rectangle ((graphic; not shown)) parallel to the y-axis is determined, and all colors included in the range of the determined rectangle (graphic) are set as background colors of the chroma key processing.

[0366] Further, the personal computer 72 includes:
When the user clicks, for example, the Make button in the range c of the background color setting GUI screen with the mouse, the personal computer 72 outputs the chroma signals Cb and Cr corresponding to all the colors included in the determined figure range. The range of values is calculated, and among the pixels of the foreground image data input from the foreground image source 78 ₁ , the pixels whose values of the chroma signals Cb and Cr fall within the range of the calculated chroma signals Cb and Cr are set to the background. for replaced by a picture, only the extent appropriate, to generate a software for processing to superimpose to fit the background image data inputted from the background image source 78 ₂ is set to DSP 80.

Example of Program for DSP 80 Hereinafter, with further reference to FIG. 46, the processing contents of the program for DSP 80 generated by the personal computer 72 in response to the operation on the background color setting GUI screen by the user will be described. An example in which the range of the ellipse b indicated by 45 is set as the background color will be described. FIG. 46 is a diagram exemplifying processing of a chroma key processing program for the DSP 80 generated by the personal computer 72 of the image data processing system 10 (FIG. 43).

As shown in FIG. 46, the personal computer 72 sets the chroma signal C of each pixel of the foreground image data.
It is determined whether the coordinates (x, y) in the color (Cr-Cb) space corresponding to b, Cr are inside the ellipse b (FIG. 45), and the color (Cr-Cb) of the chroma signals Cb, Cr is determined. Cb) For the pixels of the foreground image data whose coordinates (x, y) in the space are inside the ellipse b, generate a program that causes the DSP 80 to perform the process of replacing the pixels of the background image data at the corresponding positions. . Note that the generation of the program described here includes, for example, a process of rewriting only the parameters in the template program.

[0369] processing of the DSP80 First, explaining the contents of processing of the DSP80 schematically. D
SP80 element processor 30 (FIG. 32, etc.) respectively accepts pixel data of the background image and foreground pixels included in one horizontal scanning period one each, variable T _1,
To T _2, the chroma signal Cb of the pixel data of the foreground image, Cr
Numerical value (x−) obtained by subtracting the center coordinates (x ₁ , y ₁ ) of the ellipse b in the color space from the coordinates (x, y) in the color space
x ₁ ) and (y−y ₁ ) [T ₁ = x−x ₁ , T
₂ = y-y ₁ ].

Next, the element processor 30 squares the values of the variables T ₁ and T ₂ calculated by the above processing, and substitutes the square values for the variables T ₁ and T ₂ [T ₁ = (x ₂ −
x ₁ ) ² , T ₂ = (y ₂ −y ₁ ) ² ]. Next, the variable T ₃
Is substituted for the added value of the variable T ₁ and the variable T ₂ (T ₃
= T ₁ + T ₂ ).

Next, the element processor 30 compares the variable T ₃ with the numerical value T _4, and determines that the variable T ₃ is a constant T ₄ [T ₄ = (x ₂ −x ₁ ) that does not depend on the data of the image mismatch. ² × (y ₂
−y ₁ ) ² ], it is determined that the coordinates of the chroma signals Cb and Cr of the pixel data are inside the ellipse b, and the process proceeds to the following process B, where the variable T ₃ is equal to or larger than the constant T _4. In this case, it is determined that the coordinates of the chroma signals Cb and Cr of the pixel data are outside the ellipse b, and the process proceeds to the following process A.

In the process A, the element processor 30
Output processing is performed on the input pixel data of the background image. In the process B, the element processor 30 outputs pixel data of the foreground image instead of the input pixel data of the background image.

The DSP 80 calculates the value [(x ₂ −x ₁ ) ² × (y ₂ −y ₁ ) ₂ ] × from the calculated value of the variable T _3.
0.8 is subtracted from 0 to [(x ₂ −x ₁ ) ² × (y ₂ −
y ₁ ) ₂ ] × 0.2, and multiply the variable T ₃ by a numerical value 5 / [(x ₂ −x ₁ ) ² × (y ₂ −y ₁ ) ₂ ] to obtain a new variable T ₃ , the variable T ₃ itself is used as the chroma key data, and the element processor 30 calculates the product of the pixel data of the foreground image and the variable T ₃ (pixel data of the foreground image × T ₃ ), the pixel data of the background image, Variable T ₃
The pixel data obtained by adding the multiplication value of the value obtained by subtracting 1 from 1 may be output to smooth the switching between the background image and the foreground image. This is a technique called a soft key.

With further reference to FIG. 47, the DSP 80 based on the program generated by the personal computer 72
Is specifically described. FIG. 47 shows a personal computer 72 of the image data processing system 10 (FIG. 43).
32 generates an element processor 30 for the DSP 80 (FIG. 32).
FIG. 7 is a flowchart illustrating an example of the contents of a chroma key processing program executed by the program of FIG.

In step S320, each element processor 30 of the DSP 80 determines whether the background image data Yf, C
rf and Cb-f, and foreground image data Yf, Cr-f and Cb-f are input to the SAM.
Enter in the section.

In step S321, each element processor 30 secures areas 1 to 5 in the data memory unit.

[0377] In step S322, each element processor 30 outputs the Yf, Cr of the foreground image from the input SAM unit.
-F and Cb-f are stored in the data memory area 1
Transfer to

[0378] In step S324, each element processor 30 sends Yf, Cr of the background image from the input SAM unit.
-F and Cb-f are transferred to the data area 2.

[0379] In step S325, ALU array unit of the processor elements 30, the Cr-f data of the foreground image area of the data memory 1, by subtracting the numerical value x ₁ which is input by the GUI, the area of the data memory unit 3 Is stored (substituted).

[0380] In step S326, the ALU array unit of each element processor 30 stores the Cb-
subtracting the numerical value y ₁ input by the GUI from the f data and stores (substituted) in the area 4 of the data memory unit.

In step S327, the ALU array section of each element processor 30 stores the area 3 of the data memory section.
Is squared and stored (substituted) in the area 3 of the data memory unit.

In step S328, the ALU array section of each element processor 30 stores data in area 4 of the data memory section.
Is squared and stored (substituted) in the area 4 of the data memory section.

In step S329, the ALU array section of each element processor 30 stores data in area 3 of the data memory section.
And the data in the area 3 are added and stored (substituted) in the area 5 of the data memory unit.

[0384] In step S330, the ALU array section of each element processor 30 stores the area 5 of the data memory section.
And a constant T ₄ [T ₄ = (x ₂ −x ₁ ) ² × (y
_2- y ₁ ) ² ], and if the data in the area 5 of the data memory section is less than the constant T ₄ , the process proceeds to S 331,
Data area 5 of the data memory unit proceeds to the processing of long constant T ₄ or S332.

At step S331, each element processor 30 outputs the data of the area 2 of the data memory unit via the output SAM unit.

At step S332, each element processor 30 outputs the data of the area 1 of the data memory unit via the output SAM unit.

Operation of Image Data Processing System 10 The operation of the image data processing system 10 shown in FIG. 43 will be described below with reference to FIG. FIG. 48 is a flowchart showing the chroma key processing by the image data processing system 10 (FIG. 43).

As shown in FIG. 48, in step S340, the personal computer 72 displays the background color setting GUI image (FIG. 45) on the monitor of the computer. In step S342, the user designates the range of the color to be set as the background color by using the mouse of the input device 70 with respect to the display of the background color setting GUI image.

In step S344, when the user presses the Make button of the background color setting GUI image with the mouse or the like of the input device 70, the personal computer 72 displays all the colors included in the range specified by the graphic on the background. And a program for superimposing the background image so as to fit the background color portion of the foreground image (FIGS. 46 and 4).
7) is generated. In step S346, the personal computer 72 transmits the generated program to the DSP 8
Download to 0. The DSP 80 executes the downloaded program, performs the real-time image processing shown in FIGS. 46 and 47, and displays the chroma key processing result on the image monitor 76.

As described above, according to the image data processing system 10 of the present invention, the chroma key processing is performed by a small, highly versatile and software programmable SIM.
It can be realized by a D-controlled linear array type multi-parallel processor, and the background color of the chroma key can be easily set by GUI operation. Further, the image data processing system 10 according to the present invention performs the chroma key processing by software, so that an arbitrary background color can be set, and the change is easy.

In the tenth embodiment, the case where the elliptical or rectangular range of the color space is set as the background color has been described. However, other figures, for example, within the range of a circle and a square, or The outside of the range may be set as the background color. In the tenth embodiment, the color space is represented by the chroma signals Cb and Cr. However, the color space is represented by another signal, for example, an RGB signal, and is input from the foreground image source 78 ₁ and the background image source 78 _2. The image data processing system 10 may be configured to perform chroma key processing on the RGB signals of the image data to be processed. The method of setting the background color for chroma key processing in the tenth embodiment is described in SIM
The present invention can be applied not only to the D-controlled linear array type multi-parallel processor but also to other types of DSPs.

Eleventh Embodiment Hereinafter, an eleventh embodiment of the present invention will be described.

[0393] edge enhancement processing below with reference to FIGS. 49 and 50, illustrating the edge enhancement process. FIG. 49 is a first diagram showing an outline emphasis process by the image data processing system 9 (FIG. 37) shown as the eleventh embodiment. FIGS. 50A to 50E show an image data processing system 9 (FIG. 37) shown as the eleventh embodiment.
FIG. 9 is a second diagram illustrating the outline emphasis processing by the first embodiment. As shown in FIG. 49, the level enhancement (level d
epend) processing, filtering processing, crispening (cli
spining) processing, delay processing, and addition processing. Actually, the luminance signal Y
And a conversion process [FIG. 50 (A)] for the contour of one of the chroma signals Cb and Cr.

Level Dependent Processing In the contour emphasizing processing, the level dependent processing shown in FIG. 50 (B) is performed in the same manner as the color correction (γ correction) processing shown in the eighth embodiment, and an external video equipment such as a VTR device. Of the image data VIN input from the image data is nonlinearly converted, and a component for enhancing the contour of the image of the object in the image data is emphasized.

Filtering Process In the filtering process shown in FIG. 50C, a high-pass filter (HPF; actually, an FIR filter is used, which passes only high frequency components of level-depended image data, see the twelfth embodiment). , The contour of the image of the object in the image data is detected, and contour data indicating the contour of the detected image is generated.

Crispening Process The crispening process shown in FIG. 50 (D) non-linearly transforms the contour data to prevent the contour after being synthesized with the original image data from becoming too conspicuous.

Delay Processing In the delay processing, the original image data is given a time delay by the time required for each of the above processing, and the timing of the contour data subjected to the crisping processing and the timing of the original image data are adjusted.

Addition Processing The addition processing shown in FIG. 50 (E) adds the delayed original image data and the crispening processed outline data to generate image data in which the outline of the object image is enhanced.

The eleventh embodiment of the present invention relates to, for example, GU
The operation of the image data processing system 9 shown in FIG. 37 is modified so that the outline enhancement processing can be performed by simply setting the processing characteristics of each of the above-described processings using I.

Each of the image data processing systems 9 (FIG. 37)
The operation of each component of the image data processing system 9 shown as the eleventh embodiment will be described below.

The DSP 80 executes the program created by the personal computer 72, converts the image data VIN with the function S, generates the image data S, performs the level dependent process of the image data S with the function S ′, and executes the image data S ′.
, Generation of image data S ", filtering of image data S" and generation of image data S "" by a function S "", delay processing of image data VIN, and,
An addition process of the delayed image data VIN and the image data S ″ ′ is performed, an outline enhancement process is performed, and the image data obtained as a result of the process is displayed on the image monitor 76.

[0402] Personal computer 72 Referring to Figure 51-52, the operation of the personal computer 72.

Setting of Conversion Function FIG. 51 shows that the luminance signal Y and the chrominance signal C in the contour emphasizing process by the image data processing system 9 (FIG. 37).
G used to set a function that emphasizes b and Cr
FIG. 3 is a diagram illustrating a UI image. Personal computer 72
5 according to the operation of the user through the input device 70.
The function setting GUI image shown in FIG. 1 is displayed on the monitor.

[0404] The bars in the window in the GUI image for function setting are the luminance signal Y and the chroma signal Cb, respectively.
The function S corresponds to the coefficients a to c by which Cr is multiplied.
Defined as 0. That is, the coefficients a to c set by the function setting GUI correspond to the degree of which one of the luminance signal Y and the chroma signals Cb and Cr of the image data is to be emphasized to perform the outline emphasis processing.

[0405]

S = aY + bCb + cCr (10)

The user drags each of the three bars in the window with the mouse or the like of the input device 70 in accordance with the display of the function setting GUI, and sets the coefficients a to c in the window.
Change the length of the corresponding bar. The personal computer 72 receives the coefficients a to c corresponding to the length of the bar in the window after the change, creates a program of the DSP 80 for converting the image source 74 by the function S, and downloads the program to the DSP 80. The DSP 80 executes the downloaded program, and executes the image source 74
The image data S is generated by converting the luminance signal Y and the chroma signals Cb and Cr of the image data input from the image processing unit by using a function S, and is subjected to the contour emphasis processing.

Setting of Level Dependent Processing Characteristics FIGS. 52A to 52D show a GUI used for setting characteristics of nonlinear conversion processing in level dependent processing or crispening processing in the outline enhancement processing by the image data processing system 9. It is a figure showing a screen. The personal computer 72 displays a GUI image for setting the characteristics of the level dependent process shown in FIGS. 52A to 52C on the monitor in accordance with the operation of the user via the input device 70.

[0408] The level-dependent processing is a kind of non-linear conversion processing as described above.
2 shows the conversion characteristic of the level dependent process in FIG.
As shown in (D), a graph in which the horizontal (x) axis is the value of the pixel data of the image data S and the vertical (y) axis is the value of the pixel data of the image data S ′ after the level dependent process is performed. Express in a format.

The user sets G for setting the level dependent characteristic.
Add button in the bottom window of the UI image, Move
By pressing the button or the Delete button with the mouse or the like of the input device 70, an Add mode, a Move mode, or a Del mode shown in FIGS.
One of the ETE modes is always selected, and a passing point (point) of the curve indicating the characteristic of the level dependent processing is added, moved, or deleted, and the curve of the graph is changed to indicate the desired characteristic.

Further, when the user instructs the personal computer 72 using the input device 70 to end the characteristic setting of the level dependent processing, the personal computer 7
2 receives the curve of the graph after the change shown in FIG. 52 (D) and extracts a function S ′ corresponding to the received curve.

Setting of Filtering Characteristics FIGS. 53A to 53C are views showing GUI screens used for setting the characteristics of the filtering process in the outline emphasizing process by the image data processing system 9. As described above, the contour detection process is realized by performing a filtering process on the image data S ′.
As shown in FIGS. 53 (A) to 53 (C), a frequency response is represented in a graph format in which the horizontal (x) axis is frequency and the vertical (y) axis is attenuation (gain). In addition, FIG.
In the graph shown in (C), the upper part of the vertical axis indicates the pass frequency band, and the lower part of the vertical axis indicates the stop frequency band.

The user presses the Add button, Move button, or Delete button in the lower window of the GUI image for setting the characteristics of the filtering process with the mouse of the input device 70, as in the case of setting the level dependent characteristics. As a result, the Add mode, Move mode, or Delete mode shown in FIGS.
One of the modes is always selected, and the curve points of the graph showing the characteristics of the filtering process are added, moved or deleted to change the curve of the graph to show the desired characteristics.

Further, when the user instructs the personal computer 72 using the input device 70 to end the characteristic setting of the level dependent processing, the personal computer 7
2 accepts the curve of the graph after the change and extracts a frequency response S "corresponding to the accepted curve.

[0414] chestnut spinning processing characteristics for setting the personal computer 72, in response to user's operation via the input device 70, FIG. 52 (A) ~ GUI image for setting characteristics of chestnut spinning process shown in (C) Is displayed on the monitor.

The crispening process is a kind of non-linear conversion process similar to the level dependent process as described above, and the personal computer 72 shows the conversion characteristics of the crispening process in FIGS. 52 (A) to 52 (D). like,
The horizontal (x) axis is the pixel data value of the image data S ″,
The vertical (y) axis is represented in a graph format in which pixel data values of the image data S ″ ′ after the crispening process are set.

[0416] The user presses the Add button, Move button, or Delete button in the lower window of the GUI image for setting the crispening characteristic having substantially the same contents as the level dependent characteristic setting with the mouse of the input device 70, and the like. A shown in each of 52 (A) to (C)
Always select one of the dd mode, Move mode and Delete mode, add, move or delete the passing points of the curve of the graph showing the characteristics of the crispening process, and change the curve of the graph to show the desired characteristics. I do.

Further, when the user instructs the personal computer 72 using the input device 70 to end the setting of the characteristics of the crispening process, the personal computer 7
2 receives the curve of the graph after the change shown in FIG. 52 (D) and extracts a function S ″ ′ corresponding to the received curve.

The user who creates the program for the DSP 80 can use the program shown in FIGS. 52 (A) to 52 (D) and FIGS.
When the setting of the characteristics of each process for the characteristic setting GUI image shown in FIG.
2 is a DSP that determines the characteristics of each process according to the operation of the user via the input device 70 and performs each process with the determined characteristics.
Create a program or parameter file for 80.

That is, the personal computer 72
The image data S is subjected to non-linear conversion processing (level-dependent processing) using a function S ′ corresponding to the curve of the graph indicating the level-dependent processing shown in FIG.
The image data S ′ is filtered with the frequency response S ″ corresponding to the curve of the graph after the change shown in FIG.
The image data S "is subjected to a non-linear conversion process (crispinning process) by a function S"'corresponding to the curve of the graph indicating the crispening process shown in (D), and further, the delayed original image data VIN and image data S DSP that adds "'
The program 80 is generated and downloaded to the DSP 80.

That is, the personal computer 72
Based on the setting of the characteristics of each process shown in FIG. 49, a program for performing these processes with the set characteristics is generated, and D is generated.
Set to SP80. However, in this program, since the delay processing of the original image data can be realized by holding the original image data VIN until the execution of the addition processing, it is particularly necessary to create the delay processing as an independent program module. There is no.

The contents of the program of the DSP 80 are described below.
0 will be described.

[0422] Creating a transformation function S First, DSP 80; the processor elements 30 of the (linear array type of SIMD control multi-parallel processor parallel processor 6 and the like shown in FIG. 32) is, in the data memory 23, the input SAM unit 22 An area (work area) for storing the luminance signal Y, the chroma signals Cb and Cr, the variable S, and the data of the intermediate result of the calculation by the ALU array unit 24 is secured.

Next, the ALU array unit 24 of each element processor 30 of the DSP 80 (parallel processor 6) multiplies the luminance signal Y stored in the data memory unit 23 by the coefficient a, and stores the multiplication result in a variable S. Substitution (S = aY). Further, the ALU array unit 24 includes the chroma signal Cb and the coefficient b.
, The result of the multiplication is added to the variable S, and the result is substituted for the variable S (S = aY + bCb). Further, the ALU array unit 24 multiplies the chroma signal Cr by the coefficient c, adds the multiplication result to a variable S, and substitutes the variable S for the variable S (S = a
Y + bCb + cCb).

Level Dependent Processing and Crispening
Since the processing level dependent processing and the crispening processing are the same in principle, the level dependent processing in the case where the function S ′ is as shown in Table 1 below will be described as an example.

[0425]

[Table 1]

If the function S ′ is as shown in Table 1, the DSP
First, the element processor 30 of the 80 (parallel processor 6) approximates the function S ′ by a linear function for each of the regions 1 to 3. Next, the DSP 80 (parallel processor 6)
Are areas A and B for storing coefficients in the data memory unit 23.
And secure a work area.

Next, the ALU array unit 24 of each element processor 30 of the DSP 80 (parallel processor 6) determines whether or not the value of the variable S is larger than the numerical value 100. , B to the coefficient a
₃ and b ₃ are stored.
The coefficients a ₁ and b ₁ are stored in B, respectively.

Next, the ALU array unit 24 of each element processor 30 determines whether or not the value of the pixel data is larger than the numerical value 150.
The coefficients a ₂ and b ₂ are stored in B, respectively, and when the value is 150 or less, the values of the coefficients stored in the areas A and B are left as they are.

By the above processing, each element processor 30
Are stored in the areas A and B according to which area in Table 1 the pixel data input to. The ALU array unit 24 of the element processor 30 further performs the operation of the function S ′ based on the values of the coefficients stored in the areas A and B and the value x of the pixel data.

Calculation of Filtering Coefficient The personal computer 72 calculates the filtering coefficient based on the parameters indicating the filtering characteristics (FIGS. 53A to 53C).
Calculate the filter coefficient of the FIR filter.

Horizontal Filtering When horizontal filtering is realized by a 16-tap FIR filter, each element processor 30 of the DSP 80 (parallel processor 6) converts the data converted by the function S ′ into 7 taps in advance. The values are shifted and stored in the front (left in FIG. 32) element processor 30, and are sequentially multiplied by the filter coefficient calculated by the personal computer 72 from the rear (right in FIG. 32) element processor 30. Right element processor 30
Is repeated 16 times.

Vertical Filtering Next, vertical filtering is performed by using a 16-tap F
In the case of realizing with an IR filter, first,
Each of the element processors 30 of the (parallel processor 6) stores the data subjected to the horizontal filtering process as described above in the data memory unit 23 in advance. When accessing the pixel data in the data memory unit 23, the ALU array unit 24 of each element processor 30 rotates the address and uses the pixel data of the latest input line to determine the pixel data of the oldest input line. Write to the next address of the pixel data, and as shown in Table 2 below, in the program processing, as if the pixel data of the newly input line is recorded from the fixed address in order from the fixed address, it is as if recorded at the lower numbered address. To process.

[0433]

[Table 2] Memory: Actually written: On the program after n cycles: Address: Pixel data line: Line: Number of number: n = 16; n = 17; n = 18: ====== ======================== 0-15: 1, 17 lines: 1 line; 2 lines; 3 lines: 16-31: 2, 18 lines : 2 lines; 3 lines; 4 lines: 32-47: 3 lines: 3 lines; 4 lines; 5 lines: 48-63: 4 lines: 4 lines; 5 lines; 6 lines: 64-79: 5 lines: 5 Line; 6 lines; 7 lines: 80-95: 6 lines: 6 lines; 7 lines; 8 lines: 96-111: 7 lines: 7 lines; 8 lines; 9 lines: 112-127: 8 lines: 8 lines; 9 lines; 10 lines: 128-143: 9 lines: 9 lines; 10 lines; 11 lines: 144-159: 10 lines: 10 lines; 11 lines; 12 lines : 160-175: 11 lines: 11 lines; 12 lines; 13 lines: 176-191: 12 lines: 12 lines; 13 lines; 14 lines: 192-207: 13 lines: 13 lines; 14 lines; 15 lines: 208 -223: 14 lines: 14 lines; 15 lines; 16 lines: 224-239: 15 lines: 15 lines; 16 lines; 17 lines: 240-255: 16 lines: 16 lines; 17 lines; 18th line: ↑ ↑ ↑ Address rotation 0 -16 -32… (2)

By rotating the addresses as shown in Table 2, the addresses 0 and 15 of the data memory unit 23 of each element processor 30 are always set to FI
It is treated as the address of the end pixel data in the 16 taps of the R filter, and the pixel data at addresses 16 and 32 is always treated as the pixel data next to the shortest pixel data.

Therefore, the ALU array section 24 of the element processor 30 always stores the end address (address 0, 1).
The filtering process in the vertical direction can be performed by multiplying and adding the filter coefficients in order from 5) the pixel data.

If the memory capacity of the data memory unit 23 of the element processor 30 is not enough to store all of the pixel data for 16 taps, the pixel data for 16 taps is divided into two for each of 8 taps. Similarly, by rotating the address, the pixel data of the most recently input line is written to the next address of the pixel data of the oldest input line, and the program is executed as shown in Tables 3 and 4 below. In processing, pixel data of a newly input line is processed as if they were recorded at lower addresses in order from a fixed address.

The first block of the two blocks of pixel data divided and stored in this manner is 16 bits.
The arithmetic processing of the ninth to sixteenth taps of the FIR filter having the tap configuration is performed, and the arithmetic result and the oldest pixel data are transferred to the second pixel data block. Similarly,
For the block of the second pixel data, the calculation processing from the first tap to the eighth tap of the 16-tap FIR filter is performed, and the calculation result and the calculation result for the first pixel data block are added. To obtain the final filtering result. Even when the pixel data is divided into more blocks, the calculation processing of the FIR filter can be performed in exactly the same manner.

[0438]

[Table 3] First block memory: Actually written: On the program after n cycles: Address: Line of pixel data: Line: Number of number: n = 16; n = 17; n = 18: == ============================ 0-15: 1,9 lines: 9 lines; 10 lines; 11 lines: 16-31: 2,10 lines: 10 lines; 11 lines; 12 lines: 32-47: 3 lines: 11 lines; 12 lines; 13 lines: 48-63: 4 lines: 12 lines; 13 lines; 14 lines: 64-79: 5 lines: 13 lines; 14 lines; 15 lines; 80-95: 6 lines: 14 lines; 15 lines; 16 lines; 96-111: 7 lines: 15 lines; 16 lines; 17 lines; 112-127: 8 lines : 16 lines; 17 lines; 18 lines; ↑ ↑ ↑ Address rotation 0 -16 -32… (3)

[0439]

[Table 4] Second block memory: Actually written: On the program after n cycles: Address: Line of pixel data: Line: Number of number: n = 16; n = 17; n = 18: == ============================ 0-15: 1,17 lines: 1 line; 2 lines; 3 lines: 16-31: 2,18 lines: 2 lines; 3 lines; 4 lines: 32-47: 3 lines: 3 lines; 4 lines; 5 lines: 48-63: 4 lines: 4 lines; 5 lines; 6 lines: 64-79: 5 lines: 5 lines; 6 lines; 7 lines; 80-95: 6 lines: 6 lines; 7 lines; 8 lines; 96-111: 7 lines: 7 lines; 8 lines; 9 lines; 112-127: 8 lines : 8 lines; 9 lines; 10 lines; ↑ ↑ ↑ Address rotation 0 -16 -32… (4)

[0440] images data processing cis in the eleventh embodiment
The operation of the image data processing system 9 (FIG. 37) in the eleventh embodiment will be described below with reference to FIG. FIG. 54 is a flowchart showing the outline emphasis processing by the image data processing system 9 shown as the eleventh embodiment.

As shown in FIG. 54, in step S350, the user operates the personal computer 72 of the image data processing system 9 to display a characteristic setting GUI image [FIG. 52 (A)-(D), FIG. 53 (A) ~
(C)] to set the functions S, S ', S "' and set the filtering characteristics. The personal computer 72 sets the functions S, S ', Accept S "'and filtering characteristics.

[0442] In step S352, the personal computer 72 performs extraction processing of the functions S, S ', S "' and generation of filter coefficients for realizing the filtering characteristic. In step S354, the personal computer 72 performs the extraction. A program of the DSP 80 (linear array type multi-parallel processor) for converting the image data with the functions S, S ′, S ″ ′ and filtering the image data using the calculated filter coefficients is generated. In step S356, the personal computer 72
Downloads the generated program to the DSP 80. The DSP 80 executes the downloaded program, and executes the image data VI input from the image source 74.
The outline emphasis processing is performed on N, and the image is displayed on the image monitor 76.

[0443] If the contour enhancement processing result displayed on the image monitor 76 is unnatural, the user can proceed to S350 to S356 until satisfactory image data is obtained.
By searching for the optimal processing characteristics,
Image data in which a contour is naturally enhanced can be generated.

As described above, according to the operation of the image data processing system 9 in the eleventh embodiment, the outline emphasis processing on the image data is performed by software using the DSP 80 (SIMD-controlled linear array type multi-parallel processor). Therefore, the device scale of the contour enhancement processing device can be reduced. Further, according to the operation of the image data processing system 9 in the eleventh embodiment, it is possible to easily change the frequency response of the filtering process in the contour emphasis process, or the characteristics such as the degree of the contour emphasis by the non-linear conversion, by the GUI. And the processing result can be immediately observed.

The method of setting the processing characteristics of the contour enhancement processing in the eleventh embodiment is applicable not only to the SIMD-controlled linear array type multi-parallel processor but also to other types of DSPs.

Twelfth Embodiment Hereinafter, a twelfth embodiment of the present invention will be described. The twelfth embodiment of the present invention focuses on the filtering process by the FIR filter among the processes included in the outline emphasizing process of the image data processing system 9 (FIG. 37) shown as the eleventh embodiment. It was made.

Filtering by FIR Filter Hereinafter, filtering by the FIR filter will be described with reference to FIGS. 55 and 56. FIG. 55 shows the first
The image data processing system 9 shown in FIG.
FIG. 7 is a diagram showing the content of horizontal filtering processing by an FIR filter performed using 7).

FIG. 56 is a diagram showing the contents of horizontal and vertical filtering processing by an FIR filter performed using the image data processing system 9 (FIG. 37) shown as the twelfth embodiment. In practice, the filtering process shown in FIG. 56 is often performed by separating the filtering process in the horizontal direction and the filtering process in the vertical direction.

As shown in FIGS. 55 and 56, the FIR
The filtering process by the filter includes a delay process D for one pixel, a delay process L for a horizontal scanning period, a multiplication process M of a filter coefficient and pixel data, and an addition process S of a multiplication result.

Each part of the image data processing system 9 (FIG. 37)
The operation of each component of the image data processing system 9 shown as the twelfth embodiment will be described below.

The DSP 80 executes the program created by the personal computer 72, performs a filtering process using an FIR filter corresponding to the contents shown in FIGS. 55 and 56, and displays the image data obtained as a result of the process on an image monitor. 76.

[0452] Personal computer 72 or less, with reference to FIGS. 57 and 58, the operation of the personal computer 72.

Setting of Filtering Characteristics FIGS. 57A to 57C are diagrams showing GUI screens used for setting the characteristics of the filtering process in the filtering process by the FIR filter by the image data processing system 9. In addition, FIG.
(C) of FIG. 53 shown in the description of the eleventh embodiment.
(A) to (C).

The personal computer 72 determines the characteristics of the filtering process using the FIR filter as shown in FIG.
As shown in (A) to (C), the horizontal (x) axis is represented by a frequency, and the vertical (y) axis is represented by a graph of a frequency response with an attenuation (gain). In the graphs shown in FIGS. 57 (A) to (C), the upper part of the vertical axis indicates the pass frequency band, and the lower part of the vertical axis indicates the stop frequency band.

The user clicks the Add button in the lower window of the GUI image for setting the characteristics of the filtering process,
ove button or Delete button to the input device 70
By pressing with the mouse of FIG.
(C) Always select any of the Add mode, Move mode, and Delete mode shown, and add, move, or delete the passing points of the curve of the graph indicating the characteristics of the filtering process so that the desired characteristics are indicated. Change the curve of the graph.

That is, in the Add mode, when the user clicks a desired point in the window of the GUI screen using the mouse or the like of the input device 70, the personal computer 72 displays the passing point of the graph. Is newly provided, the corresponding point in the curve of the graph is moved to the clicked point, and the shape of the curve of the graph is changed and displayed.

In the Move mode, when the user clicks and drags a desired point in the window of the GUI screen using the mouse or the like of the input device 70, the personal computer 72 The existing passing point closest to the point is moved according to the drag of the user, and the shape of the curve of the graph is changed and displayed.

[0458] In the Delete mode, the personal computer 72 allows the user to operate the input device 70.
When the user clicks a desired point in the window of the GUI screen using the mouse or the like, the personal computer 72
The existing passing point closest to the clicked point is deleted, and the shape of the curve of the graph is changed and displayed so that the passing points on both sides of the deleted passing point are connected by a straight line.

When the design user of the FIR filter completes the setting of the characteristics of the filtering process for the GUI images for setting the characteristics shown in FIGS. 57A to 57C, the personal computer 72 operates via the input device 70. The characteristic is determined in accordance with the operation of the user, and an FIR filter that performs a filtering process with the determined characteristic is designed by a filter design tool using a filter coefficient calculated from a parameter indicating the filtering characteristic.

[0460] The program creation personal computer 72 for the DSP 80 performs the filtering process using the designed FIR filter.
Create a program for That is, the personal computer 72 generates the image data V with the frequency response S ″ corresponding to the curves of the graphs after the change shown in FIGS.
A program for the DSP 80 for filtering the IN is generated and downloaded to the DSP 80.

The contents of the DSP 80 program generated by the personal computer 72 will now be described with reference to FIG. 58. FIG. 58 shows an FIR shown as a twelfth embodiment.
FIG. 38 is a diagram illustrating processing contents (S36, S37) of a program of the DSP 80 of the image data processing system 9 (FIG. 37) that performs a filtering process using a filter.

Calculation of Filtering Coefficient The personal computer 72 calculates the filtering coefficient based on the parameters indicating the filtering characteristics (FIGS. 57A to 57C).
Calculate the filter coefficient of the FIR filter.

Horizontal Filtering (S36) When horizontal filtering is realized by a 16-tap FIR filter, as shown in FIG. 58, step 360 of horizontal filtering (S36) is performed.
In (S360), each of the element processors 30 of the DSP 80 (for example, the parallel processor 6; FIG. 32) shifts the pixel data of the image data by 7 taps in advance to the element processor 30 in the front (left direction in FIG. 32). Remember.

In step S362, each element processor 30 of the DSP 80
Is multiplied by the calculated filter coefficient and pixel data. In step S364, each element processor 30 of the DSP 80 updates the multiplication result in S362 backward (FIG. 32).
Is transferred to the element processor 30 on the right. Note that the DSP 80 repeats the multiplication process and the transfer process of the multiplication result in S362 and S364 16 times.

When filtering in the vertical direction is realized by an FIR filter having a 16-tap configuration, in the filtering process in the vertical direction (S37), each element processor 30 of the DSP 80 (parallel processor 6) performs processing for 16 lines. The pixel data of the image data S ′ is stored in the data memory unit 23 in advance. Further, when accessing the pixel data in the data memory unit 23, the ALU array unit 24 of each element processor 30 uses the address by rotating the address, and uses the pixel data of the latest input line as the oldest input line. Write to the pixel data address of the line,
As shown in Table 5 below (same as Table 2 shown in the eleventh embodiment), in the program processing, pixel data of a newly input line is recorded at a lower numbered address in order from a fixed address, as if the pixel data was newly input. Treat as if

[0466]

[Table 5] Memory: Actually written: On the program after n cycles: Address: Line of pixel data: Line: Number of numbers: n = 16; n = 17; n = 18: ====== ======================== 0-15: 1, 17 lines: 1 line; 2 lines; 3 lines: 16-31: 2, 18 lines : 2 lines; 3 lines; 4 lines: 32-47: 3 lines: 3 lines; 4 lines; 5 lines: 48-63: 4 lines: 4 lines; 5 lines; 6 lines: 64-79: 5 lines: 5 Line; 6 lines; 7 lines: 80-95: 6 lines: 6 lines; 7 lines; 8 lines: 96-111: 7 lines: 7 lines; 8 lines; 9 lines: 112-127: 8 lines: 8 lines; 9 lines; 10 lines: 128-143: 9 lines: 9 lines; 10 lines; 11 lines: 144-159: 10 lines: 10 lines; 11 lines; 12 lines : 160-175: 11 lines: 11 lines; 12 lines; 13 lines: 176-191: 12 lines: 12 lines; 13 lines; 14 lines: 192-207: 13 lines: 13 lines; 14 lines; 15 lines: 208 -223: 14 lines: 14 lines; 15 lines; 16 lines: 224-239: 15 lines: 15 lines; 16 lines; 17 lines: 240-255: 16 lines: 16 lines; 17 lines; 18th line: ↑ ↑ ↑ Address rotation 0 -16 -32… (5)

By rotating the addresses as shown in Table 5, the virtual addresses 0 to 15 of the data memory unit 23 of each element processor 30 are always set at the end of the 16 taps of the FIR filter on the program. Virtual addresses 16 to 32
Pixel data is always treated as pixel data next to the end pixel data.

Accordingly, the ALU array section 24 of the element processor 30 can always perform the filtering process in the vertical direction by always multiplying and adding the filter coefficients in order from the pixel data at the virtual addresses 0 and 15.

If the memory capacity of the data memory unit 23 of the element processor 30 is not enough to store all the pixel data for 16 taps, the pixel data for 16 taps is divided into two for each of 8 taps. Similarly, by rotating the address, the pixel data of the most recently input line is written to the next address of the pixel data of the oldest input line, and the following Tables 6 and 7 (1st
As shown in Tables 3 and 4 shown in Example 1),
In the program processing, pixel data of a newly input line is processed as if recorded at lower addresses in order from a fixed address.

The first block of the two blocks of pixel data divided and stored in this way has 16 bits.
The arithmetic processing of the ninth to sixteenth taps of the FIR filter having the tap configuration is performed, and the arithmetic result and the oldest pixel data are transferred to the second pixel data block. Similarly,
For the block of the second pixel data, the calculation processing from the first tap to the eighth tap of the 16-tap FIR filter is performed, and the calculation result and the calculation result for the first pixel data block are added. To obtain the final filtering result. Even when the pixel data is divided into more blocks, the calculation processing of the FIR filter can be performed in exactly the same manner.

[0471]

[Table 6] First block memory: Actually written: On the program after n cycles: Address: Line of pixel data: Line: Number of number: n = 16; n = 17; n = 18: == ============================ 0-15: 1,9 lines: 9 lines; 10 lines; 11 lines: 16-31: 2,10 lines: 10 lines; 11 lines; 12 lines: 32-47: 3 lines: 11 lines; 12 lines; 13 lines: 48-63: 4 lines: 12 lines; 13 lines; 14 lines: 64-79: 5 lines: 13 lines; 14 lines; 15 lines; 80-95: 6 lines: 14 lines; 15 lines; 16 lines; 96-111: 7 lines: 15 lines; 16 lines; 17 lines; 112-127: 8 lines : 16 lines; 17 lines; 18 lines; ↑ ↑ ↑ Address rotation 0 -16 -32… (6)

[0472]

[Table 7] Second block memory: Actually written: On the program after n cycles: Address: Line of pixel data: Line: Number of: n = 16; n = 17; n = 18: == ============================ 0-15: 1,17 lines: 1 line; 2 lines; 3 lines: 16-31: 2,18 lines: 2 lines; 3 lines; 4 lines: 32-47: 3 lines: 3 lines; 4 lines; 5 lines: 48-63: 4 lines: 4 lines; 5 lines; 6 lines: 64-79: 5 lines: 5 lines; 6 lines; 7 lines; 80-95: 6 lines: 6 lines; 7 lines; 8 lines; 96-111: 7 lines: 7 lines; 8 lines; 9 lines; 112-127: 8 lines : 8 lines; 9 lines; 10 lines; ↑ ↑ ↑ Address rotation 0 -16 -32… (7)

Description of Filter Circuit The personal computer 72 creates a description in a hardware description language (HDL or the like) for realizing the circuit of the FIR filter designed as described above, and outputs it to a file or the like.

[0474] processing DSP 80 below, with reference to FIGS. 59 and 60, illustrating the process of DSP 80. FIGS. 59 and 60 are first and second flowcharts showing the processing of the DSP 80 in the twelfth embodiment.

[0475] First, as shown in Table 8 below, the DSP 80 stores image data in areas 1 to 3 in the data memory section.
16 and areas 17 to 21 used for the arithmetic processing. In addition, the areas 1 to 16 secured in the data memory unit
Are used as virtual areas 1 to 16 by address rotation for each line (element processor 30),
The address rotation is performed by a part of the control circuit that controls the data memory unit. In addition, areas 17 to
21 is not subject to address rotation.

[0476]

[Table 8] Data memory section: line n: line n + 1: line n + 2: line n + 3:... Area 1: virtual area 1: virtual area 2: virtual area 3: virtual area 4: ... area 2: Virtual area 2: Virtual area 3: Virtual area 4: Virtual area 5: ... Area 3: Virtual area 3: Virtual area 4: Virtual area 5: Virtual area 6: ... Area 4: Virtual area 4: Virtual area 5: Virtual area 6: virtual area 7: ... area 5: virtual area 5: virtual area 6: virtual area 7: virtual area 8: ... area 6: virtual area 6: virtual area 7: virtual area 8: virtual area 9: ... area 7: Virtual area 7: Virtual area 8: Virtual area 9: Virtual area 10: ... Area 8: Virtual area 8: Virtual area 9: Virtual area 10: Virtual area 11: ... Area 9: Virtual area 9: Virtual area 10: Virtual area 11: virtual area 12: ... area 10: virtual area 10: virtual area 11: virtual area 12: virtual area 13: ... area 11: virtual Area 11: virtual area 12: virtual area 13: virtual area 14: ... area 12: virtual area 12: virtual area 13: virtual area 14: virtual area 15: ... area 13: virtual area 13: virtual area 14: virtual area 15 : Virtual area 16: ... area 14: virtual area 14: virtual area 15: virtual area 16: virtual area 1 ... area 15: virtual area 15: virtual area 16: virtual area 1: virtual area 2: ... area 16: virtual Area 16: Virtual area 1: Virtual area 2: Virtual area 3: ... Area 17: Virtual area 17: Virtual area 17: Virtual area 17: Virtual area 17: ... Area 18: Virtual area 18: Virtual area 18: Virtual area 18 : Virtual area 18: ... area 19: virtual area 19: virtual area 19: virtual area 19: virtual area 19: ... area 20: virtual area 20: virtual area 20: virtual area 20: virtual area 20: ... area 21: virtual Area 21: Virtual area 21: Virtual area 21: Virtual area 21: ... (8)

That is, by first substituting the data from the input SAM unit into the virtual area 1 for each line, when a certain line is viewed, new data and virtual area 2 are also stored in the virtual area 1 of the data memory unit. Has the next new data,
.., The oldest data exists in the virtual area 16.

A 16-tap filter coefficient which is determined by the GUI operation and realizes the FIR filter is calculated on a personal computer. Hereinafter, the filter coefficients in the horizontal direction are referred to as filter coefficients h1, h2,. Filter coefficients are defined as filter coefficients v1, v2,.
Write 6.

As shown in FIG. 59, in step S365, the DSP 80 sets the input S
Data to be subjected to FIR filter processing is input to the AM unit.

[0480] In step S366, the input SAM section of each element processor 30 is stored in the area 17 of the data memory section.
Then, the data input in the process of S365 is transferred.

In step S367, each element processor 30 reads the data in the area 17 of the data memory section of the element processor 30 on the right and stores it in the area 17 of the data memory section. As a result of this processing, the data in the area 17 of the data memory unit is shifted to the left by one element processor 30. The element processor 30 repeats the processing of S367 seven times, and moves the data in the area 17 of the data memory unit to the left by seven element processors 30.

[0482] In step S368, the ALU array section of each element processor 30 stores the area 1 of the data memory section.
7 is multiplied by the horizontal filter coefficient h1 of the FIR filter and stored in the area 19 of the data memory section.

In step S369, each element processor 30 reads the data in the area 17 of the data memory section of the element processor 30 on the left and stores it in the area 17 of the data memory area. By the processing of S369, the data in the area 17 of the data memory unit of each element processor 30 is
The element processor 30 is shifted right by one.

In step S370, the ALU array section of each element processor 30 stores the area 1 of the data memory section.
7 is multiplied by the horizontal filter coefficient h2 of the FIR filter and stored in the area 18 of the data memory unit.

[0485] In step S371, the ALU array section of each element processor 30 stores the area 1 of the data memory section.
8 and the data in the area 19 of the data memory section are added and stored in the area 19 of the data memory section.

As shown in FIG. 60, in step S372, the data in the area 17 of the data memory section of the element processor 30 on the left is read and stored in the area 17 of the data memory area. By the processing of S369, the data in the area 17 of the data memory unit of each element processor 30 is shifted right by one element processor 30.

[0487] In step S373, the ALU array section of each element processor 30 stores the area 1 of the data memory section.
To the horizontal filter coefficient v of the FIR filter
The result is multiplied by 1 and stored in the area 20 of the data memory section.

[0488] In step S374, the ALU array unit of each element processor 30 multiplies the data in the virtual area i of the data memory unit by the filter coefficient vi in the vertical direction.
It is stored in the area 21 of the data memory unit. Step S37
In 5, the ALU array unit of each element processor 30 adds the data in the area 20 of the data memory unit and the data in the area 21 of the data memory unit and stores the result in the area 21 of the data memory unit. In addition, A of each element processor 30
The LU array unit repeats the processing of S374 and S375 15 times by changing the virtual area i and the filter coefficient vi from the virtual area 2 to the virtual area 16 and from the filter coefficient 2 to the filter coefficient 16, respectively.

In step S376, each element processor 30 transfers the data in the area 21 of the data memory unit to the output SAM unit.

[0490] In step S378, each element processor 30 outputs data from the output SAM unit.

The image data processing system in the twelfth embodiment
The operation of the image data processing system 9 (FIG. 37) in the twelfth embodiment will be described below with reference to FIG. FIG. 61 is a flowchart showing a filtering process by an FIR filter using the image data processing system 9 shown as the twelfth embodiment.

As shown in FIG. 61, in step S380, the user creates a characteristic setting GUI image (FIGS. 56A to 56C) displayed on the monitor by the personal computer 72 of the image data processing system 9. The personal computer 72 accepts the filtering characteristic according to the setting of the user by performing the operation for the filtering characteristic (frequency response S ″).

[0493] In step S382, the personal computer 72 extracts the parameters set in the processing in S380. In step S384, the personal computer 72 calculates a filter coefficient from the parameters extracted in S382.

[0494] In step S386, the personal computer 72 executes the DSP 80 (linear array type multi-parallel program) for performing the filtering process using the FIR filter designed as described above with reference to Figs.
Create a program. In step S388,
The personal computer 72 downloads the generated program to the DSP 80. The DSP 80 executes the downloaded program, performs a filtering process using a FIR filter on the image data VIN input from the image source 74, and displays the processing result on the image monitor 76. In step S390, the personal computer 72 generates and outputs a description of the designed filter circuit in a hardware description language.

If the result of the filtering process displayed on the image monitor 76 is not satisfactory,
The user operates S3 until satisfactory image data is obtained.
By repeating the processing of 80 to S388, it is possible to obtain the optimum filtering characteristics.

As described above, according to the operation of the image data processing system 9 in the twelfth embodiment, the filtering process for the image data is performed by the DSP 80 (SIM
Since it can be realized by software using a D-controlled linear array type multi-parallel processor, the size of a filtering processing device using an FIR filter can be reduced. Further, according to the filtering processing using the image data processing system 9 in the twelfth embodiment, the frequency response S ″ is arbitrarily set by the GUI,
The filtering process can be easily performed by making a change, and the processing result can be immediately viewed.
Therefore, the filtering process using the image data processing system 9 in the twelfth embodiment is very useful when performing a process for giving a special effect to image data.

The method of setting the processing characteristics of the filtering processing by the FIR filter in the twelfth embodiment can be applied to, for example, filtering processing of various data such as voice, vibration, temperature, and humidity. Further, the setting method of the processing characteristics of the filtering processing by the FIR filter in the twelfth embodiment can be applied to the filtering processing by other methods such as the filtering processing using FFT, for example, in addition to the filtering by the FIR filter. is there.

The method of setting the processing characteristics of the filtering processing by the FIR filter in the twelfth embodiment can be applied to the filtering processing by another type of DSP in addition to the filtering processing by the SIMD-controlled linear array multi-parallel processor. It is.

Further, the image data processing system 9 shown as the twelfth embodiment designs a filter circuit,
Since the description in the hardware description language of the designed filter circuit is created and output, a filter circuit having desired characteristics can be immediately transferred to actual production. Therefore, the image data processing system 9 shown as the twelfth embodiment is very useful in the design and manufacture of an ASIC or a dedicated LSI.

Thirteenth Embodiment Granular noise is granular noise often seen in old film images and the like. When broadcasting an old film movie or the like on a television, it is necessary to remove or reduce the granular noise, and the granular noise removal (reduction) processing is indispensable in the image processing system. First of the present invention
3 is an image data processing system 9 or 10 (FIG. 3).
7, 43) is applied to a granular noise removal process.

Granular Noise Removal Processing The granular noise removal processing will be described below with reference to FIGS. 62 and 63. FIG. 62 is a first diagram illustrating the granular noise removal processing according to the thirteenth embodiment of the present invention. FIG.
(A)-(E) are the 2nd figures which show the granular noise removal processing in the 13th Example of the present invention.

As shown in FIG. 62, the granular noise removal processing includes first multiplication processing, subtraction processing, delay processing, Hadamard transformation processing, noise separation processing, inverse Hadamard transformation processing, and second multiplication processing.

In the subtraction processing shown in FIGS. 63 (A) and (E), the coefficient k (0 <k <1) obtained by the first multiplication processing is used in the subtraction processing shown in FIGS. The image data (noise image data P ″ ′) obtained as a result of the inverse Hadamard transform process and multiplied by the coefficient (1−k) is subtracted from the input image data VIN including the multiplied granular noise to reduce the granular noise. It is removed (reduced) and output as output image data.

Hadamard Transformation Processing The Hadamard transformation processing shown in FIG. 63 (B) transforms output image data (P) given a time delay of one frame using a Hadamard matrix (M), Is separated.

Noise Separation Processing In the noise separation processing shown in FIG. 63 (C), among the motion components (P ') subjected to the Hadamard transform processing, those having an area larger than a predetermined threshold value are determined to be the motion of the object in the image. By determining a noise having a smaller area than a predetermined threshold as granular noise, only the noise component (P ″) is separated from the motion component.

Inverse Hadamard Transform Processing In the inverse Hadamard transform processing shown in FIG. 63 (D), the noise component (P ″) separated by the noise separation processing is converted using the Hadamard inverse matrix (M ⁻¹ ) Generate image data (P ″ ′).

In the thirteenth embodiment (image data processing system 11; FIG. 64) of the present invention, a threshold value used for determining a noise component in a motion component in a noise separation process among these processes is determined by a GUI. The configuration is such that the value can be set to any value, the setting can be easily changed, the noise separation processing can be performed, and the result of the noise separation processing can be immediately visually checked.

Structure of Image Data Processing System 11 FIG. 64 is a diagram showing the structure of the image data processing system 11 shown as the thirteenth embodiment of the present invention. FIG.
FIG. 65 is a diagram showing data input / output to / from the DSP 80 shown in FIG. 64. In FIGS. 64 and 65, among the components of the image data processing system 11, those identical to those of the image data processing systems 9 and 10 already shown in FIGS. The reference numerals are attached.

As shown in FIG. 64, the image data processing system 11 includes an input device 70, a personal computer 7
2. It comprises an image source 74, an image monitor 76, a DSP 80 and a frame memory 82. That is, the image data processing system 11 adds the frame memory 82 to the image data processing system 9, and as shown in FIG. 65, the image data VO obtained as a result of the granular noise removal processing.
A time delay of one frame is given to the UT, and the UT is input to the DSP 80 as second input data.
The image data processing system 11 performs a granular noise removal process for removing (reducing) the granular noise of the image data VIN input from the image source 74 using these components.

Components of Image Data Processing System 11 Hereinafter, among the components of the image data processing system 11 (FIG. 64), those having different operations and the like from the respective embodiments before the twelfth embodiment will be described.

[0511] The DSP 80 executes the program created by the personal computer 72 according to the setting of the separation point, and performs the granular noise removal processing.

[0512] Personal computer 72 Fig. 66, the image data processing system 11 shown in FIG. 64
FIG. 7 is a diagram showing a GUI image displayed on a monitor by the personal computer 72 for setting a separation point of a noise component. The graph in the separation point setting GUI image shown in FIG. 66 illustrates a case where the range from −60 to +60 is set as the separation point.

The display and display of the GUI image for setting the separation point
And setting personal computer 72, as shown in FIG.
In the noise separation process [FIGS. 62 and 63 (C)], for example, what area range (separation point) of the motion components obtained by the Hadamard transform process is detected as the noise component is determined, for example. A GUI image shown in a graph format is displayed on a monitor.

[0514] The user can change the passing point of the graph (indicated by a circle in Fig. 66) in the image for setting the separation point (Fig. 66) on the GUI screen displayed on the monitor, for example, in the eleventh place.
As in the case of setting the function S in the embodiment, the input device 70 is moved by a click operation and a drag operation of a mouse or the like to perform an operation of setting a separation point. During this setting operation, the curve of the graph on the GUI screen is enlarged or reduced while maintaining a similar shape.

Creation of Program for DSP 80 In response to the user's setting operation, the personal computer 72 changes and displays the curve of the graph in the GUI image. Further, when the user completes the setting of the range and performs a predetermined operation for ending the setting of the range via the input device 70, the personal computer 72 determines the separation point, and based on the determined separation point, , Create a program for the DSP 80 that executes the granular noise removal processing,
Download to DSP80.

[0516] The processing contents of the program for the DSP 80. Hereinafter, the DSP 8 created by the personal computer 72 will be described.
The processing contents of the program for 0 will be described. The DSP 80 (parallel processor 6; FIG. 3) of the image data processing system 11
2) indicates that, for example, the input image data VIN is
The pixel block is divided into pixel blocks of 2 pixels by 2 pixels, and each pixel block is subjected to Hadamard transform processing to detect a motion component including a noise component.

For this reason, the DSP 80 stores, in the data memory section 23 of each element processor 30, an area for storing image data VIN, an area for storing eight data used for Hadamard transform processing, and eight data used for matrix operation. And an area for storing a coefficient used for detecting a noise component.

[0518] Hadamard transform Next, DSP 80 calculates the difference between corresponding pixel data of the frame input to the latest (current frame), frame input to the previous (the previous frame), the difference The values are subjected to Hadamard transform processing (FIGS. 62 and 63 (B)).
That is, each of the element processors 30 of the DSP 80 calculates the difference value of the pixel block included in the pixel block of the horizontal 4 pixels × vertical 2 pixels to be subjected to the Hadamard transform by P0.
0 to P04 and P10 to P14, a Hadamard transform process shown in the following equation 11 is performed on an 8 × 1 matrix having these difference values as elements using an 8 × 8 Hadamard matrix, and a noise component P ″ is obtained. A motion component P ′ including the motion component is detected.

[0519]

P ′ = MP (11) where || denotes a matrix, and | P00 || P'00 || P01 || P'01 || P02 || P'02 | P = ｜ P 03 ｜ ｜ P '03 ｜ ｜ P 10 ｜ P '= ｜ P '10 ｜ ｜ P 11 ｜ ｜ P '11 ｜ ｜ P 12 ｜ ｜ P '12 ｜ ｜ P 13 ｜ ｜ P '13 ｜ ｜ 1 1 1 1 1 1 1 1 │ │ 1 -1 1 -1 1 -1 1 -1 │ │ 1 1 -1 -1 1 1 -1 -1 │ │ 1 -1 -1 1 1 -1 -1 1 │ M = | 1 1 1 1 -1 -1 -1 -1 │ │ 1 -1 1 -1 -1 1 -1 1 │ │ 1 1 -1 -1 -1 -1 1 1 │ │ 1 -1 -1 1 -1 1 1 -1 |

Here, the operation for each element in Expression 11 is performed by using the function F for calculating A + B and AB from the numerical values A and B shown in Expression 12 below, and calculating the numerical values X01 to X03 and Y01.
To Y032 are defined as shown in the following Expressions 13 and 14.

[0521]

F (A, B → A + B, AB) (12)

[0522]

F (P00, P01 → X00 = P00 + P01, X01 = P00-P01) F (P02, P03 → X02 = P02 + P03, X03 = P02-P03)… (13)

[0523]

F (X00, X02 → Y00 = P00 + P01 + P02 + P03, Y01 = P00 + P01-P02-P03) (P01-P02 + P03)… (14)

The elements P00 to P03 of the matrix P are divided into upper lines (first line) and the elements P10 to P13 are divided into lower lines (second line). Suffices to store the values calculated by the element processors 30 in the first line operation processing up to the second line operation processing.

[0525]

## EQU15 ## Y10 = P10 + P11 + P12 + P13 Y11 = P10 + P11-P12-P13 Y12 = P10-P11 + P12-P13 Y13 = P10-P11-P12 + P13 (15)

Further, each element processor 30 is expressed by the following equation (1).
By performing the arithmetic processing shown in FIG. 6, 8
A × 1 matrix P ′ (motion component P ′) can be calculated.

[0527]

(16) F (Y00, Y10-> P'00 = Y00 + Y10, P'10 = Y00-Y10) F (Y02, Y12-> P'01 = Y02 + Y12, P'12 = Y02-Y12) F (Y01, Y11-> P'02 = Y01 + Y11, P'11 = Y01-Y11) F (Y03, Y13-> P'03 = Y03 + Y10, P'13 = Y03-Y13)… (16)

Noise Component Detection Processing Next, each element processor 30 of the DSP 80 sets the value of the element P'00 to P'13 of the matrix P '(motion component P') obtained by the Hadamard transformation processing to a numerical value 0. Is determined as a noise component (P ″), and elements other than the noise component (P ″) are removed.

Each element processor 30 of the DSP 80 uses the parameters extracted from the separation points set for the GUI image shown in FIG.
The conversion is performed by approximating the function P ″ shown in FIG. 66 with a linear function for each of the first to fifth regions, and the noise component P ″ is obtained.
Is detected. That is, each element processor 3 of the DSP 80
In the case of 0, a component having a value outside the range of -60 to +60 among the elements of the matrix P 'is determined as a motion component, and the value is set to 0.
Those that fall within the range of 60 to +60 are determined to be noise components P ″ and are left.

[0530]

[Table 9]

[0531] The noise component detection processing of each element processor 30 of the DSP 80 will be described more specifically. First, D
Each element processor 30 of the SP 80 includes a data memory unit 2
An area for storing the coefficients A and B is secured in 3.

Next, each element processor 30 checks the matrix P ′
It is determined whether or not the value of each element is larger than −60. If larger, the numerical values −1 and −60 are substituted for the coefficients A and B, respectively, and if smaller, the numerical values 0 and 0 are substituted.

Next, the element processor 30 judges whether or not the value of each element of the matrix P ′ is smaller than −30. If the value is larger, the numerical values 1, 0 are substituted into the coefficients A and B. , B are not changed.

By repeating the calculation processing of the coefficients A and B described above, each element processor 30 determines which of the five areas shown in Table 9 the value X of each element of the matrix P ′ belongs to. The values of the coefficients A and B can be obtained according to the following equation. The noise component P ″ is detected by substituting the value P ′ of each element of the matrix P ′ into the following equation 17 using the coefficients A and B: be able to.

[0535]

P ”= AP '+ B (17) where | P" 00 | | P "01 | | P" 02 | P "= | P" 03 | | P "10 | | P" 11 | | P "12 || P" 13 |.

Inverse Hadamard Transformation Further, each element processor 30 of the DSP 80 uses the Hadamard inverse matrix M ⁻¹ for the matrix P ″ (P ″ 00 to P ″ 13) as shown in the following equation (18). An inverse Hadamard transform is performed to generate an 8 × 1 matrix noise image P ″ ′ indicating granular noise.

[0537]

P "'= M ^-1 P (18) where | P"'00 | | P "'01 | | P"'02 | P "= | P"'03 || P "'10 || P "'11 || P"'12 || P "'13 || 1 1 1 1 1 1 1 1 || 1 -1 1 -1 1 -1 1 -1 | 1 | 1 1 -1- 1 1 1 -1 -1 │ M ^-1 = − │ 1 -1 -1 1 1 -1 -1 1 │ 8 │ 1 1 1 1 -1 -1 -1 -1 │ │ │ 1 -1 1 -1- 1 1 -1 1 │ │ 1 1 -1 -1 -1 -1 -11 1 │ │ 1 -1 -1 1 -1 1 1 -1 │.

Note that the matrix operation shown in Expression 18 is also performed by Expression 13
By using the function F shown in the equation (14), the operation can be realized with a small amount of calculation.

[0539] Each element processor 30 of the noise component removal processing DSP 80 converts the noise image P "'generated as described above into the input image data VIN.
To remove granular noise.

Operation of Image Data Processing System 11 Referring now to FIGS. 67 and 68, image data processing system 11 (FIG.
The operation 4) will be described. FIG. 67 is a diagram showing the operation of the image data processing system 11 shown as the thirteenth embodiment of the present invention. FIG. 68 is a flowchart showing the operation of the image data processing system 11 shown as the thirteenth embodiment of the present invention.

As shown in FIG. 68, in step S400, the personal computer 72 displays the GUI image for setting the separation point shown in FIG. 66 on the monitor device, and allows the user to operate the input device 70 with the mouse or the like. Depending on,
The curves of the graph in the GUI image are sequentially changed and displayed. In addition, the user finishes inputting the separation point,
When a predetermined operation is performed on the GUI image, the personal computer 72 determines and accepts a separation point corresponding to a curve of a graph in the GUI image.

[0542] In step S402, the personal computer 72 extracts the function P "shown in Table 9 based on the parameters obtained from the input separation points. In step S404, the personal computer 72 shows in FIG. The program generation tool is activated as described above, and a source program for the DSP 80 for performing the granular noise removal processing is created using the function P ″ obtained in the processing of S402. Further, the personal computer 72 activates an assembler for the DSP 80 as shown in FIG. 67 and compiles a source program to create an object program.

[0543] In step S406, the personal computer 72 transfers (downloads) the created object program to the DSP 80. DSP80
Executes the downloaded object program, performs the granular noise removal processing on the image data VIN input from the image source 74, and displays the output image data obtained as the granular noise removal processing on the image monitor 76.

As described above, according to the image data processing system 11 shown as the thirteenth embodiment of the present invention, the granular noise elimination (reduction) device is a single SIMD-controlled linear array type multi-parallel processor. Will be realized,
The apparatus scale of the granular noise elimination apparatus can be reduced. Further, according to the image data processing system 11 shown as the thirteenth embodiment of the present invention, it is possible to set an arbitrary separation point by using the GUI, change the easily set separation point, and perform the granular noise removal processing. it can.

Further, according to the image data processing system 11 shown as the thirteenth embodiment of the present invention, the noise removal processing can be performed by software processing. The component can be detected, and the quality of the image after the granular noise removal processing is improved. Further, according to the image data processing system 11 shown as the thirteenth embodiment of the present invention, the result of the noise removal processing can be immediately confirmed on the image monitor 76.

[0546] As shown in FIG. 67, the processing of the personal computer 72 is performed in a plurality, for example, a plurality (eight).
8 GUI images for setting a separation point corresponding to each of the image data VIN, receiving the separation points input according to these GUI images, and setting different separation points for each of the plurality of image data VIN. You may change so that the used granular noise removal processing may be performed.

[0547] The separation point setting method in the image data processing system 11 shown as the thirteenth embodiment is based on a SIMD-controlled linear array multi-parallel processor (D
The present invention can also be applied to granular noise removal processing using a DSP of another format other than SP80). Further, the granular noise removal processing by the image data processing system 11 shown as the thirteenth embodiment can be applied to the removal and reduction of other types of noise in addition to the granular noise. Also, the first
The pixel block division method, the Hadamard matrix and the Hadamard inverse matrix in the image data processing system 11 shown as the third embodiment are examples, and can be arbitrarily changed according to the system configuration or the noise removal method. Further, the image data processing system 11 shown as the thirteenth embodiment can be variously modified as shown in each embodiment up to the twelfth embodiment.

Fourteenth Embodiment Hereinafter, as a fourteenth embodiment of the present invention, the image data processing systems 9 to 11 shown as the ninth to thirteenth embodiments will be described.
(FIG. 37, FIG. 43, FIG. 64), color correction processing (γ correction), chroma key processing, filtering processing using an FIR filter, image edge enhancement processing, and granular noise reduction processing [hereinafter, these processings are collectively called “effect”. )
Will be described only for a specific area of image data (screen).

As described above, in order to apply the effect processing only to a specific area of the image data (screen), the image data subjected to the effect processing and the original image data are prepared in advance, and only within the set area. Alternatively, a method of replacing the original image data with the image data subjected to the effect processing may be adopted. Hereinafter, setting of an area to be subjected to effect processing by the image data processing systems 9 to 11 (effect area setting) and a method of replacing image data will be described.

The personal computer of the image data processing systems 9 to 11
Operation of Null Computer 72 Hereinafter, the operation of the personal computer 72 of the image data processing systems 9 to 11 in the fourteenth embodiment will be described.

Display of GUI Image FIG. 69 shows the image data processing systems 9-1 when effect area setting shown as the fourteenth embodiment of the present invention is performed.
1 (FIG. 37, FIG. 43, FIG. 64) for the effect area setting GU displayed on the monitor by the personal computer 72.
It is a figure showing an I picture.

The personal computer 72 displays a GUI image for setting an effect area shown in FIG. 69 on a monitor. For example, as shown in FIG.
By clicking and dragging in the image using the mouse or the like of the input device 70, an arbitrary effect area (a rectangular area shown in Example 1 in FIG. 69 or a circular area shown in Example 2) in the image data (screen) is displayed. Area, etc.).

When setting a rectangular area, for example, as shown in Example 1 of FIG. 69, the personal computer 72 sets the point [coordinate (X1 , Y1)] and a point [coordinates (X2, Y2)] where the mouse is released after dragging is a diagonal line, and a rectangular area in which each side is parallel or perpendicular to the frame of the screen is an effect area. And the coordinates of two points [(X1, Y
1), (X2, Y2)] as parameters.

When setting a circular area , for example, as shown in Example 2 of FIG. 69, the personal computer 72 sets the point [coordinates] at which the user first clicks with the mouse of the input device 70. (X1, Y1)], and after dragging, the point at which the mouse is released [coordinates (X2, Y2)] is X
A circular area having a radius in the direction and the y direction is set as an effect area, and coordinates (X1, Y1) of the center point, a radius XR of the circle in the X-axis direction (XR = X2-X1), and
Numerical values (1 / XR ² , 1 / YR ² ) obtained from the radius YR of the circle in the Y-axis direction (YR = Y2-Y1) are accepted as parameters.

Creation of Program for DSP 80 After the effect area is set as described above, when the user performs various effect processing using the image data processing systems 9 to 11, the personal computer 72 operates only for the image data in the effect area. , A program for the DSP 80 to be replaced with the image data subjected to the effect processing is created.

The contents of the program for the DSP 80 created by the personal computer 72 will be described below. FIG.
0 is a first diagram showing the processing of the program of the DSP 80 generated by the personal computer 72 of the image data processing systems 9 to 11 (FIGS. 37, 43, 64) shown as the fourteenth embodiment.

As shown in FIG. 70, in step S410, each element processor 30 of the DSP 80 performs numbering (program 0; S420, S422).
For example, the program can be switched between the vertical flyback period and other periods. The numbering refers to, for example, assigning a number 1 to each of the element processors 30 to the leftmost element processor, and assigning an ascending number in order to the right.

That is, in step S420, DS
The element processor 30 of P80 (parallel processor 6; FIG. 37) substitutes a numerical value 0 for a variable Y. Step S422
, The element processor 30 is located at the front (on the left side)
Numbering is performed on the variable X by repeating the operation of adding the numerical value 1 to the variable X of the element processor 30 (PE) and assigning it to the variable X of the element processor 30.

When performing numbering,
Since the leftmost element processor 30 (PE) does not have the leftmost element processor 30 (PE), the value of the variable X always becomes 0 (1 = 1 + 0). Therefore, the value of the variable X of each element processor 30 is as shown in the table below for the first time.

[0560]

[Table 10] PE | 0 | 1 | 2 | 3 | 4 | 5 |… X | 1 | 1 | 1 | 1 | 1 | 1 | …… (9)

Further, when the numbering is repeated, the value of the variable X of each element processor 30 is as shown in Table 11 below.

[0562]

[Table 11] PE | 0 | 1 | 2 | 3 | 4 | 5 | ... X | 1 | 2 | 2 | 2 | 2 | 2 | ... (10)

When such numbering is repeated, the values of the variables of each element processor 30 are as shown in Table 12 below, and the variable X is a value indicating the position of each element processor 30 in the horizontal scanning direction.

[0564]

[Table 12] PE | 0 | 1 | 2 | 3 | 4 | 5 | ... X | 1 | 2 | 3 | 4 | 5 | 6 | ... (11)

[0565] In step S412, the element processor 30 determines whether or not it is within the vertical retrace interval. If it is within the vertical retrace interval, the process proceeds to step S414 and the program 1 (S430, S432) is executed. Is executed, otherwise, the process proceeds to S414 and the program 2 (S
440, S442).

[0566] In step S430 of program 1, the element processor 30 substitutes a numerical value 0 for a variable Y. In step S431, the element processor 30
Determines whether the pixel position of the image data is within the effect area, and outputs data having a value corresponding to the determination result.
In step S440 of the program 2, the element processor 30 adds a numerical value 1 to the variable Y (Y = Y + 1).
In step S431, the element processor 30 determines whether or not the pixel position of the image data is within the effect area, and outputs data having a value according to the determination result.

Referring to FIGS. 71 and 72, the contents of the processing for judging whether or not the program is in the effect area in S432 and S442 of programs 1 and 2 and the processing for outputting data according to the judgment result will be described. explain.

When a rectangular effect area is set
(Example 1) FIG. 71 shows S432 and S4 of programs 1 and 2 (FIG. 70) when the rectangular area shown in example 1 of FIG. 69 is set.
FIG. 42 is a flowchart showing a process of determining whether or not the area is within the effect area in 42 and a process of outputting data according to the determination result.

As described above, when the user operates the mouse or the like of the input device 70 to set a rectangular effect area, the personal computer 72 displays the figure shown in Example 1 in FIG. 69 in the GUI window. And the coordinates (X1, Y1) of the point clicked first with the mouse, and
The coordinates (X2, Y2) of the point where the mouse is released by dragging are accepted as parameters, and are set in each element processor 30 of the DSP 80. Hereinafter, for simplification of the description, a case where X1 <X2, Y1 <Y2 will be described as an example.

[0570] DSP80 (parallel processor 6; Fig. 37)
Each of the element processors 30 assigns a numerical value 1 to a variable F,
As shown in FIG. 71, if the value of the variable X is smaller than the parameter X1 in step S450, S460
Otherwise, the process proceeds to S452.

[0571] In step S452, if the value of the variable X is larger than the parameter X2, each element processor 30 proceeds to the process of S460.
Proceed to 454.

In step S454, if the value of the variable Y is smaller than the parameter Y1, each element processor 30 substitutes a numerical value 0 for the variable F and proceeds to the process of S460. Otherwise, the process of S456 is performed. Proceed to.

In step S456, when the value of the variable Y is larger than the parameter Y2, each element processor 30 substitutes a numerical value 0 for the variable F and proceeds to the process of S460. Otherwise, the process of S458 is performed. Proceed to.

[0574] In step S458, the element processor 30 determines that the pixel data to be processed is within the range of the effect area, and substitutes a numerical value 0 for a variable F.

[0575] In step S460, the element processor 30 determines that the pixel data to be processed is outside the range of the effect area, and substitutes a numerical value 0 for a variable F.

[0576] In step S462, if the value of the variable F is 1, the element processor 30 proceeds to the process of S464, and outputs the image data subjected to the effect process as a processing result. And outputs image data (original data) that has not been subjected to effect processing as a processing result.

When a circular effect area is set (example
2) FIG. 72 shows S432 and S44 of programs 1 and 2 (FIG. 70) when the circular area shown in example 2 of FIG. 69 is set.
A determination process of whether or not it is within the effect area in 2;
FIG. 11 is a flowchart illustrating a data output process according to a determination result.

[0578] As described above, when the user operates the mouse or the like of the input device 70 to set a circular effect area, the personal computer 72 displays the figure shown in Example 2 of FIG. And the coordinates (X1, Y1) of the point clicked first with the mouse, and X
Numerical values (1 / XR ² , 1 / YR ² ) calculated from the radii XR and YR in the axial direction and the Y-axis direction are accepted as parameters and set in each element processor 30 of the DSP 80.

As shown in FIG. 72, in step S470, each element processor 30
Is substituted into a variable X2 (X2 = X-X1),
The value obtained by subtracting the variable Y1 from the variable Y is substituted for the variable Y2 (Y2 = Y−Y1).

[0580] In step S472, the processor elements 30, the variable X2, variable X2 ² parameters XR
(X2 = X2 ² / X)
R ² ), the variable Y2 ² is replaced by the parameter YR 2
The value divided by the power value is substituted into a variable Y2 (Y2 = Y2 ²
/ YR ² ).

In step S474, when the added value of the variables X2 and Y2 is greater than or equal to the numerical value 1, the element processor 30 substitutes the numerical value 0 for the variable F, and proceeds to the process of S478. If the added value is less than the numerical value 1, the numerical value 1 is substituted for the variable F, and S462 to S466
Proceed to the process in FIG.

The programs shown in FIGS. 70 to 72 are common to each effect processing. Therefore, FIG.
By adding the program shown in FIG. 72 to the program for each effect processing, each effect processing can be performed only on the pixel data in the effect area set by the user.

The image data processing system in the fourteenth embodiment
The operation of the image data processing systems 9 to 11 in the fourteenth embodiment will be described below with reference to FIG. Figure 73
Is the image data processing system 9 in the fourteenth embodiment.
FIG. 67 is a flowchart showing an operation of FIG. 11 to FIG. 11 (FIGS. 37, 43, and 64).

As shown in FIG. 73, in step S480, the personal computer 72 displays the GUI image shown in FIG. 69 on a monitor for the personal computer 72.

[0585] In step S482, the personal computer 72 changes the state of FIG.
Change the shape of the figure in the window shown in and display it.
When the user completes the setting and performs a predetermined operation, the personal computer 72 determines the effect area.

[0586] In step S484, the personal computer 72 extracts a parameter indicating the effect area in accordance with the setting of the user, and outputs the parameter to the element processor 30.
Each element processor 30 of (parallel processor 6; FIG. 37)
Set to.

[0587] In step S486, the personal computer 72 stores a parameter indicating the effect area.

In step S488, the personal computer 72 creates a program for setting the effect area shown in FIGS. 70 to 72 by including parameters in the template program.

[0589] In step S490, the personal computer 72 compiles the area selection program together with each effect processing program selected as shown in Fig. 74, and in step 492 (S492), an object program (object binary).
Generate

[0590] In step S494, the personal computer 72 transfers (downloads) the generated object program to each element processor 30 of the DSP 80. Note that an object program may be prepared as a template, and only the parameter portion in the object program may be replaced to generate and transfer the entire object (object binary).

[0590] In step S496, each element processor 30 of the DSP 80 executes the transferred program, performs various effect processing only on the image data in the set effect area, and outputs the result as a processing result.

As described above, according to the operations of the image data processing systems 9 to 11 shown in the fourteenth embodiment, an arbitrary effect area is set and only the image data in the set area is set. And various effect processing can be performed. Conventionally, switching hardware was required to perform various effect processing such as color correction while dividing an area. However, in the operation of the image data processing systems 9 to 11 shown as the fourteenth embodiment, the switching hardware was required. According to this, the effect processing such as color correction can be performed only on the image data in an arbitrary area only by rewriting the program of the DSP 80 without the switching hardware.

Fifteenth Embodiment In the following, as a fifteenth embodiment of the present invention, various effect processes shown as the ninth to thirteenth embodiments and the effect area designation shown as the fourteenth embodiment are integrated. The image data processing system 12 will be described.

Structure of Image Data Processing System 12 FIG. 74 is a diagram showing the structure of the image data processing system 12 shown as the fifteenth embodiment of the present invention. FIG.
In FIG. 4, among the components of the image data processing system 12, the same components as those of the image data processing systems 9 to 11 shown in the fourteenth embodiment are denoted by the same reference numerals. .

As shown in FIG. 74, the image data processing system 12 includes an input device 70 having a mouse 700 and a personal computer 7 having a display device 720.
2, input image selector 84, first frame memory 82
₁ , DSP 80 (for example, parallel processor 6; FIG. 3)
2), and a second frame memory 82 _2, and an output monitor selector 86.

That is, the image data processing system 12
For example, the image data processing system 9 (FIG. 37) has a configuration in which frame memories 82 ₁ and 82 ₂ , an input image selector 84 and an output monitor selector 86 are added, and is not explicitly described in the fourteenth embodiment. The mouse 700 is an example of the input means of the input device 70, and the display device 7 of the personal computer 72.
20 are explicitly shown.

[0597] The input unit 14 is a device for outputting image data of a hard disk device (HD) 140 in a personal computer as an image signal, and a D1 type VTR device (D
1) 142, NTSC image signal source (NTSC) 146,
Analog / digital (A / D) conversion circuits 148 and 15 for converting analog image signals input from RGB image signal source (RGB) 150, NTSC image signal source 146 and RGB image signal source 150 into digital image data.
2, and a plurality of various digital image data sources, such as a VGA device 154, each of which provides image data VIN to the image data processing system 12. The output unit 16 is a high-resolution (HD monitor) 16
It includes a plurality of various image display devices such as a 0 and D1 type monitor (D1 monitor) 162, and these components are composed of image data V supplied from the image data processing system 12.
Display OUT.

The image data processing system 12 includes the input unit 1
4 performs the effect processing and the like shown in the ninth to thirteenth embodiments on the image data VIN input from any of the plurality of image data sources for each specified effect area to generate image data VOUT. Then, the image is displayed on all or any of the plurality of image display devices of the output unit 16.

Components of Image Data Processing System 12 Hereinafter, components of the image data processing system 12 which are not included in the image data processing systems 9 to 11 will be described.

Input Image Selector 84 The input image selector 84 is a personal computer 72
Under the control of, select one of the image data VIN input from a plurality of image data sources of the input unit 14 (a hard disk drive 140, etc.) for output to the frame memory 82 _1. The input image selector 84, when a plurality of image data as input image data VIN is required, select a plurality of image data from a plurality of image data sources of the input unit 14 outputs to the frame memories 82 ₁ I do.

[0601] The frame memory 82 _frame memory 82 _1, for example, interlace / non-interlace conversion, the conversion of number of pixels in the vertical direction, or used for purposes such as synchronization frame, inputted from the input image selector 84 The image data is given a time delay according to the purpose and output to the DSP 80 (parallel processor 6; FIG. 32).

[0602] The frame memory ₈₂₂ frame memory ₈₂₁ is, for example, or non-interlaced / interlaced conversion, the frame memory 82
_It is used for the same purpose as ₁ and the like, and gives a time delay according to the purpose to the image data obtained as a result of the processing by the DSP 80 and outputs it to the output monitor selector 86.

Output Monitor Selector 86 The output monitor selector 86
2 Follow the control, the image data VOUT inputted from the frame memory _822, and outputs to all or a portion of the plurality of image display device of the output unit 16.

Software Configuration FIG. 75 is a diagram showing an outline of the processing of the image data processing system 12 shown as the fifteenth embodiment of the present invention. FIG.
FIG. 6 is a view showing a GUI image for effect processing selection displayed on the display device 720 by the personal computer 72.

As shown in FIG. 75, in step S500, the personal computer 72 displays a GUI image for effect processing selection shown in FIG. 76 on a monitor.
GU using the mouse 700 of the input device 70 by the user
An effect processing selection operation for an I image is accepted.

In step S502, the personal computer 72 proceeds to steps S52, S54, S56, S60, and S64 to S72 according to the accepted selection operation by the user.

[0607] In step S52, the personal computer 72 passes the image data VIN input from the input section 14 and creates a program for the DSP 80 to output as the image data VOUT (Through).

[0608] In step S520, the personal computer 72 transfers (downloads) the prepared communication program to the DSP 80.

[0609] In step S522, the DSP 80
Executes the program downloaded from the personal computer 72, and outputs the image data VIN without passing through it.

In step S72, the personal computer 72 performs the effect area selection processing shown in the fourteenth embodiment.

[0611] In step S720, the personal computer 72 operates the effect area designating GUI image (FIG. 69) displayed on the display device 720 in response to the effect area designating operation performed by the user using the mouse 700 or the like. Select an area.

In step S722, the personal computer 72 extracts and stores the parameters of the effect area selected by the effect area designating operation.
Proceed to region selection processing.

[0613] In step S54, the personal computer 72 proceeds to process A (described later with reference to Fig. 77), and performs the chroma key process shown in the tenth embodiment. In step S56, the personal computer 72 proceeds to process B (described later with reference to FIG. 80), and performs the first
The filtering processing by the FIR filter shown as the third embodiment is performed.

[0614] In step S60, the personal computer 72 proceeds to process C (described later with reference to Fig. 82), and performs the color correction (γ correction) process described in the ninth embodiment.

[0615] In step S64, the personal computer 72 proceeds to process C, and performs a filtering process on the image data of the GUI image by the user according to the setting (retouch).

[0616] In step S66, the personal computer 72 proceeds to process C to perform a color number conversion process (p
ostalization).

[0617] In step S68, the personal computer 72 proceeds to process A, and outputs the image data VIN.
As shown in the first to sixth embodiments, continuous zoom processing for enlarging / reducing is performed.

[0618] In step S70, the personal computer 72 proceeds to process A, and performs interactive zoom (int) for enlarging or reducing the image data VIN in accordance with the operation.
eractive zoom) processing.

Processing A The processing A shown in FIG. 76 will be described below with reference to FIGS. FIG. 77 shows S54 and S6 shown in FIG.
8 is a flowchart illustrating a process A started in the processes of S70. FIG. FIG. 78 is a flowchart showing the operation of S54 shown in FIG.
FIG. 75 is a diagram exemplifying a GUI image for continuous zoom processing displayed on the display device 720 (FIG. 74) in the process 0. FIG. 79 is a diagram exemplifying a GUI image for interactive processing displayed on the display device 720 (FIG. 74) in the processing of S540 shown in FIG.

When the processing A is started in the processing of S54, S68 and S70 shown in FIG. 75, as shown in FIG. 77, in step S540, the personal computer 72 executes the processing according to the selected effect processing. 45
The GUI image for selecting the background color for the chroma key processing shown in FIG. 78, the GUI image for the continuous zoom processing shown in FIG. 78, or the GUI image for the interactive zoom processing shown in FIG. 79 is displayed on the display device 720.

[0621] In step S542, the personal computer 72 accepts a setting operation by the user. For example, when performing the continuous zoom process, the user needs to perform the process shown in FIG.
An operation of setting a horizontal magnification and a vertical magnification is performed on the GUI image for continuous zoom processing shown in FIG.
Accepts the set magnification.

[0622] For example, when performing the interactive zoom processing, the user operates the buttons (set, reset, mai) in the interactive zoom processing GUI shown in FIG.
(horizontal) and vertical (vertical) magnifications by pressing the “ntain aspect ratio”, dragging the windows in the GUI in the a to c directions using the mouse 700, and the like. 72 accepts the set magnification.

[0623] In step S544, the personal computer 72 extracts parameters necessary for realizing various effect processes according to the settings of the user.

[0624] In step S546, the personal computer 72 stores the parameters for various effect processes extracted in the process of S544.

[0625] In step S548, the personal computer 72 executes the DSP 8 for realizing various processes from the template programs and parameters for various processes.
Create a program for 0.

[0626] In step S550, the personal computer 72 compiles each effect processing program created in the process in S548, and generates an object program (object binary) in step S552.

[0627] In step S554, the personal computer 72 transfers (downloads) the generated object program to each element processor 30 of the DSP 80.

[0628] In step S556, each element processor 30 of the DSP 80 executes the transferred program, performs various effect processing, and outputs a processing result.

Processing B Hereinafter, referring to FIGS. 80, 81 (A) and (B), FIG.
Process B shown in FIG. 6 will be described. FIG. 80 is a flowchart showing a process B started in the process of S56 (FIR filter) shown in FIG. FIG. 81 (A),
FIG. 80B is a diagram exemplifying a GUI image displayed on the display device 720 in the process of S560 shown in FIG. 80.

When the processing B is started in the processing of S56 shown in FIG. 76, as shown in FIG.
At 60, the personal computer 72, in accordance with the selected effect processing, performs the GU for the filtering processing by the FIR filter shown in FIGS. 81 (A) and (B).
The I image is displayed on the display device 720.

[0631] In step S562, the personal computer 72 accepts the setting operation of the user as described in the thirteenth embodiment.

[0632] In step S564, the personal computer 72 extracts parameters necessary for realizing the filtering process in accordance with the settings of the user.

[0633] In step S566, the personal computer 72 activates a filter design tool for calculating a filter coefficient from the specified passband and element area, and
A filter coefficient of the FIR filter having characteristics suitable for the parameters extracted in the processing of S564 is obtained.

In step S568, the personal computer 72 quantizes the filter coefficients of the FIR filter designed in step S566 based on the parameters extracted in step S564.

[0635] In step S570, the personal computer 72 stores the parameters calculated in the process of S568.

[0636] In step S572, the personal computer 72 creates a program for the DSP 80 that implements a filtering process using an FIR filter by including parameters in the template program.

[0637] In step S574, the personal computer 72 compiles the program created in the process in S572, and in step S576, an object program (object binary)
Generate

[0638] In step S580, the personal computer 72 transfers (downloads) the generated object program to each element processor 30 of the DSP 80.

[0639] In step S582, each element processor 30 of the DSP 80 executes the transferred program to perform a filtering process using an FIR filter.
Output the processing result.

Process C Hereinafter, the process C shown in FIG. 76 will be described with reference to FIGS. 82 to 85. FIG. 82 shows S60 and S6 shown in FIG.
FIG. 4 is a flowchart showing a process C activated in the processes of S66. FIGS. 83 (A) and (B) show FIG.
In the process of S600 shown in FIG.
FIG. 11 is a diagram illustrating a GUI image for color correction (γ correction) processing displayed at 0.

FIGS. 84 (A) to (C) are views showing examples of the GUI image for the filtering process (retouch) displayed on the display device 720 in the process of S600 shown in FIG. 82. FIG. 85 is a flowchart showing the operation of S6 shown in FIG.
FIG. 20 is a diagram illustrating a GUI image for color number conversion processing (postalization) processing displayed on the display device 720 in the processing of 00.

When the processing C is started in the processing of S60, S64, and S66 shown in FIG. 75, as shown in FIG. 78, in step S600, the personal computer 72 executes the processing according to the selected effect processing. 83
(A), (B), GUI images for various effect processes shown in FIGS. 84 (A) to (C) and FIG. 85 are displayed on the display device 720.

In step S602, the personal computer 72 accepts the user's setting operation for the GUI images shown in FIGS. 83 (A) and (B) to FIG.

[0644] In step S604, the personal computer 72 determines whether or not the effect area has been set as described in the fourteenth embodiment. When there is no setting, the personal computer 72 proceeds to the process of S606, and when there is a setting, the personal computer 72 proceeds to S606 and S62.
It proceeds to the process of 0.

In steps S620 to S626, the personal computer 72 performs the processing corresponding to the processing in S484 to S490 shown in the fourteenth embodiment (FIG. 74) and executes the processing of the DSP 80 for setting the effect area. Create and compile.

[0646] In step S606, parameters necessary for realizing various effects are extracted according to the settings of the user.

[0647] In step S610, the personal computer 72 creates a program for each effect process by including the parameters extracted in the process in S606 in the template program.

[0648] In step S612, the personal computer 72 compiles the program created in the process of S610.

In step S630, the personal computer 72 executes S626 and S6 as necessary.
The programs compiled in the process 12 are linked, and an object program combining them is created.

[0650] In step S632, the personal computer 72 transfers (downloads) the object program generated in the process of S630 to each element processor 30 of the DSP 80.

[0651] In step S634, each element processor 30 of the DSP 80 executes the transferred program to perform various effect processing, and outputs a processing result.

Effect Processing Hereinafter, effect processing not described in the fourteenth embodiment will be described.

In the filter processing (reto uch) filter processing, the personal computer 72
Displays a GUI image [FIG. 84 (A)-(C)] window showing a menu of various filter processes on the display device 7.
20 and the GU using the mouse 700 by the user
Various filter processing programs for the DSP 80 (linear array type digital signal processor) are generated and executed in response to a click of a button in the I image.

The personal computer 72 is the same as that shown in FIG.
The GUI image shown in (A) is displayed, and the user presses a button in the GUI image with the mouse 700 and selects a type of the filtering process. For example, if the user
Among the buttons in (A), “3 × 3 Custum”, “5 × 5 Custum”
um ”, the personal computer 72
Displays the GUI images shown in FIGS. 84 (B) and 84 (C) on the display device 720.
A filter coefficient is input using a keyboard of 0 or the like. A divisor is set in the “Divide” window in the GUI image of FIG. 84B (corresponding to the processing of 704 in FIG. 86), and when the “Offset” window is checked, the offset value is set to 128. Therefore, the numerical value 128 is added to the output data.

[0655] Again the flow of the filter Referring to FIG. 82. Personal computer 72
Displays the GUI image shown in FIG. 84 (A) on the display device 720 (S600).

As a filtering method, “3 × 3 Cus
If a value other than “tom” and “5 × 5 Custom” is selected, the personal computer 72 sets a filter coefficient prepared in advance as a parameter (S606 in FIG. 82).
In step S608, a program for the DSP 80 is generated (FIG. 8).
2 (S612), and download (S63 in FIG. 82).
2).

As a filtering method, “3 × 3 Cus
When “tom” is selected, the personal computer 72 displays the GUI images shown in FIGS. 84 (B) and (C) on the display device 720. Also, “3 × 3 Cus
When “tom” is selected, the personal computer 72 displays the GUi image shown in FIG. 84C on the display device 720.

[0658] The user operates the GU of the display device 720.
When the Set button of the I image [FIGS. 84B and 84C] is clicked, the personal computer 72 executes the following.

The personal computer 72 stores the filter coefficients set on the display in the parameter file (S602 and S608 in FIG. 82), and the DSP 80
Is generated (S610 in FIG. 82), and the SIMD
The data is transferred to the controlling linear array type multi-parallel processor (S632 in FIG. 82).

The contents of the program for the DSP 80. Referring now to FIG.
The contents of the program for 0 will be described. FIG. 86 shows the fifteenth
In the embodiment, the DS of the image data processing system 12
It is a flowchart figure which shows the filter process which P80 performs.

In step S700, the DSP 80
Each element processor 30 of the (parallel processor 6) stores the pixel data of three lines in the data memory unit 23. In this case, as shown in Table 13 below, each element processor 30 rotates the address for storing the pixel data in the data memory unit 23, and uses the data of the latest line in the pixel of the oldest line in practice. The data is written to the next address, but from the program side, it is as if the same address is always at the head and the latest pixel data is stored in order. By rotating the addresses in this manner, the pixel data at addresses 0 to 15 of the data memory unit 23 is always input to the first tap among the three taps, and the pixel data at addresses 16 to 32 is stored in the next tap. Is input to the tap. Therefore, the element processor 30 can perform the filtering process by multiplying the filter coefficients in order from the pixel data of addresses 0 to 15 and sequentially adding the multiplication results.

[0662]

[Table 13] Memory Actually written Address data visible n cycles after the program side n = 3 n = 4 n = 5 0-15 1st line, 4th line 1st line 2nd line 3rd line 16-31 2nd line, 5th line 2nd line 3rd line 4th line 32-47 3rd line,: 3rd line 4th line 5th line ↑ ↑ ↑ Address rotation 0 -16 -32… (13)

In step S702, the ALU array section 24 of each element processor 30 uses the filter coefficients (Table 14; coefficients A to I) of each of the 3 × 3 taps to move forward one (left adjacent) to the element processor 30. 2) multiplies the pixel data at addresses 0 to 15 in the data memory unit 23 of the element processor 30 by the coefficient A, and substitutes it for the variable X.

[0664]

[Table 14] ABCDEFGHI ... (14)

The ALU array unit 24 multiplies the data of the pixels at addresses 0 to 15 in the data memory unit 23 of the element processor 30 by the coefficient B, and adds the result to the variable X. ALU
The array unit 24 multiplies the data of the pixels at addresses 0 to 15 in the data memory unit 23 immediately behind (to the right of) the element processor 30 by a coefficient C, and adds the result to the variable X. AL
The U array unit 24 multiplies the pixel data at addresses 16 to 31 in the data memory unit 23 immediately before (to the left of) the element processor 30 by a coefficient D and adds the result to a variable X. AL
The U array unit 24 adds the coefficient E to the pixel data at addresses 16 to 31 in the data memory unit 23 of the element processor 30.
And add it to the variable X. The ALU array unit 24
The pixel data at addresses 16 to 31 in the data memory unit 23 behind (to the right of) the element processor 30 are multiplied by a coefficient F and added to a variable X. The ALU array unit 24 is located in front of (to the left of) the element processor 30 in the data memory unit 2.
The pixel data at addresses 32 to 47 of No. 3 is multiplied by a coefficient G and added to a variable X. The ALU array unit 24 multiplies pixel data at addresses 32 to 47 of the element processor 30 by a coefficient H and adds the result to a variable X. ALU array unit 2
4 multiplies the pixel data at addresses 32 to 47 in the data memory unit 23 behind (to the right of) the element processor 30 by the coefficient I and adds the result to the variable X.

[0666] In step S704, the ALU array unit 24 of each element processor 30 stores the variable X in FIG.
Divide by the divisor set in the “Divide window” shown in (B), and substitute the result of the division into a variable X.

[0667] In step S706, each element processor 30 determines whether or not the "Offset window" shown in FIG. 84B has been checked, and if so, proceeds to the process in S708 and checks. If not, the process proceeds to S710.

[0668] In step S708, each element processor 30 adds the numerical value 128 to the variable X.

In step S710, each element processor 30 outputs the value of the variable X as a result of the filtering process.

[0670] In step S712, each element processor 30 rotates the address of the data memory unit 23 as described above.

The number-of-colors conversion process ( Postalization) The number-of-colors conversion process will be described below. In the color number conversion processing, the personal computer 72 displays the GUI image for the color number conversion processing shown in FIG. 85 on the display device 720, and performs the color number conversion processing in accordance with the user's operation on the displayed GUI image. A program for the DSP 80 to be executed is created and executed. In the GUI image for color number conversion processing shown in FIG. 85, when the user clicks the “[<<] button” with the mouse 700, a setting is made to increase the degree of reduction in the number of colors. Clicking on the ">>] button" makes settings to reduce the degree to which the number of colors is reduced.

Flow of Color Number Conversion Processing Referring again to FIG. Personal computer 72
Displays the GUI image for color number conversion processing shown in FIG. 85 on the display device 720 (S600).

[0673] The user sets the number of colors for the GUI image displayed on the display device 720, and the personal computer 72 accepts the set number of colors (S6).
02).

[0674] Furthermore, when the user clicks the "Set button" in the GUI screen with the mouse 700, the following processing is executed.

FIG. 87 is a diagram exemplifying a step function used in the color number conversion processing. Personal computer 72
Stores the parameters of the step function shown in FIG. 87 in the parameter file based on the number of colors set according to the GUI screen, creates a program for the DSP 80 using the stored parameters, and transfers the program to the DSP 80 ( S606
To S632).

The conversion of the number of colors is realized by performing the conversion using the step function shown in FIG. 87 on the color data of each pixel. This is done by changing the number of function stages. Also, for example, the step function is set as shown in Table 15 below.

[0677]

[Table 15] y = b (1) 0 (minimum value) <x <= 30 (x (1) = 30) y = b (2) 30 <x <= 80 (x (2) = 80) y = b (3) 80 <x <= 120 (x (3) = 120) ... y = b (N) 200 <x <= 255 (maximum value) (x (N) = 255)… (14)

[0678] the content of the program for the DSP80 below, with reference to FIG. 88, performs color conversion processing DSP80
The contents of the program for use will be explained. FIG. 88 shows the DSP of the image data processing system 12 in the fifteenth embodiment.
FIG. 7 is a flowchart illustrating a color conversion process performed by a color conversion processing;

Each element processor 30 of the DSP 80 (parallel processor 6) secures a memory area B for storing coefficients and a work area in the data memory unit 23, and assigns a numerical value 1 to a variable i. Next, as shown in FIG. 88, in step S720, for example, when the step function is set as shown in Table 15, each element processor 3
0 means that the value x of the color data of each pixel is a numerical value 30 [x (1)]
It is determined whether or not the value is greater than the value.
In step S734, the process proceeds to step S734, in which the process proceeds to step S734.
Is substituted for the numerical value b (1), and the process ends.

[0680] In step S724, each element processor 30 determines whether or not the variable i is smaller than a numerical value N indicating the number of steps in the step function. Otherwise, S730.
Proceed to processing.

In step S726, each element processor 30 determines whether or not the value x of the color data is greater than 80 [x (2)]. If the value is larger, the process proceeds to step S728 and the variable B is set to b (3). And if not large, S730
And the value of the variable B is stored. Step S73
At 0, each element processor 30 outputs the value of variable B.

Continuous zoom processing The continuous zoom processing will be described below. In the continuous zoom process, the personal computer 72 displays the GUI image for the continuous zoom process shown in FIG.
0, and receives the magnification setting according to the user's operation.
Based on the set magnification, a program for the DSP 80 for enlarging / reducing the image data is created, and the DSP 80 executes the program.

The user sets the magnification of the GUI image for the continuous zoom process shown in FIG. 78 by an operation such as clicking with the mouse 700 or by directly inputting it from the keyboard. The magnification includes a horizontal magnification and a vertical magnification. Since the setting method is the same, a case where the horizontal magnification is set will be described as an example.

In the case of setting a fixed magnification as the horizontal magnification, the user directly inputs the magnification in the text field of Mag at a 100-percent rate from the keyboard to the GUI image for the continuous zoom processing. In addition, if the user says "[Vari
Click the "able" button to perform a continuously variable zoom, and click the "[Normal] button" to return the magnification to 100%.

The flow of the continuous zoom process will be described with reference to FIG. When the user sets a fixed magnification for the GUI image for continuous zoom processing, the personal computer 72 stores the set magnification in a parameter file, generates a program for the DSP 80,
The data is transferred to the DSP 80 (S600 to S632).

[0686] However, the personal computer 72 allows the user to input "[Variable]" of the GUI image for continuous zoom processing.
When the button is clicked, a program for the DSP 80 that performs the continuously variable zoom process is created and transferred,
When the user clicks the "[Normal] button", the parameter file is stored at 100%, a program for the DSP 80 is generated and transferred. The program of the DSP 80 for performing the continuous zoom process is the same as the interpolation filtering process for enlarging or reducing image data at an arbitrary magnification shown in the first to sixth embodiments.

[0687] The interactive zoom process will be described below. As shown in FIG. 79, the personal computer 72 displays a GUI image for interactive zoom processing for interactively (interactively) setting the enlargement / reduction magnification on the display device 720, and FIG. In response to the user's setting operation of dragging the mouse 700 in the direction indicated by c, a program for the DSP 80 for enlarging / reducing an image is created and executed by the DSP 80.

When the user drags the lower side of the image display window in the GUI image for interactive zoom processing in the direction of a with the mouse 700 and the lower side of the image with the mouse, the personal computer 72 sets the magnification in the vertical direction. In response to this, the display of the window is enlarged / reduced in the vertical direction.

[0689] When the user drags the side of the image display window with the mouse 700 in the direction b, the personal computer 72 receives the setting of the horizontal magnification and enlarges the display of the window in the horizontal direction. ·to shrink. When the user drags the corner of the image display window with the mouse 700 in the direction of c with the mouse, the personal computer 72 receives the settings of the vertical and horizontal magnifications and changes the window display in the vertical and horizontal directions. Scale.

[0690] When the user checks the "Maintail Aspect Retio button", the personal computer 72 enlarges / reduces the window display while maintaining the ratio in the vertical and horizontal directions.

Flow of Interactive Zoom Processing Referring again to FIG. Personal computer 72
Is G for the interactive zoom processing shown in FIG.
The UI image is displayed on the display device 720. When the user clicks the "[Set] button", the following processing is executed.

The personal computer 72 sets the interactive zoom processing GUI image.
Parameters are extracted based on the vertical and horizontal magnifications and stored in a parameter file. Further, the personal computer 72 creates a program for the DSP 80 for performing the interactive zoom process, and
80 (S600 to S632).

[0691] However, when the user clicks the "[Reset] button" of the GUI image for interactive zoom processing, the personal computer 72 sets the magnification in the vertical direction and the horizontal direction to 100%, and generates parameters. Further, the personal computer 72 creates a program for the DSP 80 that performs the interactive zoom processing with the magnification in the vertical direction and the horizontal direction being 100%, and transfers the program to the DSP 80. The program of the DSP 80 for performing the interactive zoom processing includes first to sixth programs.
This is the same as the interpolation filtering processing in the case where the image data is enlarged / reduced at an arbitrary magnification shown in the embodiment.

Although not shown in FIG. 76, the image data processing system 12 further has the following functions.

[0695] O image selection view 89 is a diagram showing a GUI image for input and output image selection of the image data processing system 12 shown as a fifteenth embodiment. As shown in FIG. 89, the personal computer 72 displays an input / output selection GUI for displaying images input from the hard disk device 140 to the VGA device 154 of the input unit 14 in a plurality of windows.

The user can use the mouse 700 to move the window in which the desired image in the input / output selection GUI image is displayed.
Click to select the personal computer 7
2 controls the input image selector 84, among a plurality of image data input from the input unit 14, to select the image data corresponding to the image is clicked, to output to the frame memory 82 _1.

However, if the image data processing system 12 is HD
When the user clicks the “Main Video Source button” in the input / output selection GUI image when the image data VOUT is set to be displayed on the monitor 160, the personal computer 72
Controls the input image selector 84 so that the hard disk device 140, the VTR device 142, the NTSC image signal source 1
46 (A / D conversion circuit 148) and the RGB image signal source 150 (A / D conversion circuit 152) are switched in this order to select the supply source of the image data VIN.

The image data processing system 12 has the D1
When the user clicks the “Main Video Source button” in the input / output selection GUI image when the image data VOUT is set to be displayed on the monitor 162, the personal computer 72
Controls the input image selector 84 so that the VTR device 14
2. NTSC image signal source 146 (A / D conversion circuit 14
8), RGB image signal source 150 (A / D conversion circuit 15
Switching in the order of 2) and VGA device 154,
The source of the image data VIN is selected.

[0699] Also, when the user clicks the "Back Video Source button" in the input / output selection GUI image,
Each time the user clicks, the personal computer 72 controls the input image selector 84 so that the VTR devices 142 and N
TSC image signal source 146 (A / D conversion circuit 148), R
By switching in the order of the GB image signal source 150 (A / D conversion circuit 152) and the VGA device 154, the supply source of the image data VIN is selected, and after the display of the image data input from the VGA device 154, The image data input from the four sources is displayed by dividing the screen of the display device 720 into four parts.

The user selects “Definition” in the input / output selection GUI image.
When the item “HD” is selected from the items of the radio button, the personal computer 72 controls the output monitor selector 86 to transfer the image data VOUT to the HD monitor 1.
60 is displayed. When the user selects the item “SD”, the personal computer 72 controls the output monitor selector 86 to display the image data VOUT on the D1 monitor 162.

When the user selects the item “30P” in the “Mode” radio button in the input / output selection GUI image, the personal computer 72 displays the image in a progressive format of 30 frames per second. It generates and outputs data VOUT.
In addition, the user selects “Mode” in the input / output selection GUI image.
Is selected, the personal computer 72 generates and outputs image data VOUT in a 60-field interlaced format per second.

Setting of Main Image Position at Output FIG. 90 is a view showing a GUI image for setting the position of the main image. The personal computer 72 displays a GUI image for setting a GUI image position shown in FIG. When the user clicks an arbitrary position in the GUI image for setting the GUI image position, the personal computer 72 sets the clicked position to the upper left position of the main image on the screen.

[0703]

As described above, according to the present invention,
For example, nonlinear processing such as color correction on image data can be performed using a DSP.

Also, according to the present invention, the contents of the non-linear processing such as color correction are described as the components (Y, Cr, C
(b, R, G, B, etc.) can be arbitrarily set using the GUI, and the result of the color correction processing or the like can be immediately confirmed on the GUI screen.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of an original image.

FIG. 2 is a diagram showing an example of an image obtained by enlarging an original image.

FIG. 3 is a diagram illustrating an example of a positional relationship between pixels of an original image and pixels of an enlarged image.

FIG. 4 is a diagram illustrating an example of an image in which the resolution of an original image is increased.

FIG. 5 is a diagram illustrating an example of an image obtained by reducing an original image.

FIG. 6 is a diagram illustrating an example of a positional relationship between pixels of an original image and pixels of a reduced image.

FIG. 7 is a diagram illustrating an example of an image in which the resolution of an original image is reduced.

FIG. 8 is a diagram illustrating an example of a positional relationship between pixels of an original image and pixels generated by interpolation.

FIG. 9 is a diagram illustrating an example of an interpolation relationship.

FIG. 10 is a block diagram illustrating a configuration example of a device that performs a filter operation in hardware.

11 is a diagram illustrating an example of a signal of each unit in each cycle of a filter operation performed in the device in FIG. 10;

FIG. 12 is a diagram illustrating an example of a correspondence relationship between a filter selection signal and a filter coefficient set.

FIG. 13 is a block diagram illustrating a configuration example of a device that performs a filter operation by software.

14 is a diagram illustrating an example of a supply pattern of input data when an image is enlarged in the apparatus of FIG. 13;

FIG. 15 is a diagram illustrating an example of a positional relationship with an element processor having data necessary for processing.

FIG. 16 is a block diagram illustrating a configuration of a second embodiment of the image processing apparatus according to the present invention.

FIG. 17 is a block diagram illustrating a configuration example of an element processor.

FIG. 18 is a circuit diagram illustrating a detailed configuration example of an element processor.

FIG. 19 is a flowchart illustrating an operation of the image processing apparatus in FIG. 16;

20 is a diagram illustrating an example of data stored in each unit of the image processing apparatus in FIG.

FIG. 21 is a diagram illustrating an example of a positional relationship with an element processor having data necessary for processing.

FIG. 22 is a diagram illustrating an example of a positional relationship in which the positional relationship of FIG. 21 is degenerated.

FIG. 23 is a flowchart illustrating a filter calculation process in the image processing apparatus in FIG. 16;

FIG. 24 is a flowchart illustrating a filter calculation process in the image processing apparatus of FIG. 16;

FIG. 25 is a block diagram showing the configuration of a third embodiment of the image processing apparatus of the present invention.

FIG. 26 is a diagram showing an example of a filter selection number stored in a data memory unit.

FIG. 27 when supplying a filter coefficient set;
5 is a flowchart for explaining the operation of the image processing apparatus of FIG.

FIG. 28 is a flowchart illustrating an operation when each element processor calculates a filter coefficient set in the fourth embodiment.

FIG. 29 is a flowchart illustrating an operation when each element processor calculates a filter coefficient set in the fourth embodiment.

FIG. 30 is a block diagram showing a configuration of a fifth embodiment of the image processing apparatus of the present invention.

FIG. 31 is a flowchart illustrating an operation of the image processing apparatus of FIG. 30 when each element processor calculates a filter selection number.

FIG. 32 is a block diagram showing a configuration of a sixth embodiment of the image processing apparatus of the present invention.

FIG. 33 is a diagram showing a configuration of a seventh exemplary embodiment of the present invention.

FIG. 34 is a diagram showing a configuration of an eighth example of the present invention.

35 (A) to (D) are views showing GUI images displayed on a monitor by the personal computer (FIG. 34).

FIG. 36 is a flowchart showing a process of the image data processing system shown in FIG. 34;

FIG. 37 is a diagram showing a configuration of a ninth embodiment of the present invention.

FIG. 38 is a flowchart showing a process of the image data processing system shown in FIG. 37;

FIG. 39 is a diagram illustrating a polygonal line function extracted by a personal computer of the image data processing system shown in FIG. 37;

40 is a flowchart showing a program of the DSP (FIG. 37) for realizing the non-linear processing by performing a linear operation for each of N regions.

FIG. 41 is a diagram illustrating a configuration example of a chroma key device that performs analog processing.

FIG. 42 is a diagram illustrating a configuration example of a chroma key device that performs digital processing.

FIG. 43 is a diagram showing a configuration of a tenth embodiment of the present invention.

FIG. 44 is a diagram showing data input or output to the DSP shown in FIG. 43.

FIG. 45 is a diagram exemplifying a GUI image for setting a background color of chroma key processing displayed on a monitor by a personal computer of the image data processing system (FIG. 43).

46 is a diagram exemplifying processing of a chroma key processing program for a DSP generated by a personal computer of the image data processing system (FIG. 43).

47 is a flowchart illustrating the contents of a chroma key processing program executed by a DSP element processor (FIG. 32 and the like) generated by the personal computer of the image data processing system (FIG. 43).

FIG. 48 is a flowchart showing a chroma key process by the image data processing system (FIG. 43).

FIG. 49 is a first diagram showing an outline emphasis process by the image data processing system (FIG. 37) shown as the eleventh embodiment.

FIG. 50 is a second diagram showing the outline emphasis processing by the image data processing system (FIG. 37) shown as the eleventh embodiment.

FIG. 51 shows a luminance signal Y and a chroma signal C in an outline emphasis process by the image data processing system (FIG. 37).
G used to set a function that emphasizes b and Cr
FIG. 3 is a diagram illustrating a UI image.

FIGS. 52 (A) to 52 (D) show GUI screens used for setting characteristics of a non-linear conversion process in a level-dependent process or a crispening process in an outline emphasis process by the image data processing system (FIG. 37). FIG.

FIGS. 53A to 53C are diagrams showing GUI screens used for setting characteristics of a filtering process in the contour emphasizing process by the image data processing system (FIG. 37).

FIG. 54 is a flowchart showing an outline emphasis process by the image data processing system (FIG. 37) shown as the eleventh embodiment.

FIG. 55 is a diagram illustrating the content of horizontal filtering processing by an FIR filter performed using the image data processing system (FIG. 37) illustrated as the twelfth embodiment;

FIG. 56 is a diagram showing the contents of horizontal and vertical filtering processing by an FIR filter performed using the image data processing system (FIG. 37) shown as the twelfth embodiment.

FIGS. 57A to 57C are diagrams showing GUI screens used for setting characteristics of the filtering process in the filtering process by the FIR filter by the image data processing system (FIG. 37).

FIG. 58 shows the processing contents (S36,
It is a figure which shows S37).

FIG. 59 is a first flowchart showing the processing of the DSP in the twelfth embodiment.

FIG. 60 is a second flowchart showing the processing of the DSP in the twelfth embodiment.

FIG. 61 is a flowchart showing a filtering process by an FIR filter using the image data processing system shown as the twelfth embodiment.

FIG. 62 is a first diagram illustrating the granular noise removal processing according to the thirteenth embodiment of the present invention;

FIGS. 63 (A) to (E) are second diagrams showing the granular noise removal processing in the thirteenth embodiment of the present invention.

FIG. 64 is a diagram showing a configuration of an image data processing system shown as a thirteenth embodiment of the present invention.

FIG. 65 is a diagram showing data input / output to / from the DSP shown in FIG. 64;

FIG. 66 is a diagram showing a GUI image displayed on a monitor by the personal computer of the image data processing system shown in FIG. 64 in order to set a noise component separation point.

FIG. 67 is a diagram illustrating an operation of the image data processing system illustrated as the thirteenth embodiment of the present invention.

FIG. 68 is a flowchart showing an operation of the image data processing system shown as the thirteenth embodiment of the present invention;

FIG. 69 is a diagram illustrating an image data processing system (FIG. 3) for setting an effect area shown as a fourteenth embodiment of the present invention.
64 is a diagram showing a GUI image for setting an effect area displayed on the monitor by the personal computer of FIG. 7, FIG. 43, and FIG. 64).

FIG. 70 is a first diagram illustrating processing of a DSP program generated by a personal computer of the image data processing system (FIGS. 37, 43, and 64) illustrated as the fourteenth embodiment;
FIG.

71 shows S432 and S4 of programs 1 and 2 (FIG. 70) when the rectangular area shown in example 1 of FIG. 69 is set;
FIG. 42 is a flowchart showing a process of determining whether or not the area is within the effect area in 42 and a process of outputting data according to the determination result.

72 shows S432 and S44 of programs 1 and 2 (FIG. 70) when the circular area shown in example 2 of FIG. 69 is set;
A determination process of whether or not it is within the effect area in 2;
FIG. 11 is a flowchart illustrating a data output process according to a determination result.

FIG. 73 is a flowchart showing an operation of the image data processing system (FIGS. 37, 43, and 64) in the fourteenth embodiment.

FIG. 74 is a diagram showing a configuration of an image data processing system shown as a fifteenth embodiment of the present invention.

FIG. 75 is a diagram showing an outline of processing of an image data processing system shown as a fifteenth embodiment of the present invention;

FIG. 76 is a diagram showing a GUI image for effect processing selection displayed on the display device by the personal computer.

FIG. 77 is a flowchart showing a process A started in the processes of S54, S68, and S70 shown in FIG. 76;

FIG. 78 is a diagram exemplifying a GUI image for continuous zoom processing displayed on the display device (FIG. 74) in the processing of S540 shown in FIG. 77;

FIG. 79 is a diagram exemplifying a GUI image for interactive processing displayed on the display device (FIG. 74) in the processing of S540 shown in FIG. 77;

FIG. 80 is a flowchart showing a process B started in the process (FIR filter) of S56 shown in FIG. 76;

FIGS. 81 (A) and (B) show S560 shown in FIG. 80;
FIG. 75 is a diagram illustrating a GUI image displayed on the display device (FIG. 74) in the processing of FIG.

FIG. 82 is a flowchart showing a process C activated in the processes of S60, S64, and S66 shown in FIG. 76;

83 (A) and (B) show S600 shown in FIG. 82.
FIG. 75 is a diagram illustrating a GUI image for color correction (γ correction) processing displayed on the display device (FIG. 74) in the processing of FIG. 74.

84 (A) to (C) show S600 shown in FIG. 82.
FIG. 75 is a diagram exemplifying a GUI image for filtering processing (LAP retouch) processing displayed on the display device (FIG. 74) in the processing of FIG.

85 is a process for converting the number of colors (pos) displayed on the display device (FIG. 74) in the process of S600 shown in FIG. 82;
FIG. 11 is a diagram illustrating a GUI image for processing.

FIG. 86 is a flowchart showing a filter process executed by the DSP of the image data processing system (FIG. 74) in the fifteenth embodiment;

FIG. 87 is a diagram illustrating a step function used in the color number conversion process.

FIG. 88 is a flowchart showing a color conversion process executed by the DSP of the image data processing system (FIG. 74) in the fifteenth embodiment.

FIG. 89 is a diagram showing a GUI image for input / output image selection of the image data processing system (FIG. 74) shown as the fifteenth embodiment.

FIG. 90 is a diagram showing a GUI image for setting the position of the main image.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Operation device, 2-6 ... Parallel processor, 21 ... Input pointer, 22 ... Input SAM part, 23 ... Data memory part,
24 ALU array unit, 25 Output SAM unit, 26 Output pointer, 27, 27a, 27b, 27c, 27d ...
Program control unit, 28, 28a, 29 ... memory, 30
... Element processor, 7 ... Image data processing device, 60 ... Selector circuit, 62 ... Memory circuit, 8-12 ... Image data processing system, 70 ... Input device, 72 ... Personal computer, 74 ... Image source, 76 ... Image monitor, 78
₁ ... foreground image source, 78 ₂ ... background image source, 80 ...
DSP, 82, 82 ₁ , 82 ₂ ... Frame memory, 84
... input image selector, 86 ... output monitor selector, 14
... input unit, 140 ... hard disk drive, 142 ... VT
R device, 146... NTSC image signal source, 148, 152
.. A / D conversion circuit, 154 VGA device, 16 output unit, 160 HD monitor, 162 D1 monitor.

Claims (9)

[Claims] An input image display means for displaying an input image indicating input / output characteristics between input image data and output image data; and input means for inputting the input image data according to the displayed input image. A designated data receiving means for accepting designated data to be designated; an input / output characteristic extracting means for extracting the input / output characteristics from the received designated data; and an input / output for displaying an input / output characteristic image indicating the extracted input / output characteristics Characteristic image display means; image data processing for processing the input image data to generate the output image data so that the input image data and the output image data have a relationship indicated by the extracted input / output characteristics Image processing apparatus having means. 2. The input image display means displays a graph of initial values of the input / output characteristics, and the designated data receiving means adds at least a passing point of the displayed curve of the graph and a passing point to be added. First designation data for specifying the position on the graph of the above, change of the position of the added passing point, second designation data for specifying the changed position of the passing point to be changed, and the added passing And accepting third designated data for designating point deletion, wherein the input image display means changes the input / output characteristic graph based on the accepted first to third designated data. Item 2. The image processing device according to Item 1. 3. An input / output characteristic data generating means for generating input / output characteristic data for associating the input image data with the output image data according to the extracted input / output characteristics, wherein the image data processing means comprises: The image processing apparatus according to claim 1, wherein a value of the input image data is converted into a value of the output image data by a memory mapping method based on the generated input / output characteristic data. 4. The image data processing means generates the output video data by processing the input video data based on a set program, and the image data processing means based on the extracted input / output characteristics. The image processing apparatus according to claim 1, further comprising: a program generating unit configured to generate a program for generating the output image data from the input image data. 5. An image processing apparatus according to claim 4, wherein said image data processing means is a linear array type multi-parallel processor controlled by SIMD. 6. An input image indicating input / output characteristics between input image data and output image data is displayed, and input data is input according to the displayed input image, and specification data for specifying the input / output characteristics is received. Extracting the input / output characteristics from the received specified data, displaying an input / output characteristics image indicating the extracted input / output characteristics, the input image data and the output image data being the extracted input / output characteristics An image processing method for processing the input image data to generate the output image data such that the relationship shown by 7. A graph of an initial value of the input / output characteristics is displayed, a passing point of a curve of the displayed graph is added, and first designated data for designating a position of the passing point on the graph, At least the second specified data for specifying the change of the position of the added passing point, the changed position of the changed passing point, and the third specified data for specifying the deletion of the added passing point are accepted. 7. The graph of the input / output characteristics is changed based on the received first to third specified data.
The image processing method according to 1. 8. An input / output characteristic data which associates the input image data with the output image data in accordance with the extracted input / output characteristic, and based on the generated input / output characteristic data, a memory mapping method is used. 7. The image processing method according to claim 6, wherein a value of the input image data is converted into a value of the output image data. 9. The output image data is generated by processing the input image data based on a set program, and the output image data is generated from the input image data based on the extracted input / output characteristics. The image processing method according to claim 6, wherein a program is created, the generated program is executed, the input image data is processed, and the output image data is generated.