JPH10124656A - Image processor and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate the processing of an image by a processor in an SIMD (single instruction multiple data stream) form. SOLUTION: Input data for one pixel are supplied to each element processor 31. Data supplied to the prescribed element processor 31 is defined as R0 , and data supplied to the element processors 31 which are left-hand, left-hand next to it, right-hand, right-hand next to is, and right-hand next to it are respectively defined as R-1 , R-2 , R+1 , R+2 , and R+3 . The element processor 31 uses a preliminarily supplied filter coefficient set (FC1, FC2, FC3, and FC4), and outputs R-1 ×FC1+R0 ×FC2+R+2 ×FC3+R+3 ×FC4 or R-2 ×FC1+R0 ×FC2+R+1 ×FC3+ R+2 ×FC4 as output data according to the position relation of the pixels corresponding to the output data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing method, and more particularly, to a method of supplying image data to a plurality of element processors via an input bus and controlling the plurality of element processors by SIMD. The present invention relates to an image processing apparatus and method for performing image processing in parallel.

[0002]

2. Description of the Related Art Many image displays (displays) such as television receivers use a CRT (Cathode Ray Tube). In such a display, when an image signal is handled in an analog manner corresponding to various image systems and an image is displayed, the display is often handled by changing a horizontal scanning frequency.

On the other hand, when image signals are handled digitally, the resolution of the images differs according to the broadcast transmission system such as NTSC or PAL. The number differs for each broadcast transmission system. Also, there are various broadcast transmission systems including HDTV, and the standards for the number of pixels (resolution) are various. Therefore, in a system that performs digital processing on image data, in order to support all of these transmission methods, the number of pixels is set to an “interpolation filter”.
Needs to be converted.

Next, an example of an interpolation filter for converting the number of pixels of an image will be described.

First, the enlargement or reduction of an image and the conversion of the sampling frequency (the number of pixels) will be described.

[0006] Both the enlargement or reduction of an image and the conversion of the sampling frequency (number of pixels) of the image (conversion between image standards having different resolutions) are performed with respect to each pixel position of the original image in the original image. This is realized by performing an operation for obtaining data of a pixel that did not exist. Therefore, the above-described two processes can be performed by using an interpolation filter that performs the same calculation operation.

FIG. 18 shows an example of a part of an original image. The circles in the figure represent the positions of the pixels. This portion includes eight pixels in the horizontal direction and six pixels in the vertical direction (the number of pixels is set to a small value here for convenience).

Next, a case where the original image is enlarged, for example, by (10/7) will be described. The magnification is expressed not by the area but by the length ratio. When the image of FIG. 18 is enlarged, the pixel arrangement (that is, the pixel interval, etc.) is kept the same as in FIG. 18 without changing the display image standard. When the enlargement process is performed in this manner, the resulting image is as shown in FIG. In this case, the magnification is 1.42
9 (= 10/7), the length of one side of the image is
1.429 times, the number of pixels increases about 1.429 ² times.

For example, in the horizontal direction (horizontal scanning direction), the number of pixels in the original image is 8, but after enlargement, 11 or 12 (8 × 10/7 = an integer close to 11.429) pixels become. Therefore, since the positional relationship of each pixel corresponding to the same part of the image in the similar image after enlargement is different from the positional relationship in the original image, the value of the data (expressing luminance and color) of each pixel after enlargement is Will be different from that of the original image.

FIG. 20 shows the positional relationship between horizontal pixels in an original image and an enlarged image when the image is enlarged at a magnification of (10/7).

In the figure, the upper Ri (i = 1, 2,...)
Represents pixel data of the original image, and Qi (i
= 1, 2,...) Represents the data of the interpolated pixel after the enlargement. The pixels corresponding to Ri are arranged at an interval (10/7) times the interval between the pixels corresponding to Qi. Although FIG. 20 shows only the state of enlargement in the horizontal direction, the same applies to the vertical direction, and a description thereof will be omitted.

The value of the data of each pixel after the enlargement is interpolated from the values of the pixel data of some surrounding original images according to the correspondence relationship with the position of each pixel of the original image as shown in FIG. It is calculated by performing a filter operation, that is, a convolution operation of an interpolation function (described later).

Next, consider a case where the sampling frequency is increased by, for example, (10/7) without changing the size of the image.
This sampling frequency conversion is equivalent to conversion to an image standard whose resolution is higher by (10/7) times. That is, the number of pixels in the horizontal direction is changed to (10/7) times. In this case, as shown in FIG. 21, the original image of FIG. 18 is converted into an image having one-dimensionally about 1.429 times the number of pixels, that is, having an area density of 1.429 ² times.

The correspondence between each pixel in FIG. 18 and each pixel in FIG. 19 and the correspondence between each pixel in FIG. 18 and each pixel in FIG. 21 are as shown in FIG. Therefore, the operation for converting to an image standard having a large number of pixels is performed in the same manner as the above-described operation for enlarging an image.

Next, the original image shown in FIG.
3) The case of reducing the size by a factor of 2 will be described.

When the image is reduced, since the standard of the image is not changed, the arrangement of the pixels in the reduced image, that is, the pixel interval becomes the same as the original image shown in FIG.

FIG. 22 shows the original image of FIG.
3) shows an image reduced by a factor of two. In this case, the magnification is 0.769 (= 10/13).
The length of the side is reduced to 0.769 times, and the number of pixels forming the reduced screen is reduced to about 0.769 ² .

For example, in the original image, the number of pixels in the horizontal direction is 8, but in the reduced image, the number of pixels in the horizontal direction is an integer close to 6 or 7 (8 × 10/13 = 6.154). )become. Accordingly, since the positional relationship of each pixel corresponding to the same portion of the image in the reduced similar image is different from the positional relationship of each pixel in the original image, data (expressing luminance and color) of each pixel after reduction is obtained. Is different from that of the original image.

FIG. 23 shows the positional relationship between pixels in the horizontal direction between the original image and the reduced image when the image is reduced by a factor of (10/13).

In the figure, the upper Ri (i = 1, 2,...)
Represents pixel data of the original image, and Qi (i
= 1, 2,...) Represents the data of the interpolated pixel after reduction. The pixels corresponding to Ri are arranged at an interval (10/13) times the interval between the pixels corresponding to Qi. Although FIG. 23 shows only the state of reduction in the horizontal direction, the same applies to the vertical direction, and a description thereof will be omitted.

The data value of each pixel after reduction is calculated by interpolation filter calculation from the pixel data values of several surrounding original images according to the correspondence relationship with each pixel of the original image as shown in FIG. That is, it is calculated by performing a convolution operation of the interpolation function.

Next, consider the case where the sampling frequency is increased, for example, by (10/13) without changing the size of the image. This sampling frequency conversion has a resolution of (10/13)
This is equivalent to converting to an image standard that is twice as low. That is, the number of pixels is changed to (10/13) times. In this case, the original image of FIG. 18, as shown in FIG. 24, the one-dimensional and is converted to about 0.769 times the number of pixels, i.e., an image having 0.769 ² times the surface density.

The correspondence between each pixel in FIG. 18 and each pixel in FIG. 22 and the correspondence between each pixel in FIG. 18 and each pixel in FIG. 24 are as shown in FIG. The calculation operation for converting to a low-resolution image standard is performed in the same manner as the calculation operation for image reduction described above.

As described above, when an image is enlarged or reduced and the sampling frequency (the number of pixels) is converted, an interpolation filter for calculating pixel data at a position not existing in the original image is required. .

Next, the operation performed in the interpolation filter will be described.

As shown in FIG. 25, the sampling interval of the original image is S, and the position (phase) P away from the pixel R of the original image is the position of the pixel Qi generated by interpolation (interpolation point). ), The value of the pixel Qi is calculated by a convolution operation on the pixel value R of the surrounding original image.

According to the "sampling theorem", when ideal "interpolation" is performed, the sinc function as shown in equation (1) and FIG. The convolution operation from the pixel of to the pixel in the future for infinite time is performed. f (x) = sinc (π × x) = sin (π × x) / (π × x) (1)

Here, π represents the pi.

However, in practice, it is necessary to calculate an interpolated value within a finite time, so an interpolation function that approximates a sinc function within a finite range is used.

As an approximation method, a nearest neighbor approximation method, a bilinear approximation method, a Cubic approximation method and the like are known.

In the nearest neighbor approximation method, data of one pixel after interpolation is calculated from data of one pixel of the original image using an interpolation function as shown in equation (2) and FIG. 26 (B). . Note that the variable x in Equation (2) and FIG.
It is assumed that the displacement in the horizontal direction from the pixel position of the original image represents an amount normalized by the sample interval of the original image.

(Equation 1)

In the bilinear approximation method, data of one pixel after interpolation is calculated from data of two pixels of the original image by using an interpolation function as shown in equation (3) and FIG. 26 (C). . Note that the variable x in Equation (3) and FIG.
It is assumed that the displacement in the horizontal direction from the pixel position of the original image represents an amount normalized by the sample interval of the original image. The bilinear approximation method is well known as linear interpolation, and a weighted average is calculated.

(Equation 2)

In the Cubic approximation method, data of one pixel after interpolation is calculated from data of four pixels of the original image by using an interpolation function as shown in equation (4) and FIG. 26 (D). The variable x in equation (4) and FIG.
Represents the amount of displacement in the horizontal direction from the pixel position of the original image normalized by the sample interval of the original image.

(Equation 3)

These convolution operations can be performed using a so-called FIR digital filter. In this case, the center of the interpolation function is set to the interpolation point, and a value obtained by sampling the interpolation function at the sampling points of the original image nearby by a predetermined number of pixels is used as an interpolation filter coefficient set.

For example, in the case where the interpolation is performed by the bilinear approximation method, when the phase P is 0.0, the two weights (filter coefficients) constituting the filter coefficient set are 1.0 and 0.0. , A coefficient set that directly outputs the pixel data value of the original image at the same position.

When the phase P is 0.5, the two filter coefficients are 0.5 and 0.5, and when P is 0.3, they are 0.7 and 0.3.

When the interpolation operation is performed by the Cubic approximation method, when the phase P is 0.0, the four weights (filter coefficients) constituting the filter coefficient set are 0.0, 1.
The coefficient set is 0, 0.0, and 0.0, and is a coefficient set that directly outputs the data value of the original image pixel at the same position.

When the phase P is 0.5, the four filter coefficients are -0.125, 0.625, 0.62
5, and -0.125, and when P is 0.3, -0.063, 0.847, 0.36
3, and -0.147.

At this time, since the phase P with the pixel of the original image is different for each interpolation point for calculating data,
A plurality of sets of filter coefficients corresponding to different phases are required.

Next, a conventional interpolation filter operation device will be described.

FIG. 27 shows an example of the configuration of an arithmetic unit using an FIR digital filter for performing an interpolation operation, that is, a convolution operation of an interpolation function. The arithmetic device in FIG. 27 performs a convolution operation using the Cubic approximation method.

The coefficient memory 1 holds a plurality of filter coefficients corresponding to each interpolation point (or each phase), and stores four filter coefficients corresponding to a filter selection signal supplied from a predetermined device (not shown). Filter coefficients FC1, FC2, FC
3 and FC4 are output to multipliers 3-1 to 3-4, respectively.

The register 2-1 holds data supplied from a predetermined device (not shown) and outputs the data to the register 2-2 in response to a control signal. Register 2-2, 2-3
Holds the data supplied from the registers 2-1 and 2-2, respectively, and stores the data in the registers 2-3 and 2 according to the control signal.
-4. The register 2-4 holds the data supplied from the register 2-3.

The registers 2-1 to 2-4 are connected in series and operate as a four-stage shift register. To this shift register, a horizontally scanned input image data sequence is sequentially input in word units,
The pixel data of one original image is stored.

In the Cubic approximation method, the data of the interpolation point is calculated from the data of a total of four pixels, that is, the left and right two pixels sandwiching the interpolation point, using the four-stage shift register.

The multiplier 3-i (i = 1,..., 4)
The value held in the register 2-i is multiplied by the value (filter coefficient) FCi supplied from the coefficient memory 1 and the operation result is output to the adder 4.

The adder 4 calculates the sum of the values supplied from the multipliers 3-1 to 3-4 and outputs the result as an interpolated value.

As described above, the data and the filter coefficients input to the register 2-1 in time series are multiplied by the multiplier 3
-1 to 3-4 and a product-sum operation in the adder 4
The data of the interpolation points, which are the calculation results, are output in chronological order.

Next, the operation of the arithmetic unit shown in FIG. 27 when the original image is enlarged by (10/7) by Cubic approximation will be specifically described.

In the image magnification of (10/7) times, as described above, in the horizontal direction, the positional relationship of each pixel with respect to each interpolation point is set as shown in FIG. do it.

FIG. 28 shows the values of each part of the arithmetic unit of FIG. 27 in each cycle.

In a device which performs hardware processing as shown in FIG. 27, latency (delay for realizing high-speed operation) usually occurs due to pipeline processing in the multiplication and summation operations. For convenience, it is assumed here that there is no latency.

In the first cycle of FIG. 28, input data R1 as image data for one pixel of an original image is supplied from a predetermined device. At this time, the registers 2-1 to 2-4 store data Rm0, which is one before the input data R1,
Data Rm1 two before the input data R1, data Rm2 three before the input data R1, and input data R
The data Rm3 four data before four are held.

At this time, since the value of the control signal is "H", the registers 2-1 to 2-4 shift the data at the timing of the next rising edge of the clock.

Since each data is shifted, the second
In the cycle, registers 2-1 to 2-4 store R
1, Rm0, Rm1, and Rm2 are held. At this time, since the value of the control signal is “H”, the registers 2-1 to 2-4 shift the data at the timing of the next rising edge of the clock.

Since each data is shifted, the third
In the cycle, registers 2-1 to 2-4 store R
2, R1, Rm0 and Rm1, respectively. At this time, since the value of the control signal is “H”, the registers 2-1 to 2-4 shift the data at the timing of the next rising edge of the clock.

Similarly, since the data is shifted, the registers 2-1 to 2-
4 holds R3, R2, R1, and Rm0, respectively. Also, Rm0, R1, R2, R in FIG.
Filter selection signal P indicating the phase of interpolation value Q1 for
0 is supplied to the coefficient memory 1. As described above, the filter selection signal is supplied corresponding to the phase P of the output signal Qi.

In this case, Ra in FIG.
, Rb corresponds to R1, Rc corresponds to R2, Rd corresponds to R3, and Q in FIG. 25 corresponds to the interpolation value Q1.

The coefficient memory 1 stores ten types of filter coefficient sets shown in FIG. 29, and four coefficients FC1, FC2, FC3, and FC3 according to the supplied filter selection signal Pi.
Select and output FC4. In the case of (10/7) times image enlargement, the phase of the pixel in the interpolation operation is as shown in FIG.
Since there are only 10 types as shown in FIG.
Have as many filter coefficient sets as their phases.

That is, the filter selection signal Pi corresponds to a filter coefficient set when the phase is i / 10, out of ten types of phases corresponding to each position where S is divided into ten equal parts in FIG. . The decimal point expression coefficient (filter coefficient) in FIG. 29 is a value calculated by substituting the phase corresponding to the filter selection signal Pi into x in Expression (4), and the 8-bit expression coefficient is the decimal point expression coefficient. Is limited to 8 bits in word length (here, the maximum amplitude is set to 128).

In this case, since the filter selection signal is P0 in the coefficient memory 1, the filter coefficient set (0.0, 1.0, 0.0, 0.0) corresponding to the phase P0 in FIG.
(In the case of 8-bit representation, (0,128,0,0)) is
These are output to the multipliers 3-1 to 3-4 as four filter coefficients FC1, FC2, FC3, and FC4, respectively.

Then, the above-described product-sum operation is performed by the multipliers 3-1 to 3-4 and the adder 4, and the operation result is output as output data Q1.

At this time (in the fourth cycle), since the value of the control signal is "L", in the next clock,
The registers 2-1 to 2-4 do not output the held data.

In the fifth cycle, register 2-1
Nos. To 2-4 continuously hold the data held in the fourth cycle. At this time, R in FIG.
A filter selection signal P7 indicating the phase of the output data Q2 for m0, R1, R2, and R3 is supplied to the coefficient memory 1.

In this case, as shown in FIG.
Since 1 and Q1 have the same phase, and the interval between Q1 and Q2 is 7/10 of the interval S between R1 and R2, the phase is 7/10, and the filter selection signal P7 is supplied.

Then, since the filter selection signal is P7, the coefficient memory 1 sets the filter coefficient set (-0.147, 0.363,
0.847, -0.063) (in the case of 8-bit representation,
(−19, 46, 108, −8)) as the four filter coefficients FC1, FC2, FC3, and FC4 as multiplier 3-
1 to 3-4.

The multiplier-sum operation is performed by the multipliers 3-1 to 3-4 and the adder 4, and the operation result is output as output data Q2.

When the pixels of the original image used to calculate the output data Q1 in the fourth cycle and the output data Q2 in the fifth cycle are the same as in this case, the value of the control signal in the fourth cycle is Is set to “L”, the registers 2-1 to 2-4 are not shifted when shifting from the fourth cycle to the fifth cycle.

At this time (in the fifth cycle), since the value of the control signal is “H”, the registers 2-1 to 2-
No. 4 shifts the data at the timing of the next rising edge of the clock.

Next, in the sixth cycle, the registers 2-1 to 2-4 store R4, R3, R2 and R1.
Are respectively held. Further, R4, R in FIG.
3, a filter selection signal P4 indicating the phase of the output data Q3 with respect to R2 and R1 is supplied to the coefficient memory 1.

The current phase is the previous phase 7/10.
Is added to 7/10, and becomes 14/10. Since the phase (= 10/10) corresponding to one original image data is subtracted, the current phase is 4/10 (= 7/10 + 7). / 1
0-10 / 10).

That is, the phase originally changes by 7/10 every one cycle. Then, since the integer is treated as a data delay, the phase is eventually subjected to a modulo operation.

The coefficient memory 1 stores the filter selection signal P4
Therefore, the filter coefficient set (−0.096, 0.744, 0.496, −0.1) corresponding to P4 in FIG.
44) (In the case of the 8-bit representation, (-12, 95, 63,
−18)) with four filter coefficients FC1, FC2, F
Output to multipliers 3-1 to 3-4 as C3 and FC4.

Then, the multiplier-sum operation is performed by the multipliers 3-1 to 3-4 and the adder 4, and the operation result is output as output data Q3.

At this time, since the value of the control signal is "H", the registers 2-1 to 2-4 shift the data at the timing of the next rising edge of the clock.

In the same manner, as shown in FIG. 28, the process proceeds, and output data Qi is sequentially output.

When the number of pixels of an image is converted using the above-described apparatus, the input data rate and the output data rate change due to a change in the number of pixels.

For example, in the conversion in which the number of pixels is increased as described above, although the output data rate is constant, the supply of the input data string may be stopped as in the fifth cycle in FIG. is there. Further, in the case of conversion in which the number of pixels is reduced, the output of output data may be stopped although the input is constant.

Therefore, in practice, the data rate is kept constant by providing a buffer memory for temporarily storing the input / output data of the arithmetic unit shown in FIG.

As described above, the enlargement or reduction of the image and the conversion of the resolution are performed by hardware (that is, by using an electronic circuit configured corresponding to each operation in the processing). ing.

However, in the case where a device for enlarging or reducing an image and converting the resolution is used in terms of hardware as described above, it is desired to simultaneously perform various image processing operations at the time of image conversion. In order to perform television signal processing, noise elimination, and the like, a separate device corresponding to each process is required. Therefore, a plurality of devices are required, and it is difficult to reduce the scale of the entire device. Have.

Thus, for example, Japanese Patent Application Laid-Open No. 8-123683
As described in Japanese Unexamined Patent Publication No.
A method has been considered in which the above-described computation is performed in software using a parallel processor of a truncation multiple data stream (traffic multiple data stream) type.

FIG. 30 shows a configuration example of such a parallel processor. This parallel processor includes an input pointer 21, an input SAM (serial access memory) unit 2
2. Data memory unit 23, ALU array unit 24, output S
It comprises an AM unit 25, an output pointer 26, and a program control unit 27.

The input SAM unit 22, the data memory unit 23,
The ALU array unit 24 and the output SAM unit 25 constitute a group of element processors parallelized in a linear array (linear array) type. These element processors 31
In accordance with one program of the program control unit 27, it is controlled in an interlocked manner (that is, SIMD controlled). The program control unit 27 includes a program memory,
It has a sequence control circuit or the like that advances the program, and generates various control signals according to the program written in advance in the program memory to control the various circuits.

The input SAM 22, the data memory 23, and the output SAM 25 are mainly composed of memories. Although not described in detail, in the apparatus of FIG. 30, it is assumed that “row” address decoders for these memories are included in the program control unit 27.

The parallelized element processors 31 (for a single element) correspond to the hatched portions in FIG. 30, and a plurality of element processors 31 are arranged in the horizontal direction in the figure. That is, only the hatched portions in FIG. 30 have components corresponding to one processor.

Next, the operation of the linear array type parallel processor for image processing of FIG. 30 will be described.

The input data (image data for one pixel) supplied to the input terminal DIN is supplied to the input SAM unit 22.

The input pointer 21 stores the value “H” of 1 for only one element processor 31 for one input data.
It outputs a bit signal, that is, an input pointer signal (SIP). Then, the element processor 31 specified by the value “H”
Is input to the input SAM unit 22 (input SAM cell).

The designation of the element processor 31 that supplies data by the input pointer signal sequentially moves from the leftmost element processor 31 to the rightmost element processor 31 in the figure at every clock of the input data. Are sequentially supplied from the input SAM unit 22 (input SAM cells) of the leftmost element processor 31 to the input SAM cells of the rightmost element processor 31.

Since the number of the element processors 31 is designed to be equal to or more than the number of pixels H in one horizontal scanning period of the image signal, the pixel data for one horizontal scanning period of the image signal can be stored in the input SAM unit 22. it can. Such an input operation is
It is repeated every horizontal scanning period.

The program control unit 27 receives the data of the image signal for one horizontal scanning period in the input SAM unit 22 in this manner.
Each time the data is accumulated, the input SAM unit 22, the data memory unit 23, the ALU array unit 24, and the output SAM unit 25 are SIMD-controlled as described below to execute processing.

This program control is repeated every horizontal scanning period. Therefore, it is possible to process a program corresponding to the number of steps calculated by dividing the time corresponding to the horizontal scanning period by the instruction cycle period of the processor. Because of the SIMD control, the following operations are similarly executed in parallel in all the element processors 31.

The input data for one horizontal scanning period stored in the input SAM unit 22 is transferred from the input SAM unit 22 to the data memory unit 23 as necessary in the next horizontal scanning period, and is used for subsequent arithmetic processing. used.

The input SAM unit 22 to the data memory unit 23
In the transfer of data to the
Is input SA based on the input SAM read signal (SIR).
After selecting and accessing data of a predetermined bit of the M section 22, a memory access signal (SWA) is issued, and the data is written to a predetermined memory cell (described later) of the data memory section 23.

Next, the program control unit 27 controls the ALU array unit 2 of each element processor 31 according to the program.
4 is supplied with the data held in the data memory unit 23 of the element processor 31 and causes the arithmetic or logical operation to be performed on the data. Then, the calculation result is written to a predetermined address of the data memory unit 23.

Note that all the operations in the ALU array unit 24 are performed in units of bits, so that the processing proceeds one bit per cycle. For example, it takes at least eight cycles to perform a logical operation between 8-bit data. In addition, it takes at least 9 cycles to perform addition of 8-bit data. 8
When multiplying bits of data, the multiplication is 64
Since this is equivalent to one bit addition, it takes at least 64 cycles.

The element processor 31 is connected to a nearby element processor 31 and can perform inter-processor communication. However, the neighboring element processors 31
To access the data memory unit 23 of the SIM
Due to the D control, for example, the element processor 31 on the right
, All the element processors 31 access the data memory section 23 of the element processor 31 on the right.

Note that such operation is performed by the FIR
There is no particular problem in realizing a digital filter. When reading data from the element processor 31 that is not directly connected, the number of program steps is slightly increased.
Data is read out by repeating communication between nearby processors.

Using such communication, a horizontal FIR digital filter operation of an image can be realized using data held by the neighboring element processors 31.

In such a parallel processor, data of a pixel at the same position in the horizontal direction is transferred to a predetermined one element processor 31 in all horizontal scanning periods.
When the data is transferred from the input SAM unit 22 to the data memory unit 23, the address for storing the data is changed for each horizontal scanning period, so that the input data of the past horizontal scanning period can be changed. The data can be held in the data memory unit 23 until the subsequent horizontal scanning period. By doing so, the data necessary for the calculation of the FIR digital filter in the vertical direction of the image can be sequentially stored in the data memory unit 23.

In this manner, each element processor 31 stores a predetermined continuous number of pixel data in the vertical direction (the direction perpendicular to the horizontal scanning direction) in the data memory unit 2.
3 to realize a vertical FIR digital filter operation.

When the calculation assigned to one horizontal scanning period is completed as described above, the data calculated during the horizontal scanning period during the horizontal scanning period is output SA.
The data is transferred to the M unit 25.

As described above, during one horizontal scanning period, the transfer of the input data accumulated in the input SAM unit 22 to the data memory unit 23, the calculation by the ALU array unit 24, and the data transmission to the output SAM unit 25 Is executed according to a SIMD control program in units of bits.
This process is sequentially repeated in units of the horizontal scanning period.

The output data transferred to the output SAM unit 25 is the output data in the next horizontal scanning period.
It is output from the AM unit 25.

As described above, the input processing for writing the input data to the input SAM section 22, the transfer of the input data accumulated in the input SAM section 22 to the data memory section 23 by the program control section 27, and the ALU array section 24 Three types of processing are performed for each input data: a calculation processing for transferring the output data to the output SAM unit 25, and an output processing for outputting the output data from the output SAM unit 25. Note that these three processes are executed as pipeline processes in units of one horizontal scanning period of the image signal.

Focusing on the input data for one horizontal scanning period, the time corresponding to one horizontal scanning period elapses in each of the three processes for the input data. Although it takes a corresponding time, since the three processes are executed in parallel as pipeline processes, the process can be performed in a time corresponding to one horizontal scanning period per input data for one horizontal scanning period on average. .

[0108]

However, it is possible to realize a general FIR digital filter as described above, but when enlarging or reducing an image for which interpolation calculation is required (similarly, resolution ), The interpolation operation is a kind of FIR digital filter,
The number of data held in the input SAM unit 22 and the output SA
Since the number of data output to the M unit 25 is different, the input S
In the AM unit 22 or the output SAM unit 25, the input data Ri or the output data Qi is not densely arranged.

Therefore, when the element processor 31 acquires input pixel data necessary for the interpolation processing from a predetermined number of other element processors 31, the element processor 31
And the positional relationship with other element processors 31 is different for each element processor 31, so that all the element processors 3
1 has a problem that it is difficult to obtain necessary data in a SIMD parallel processor in which the same operation is performed.

For example, in the Cubic approximation, a convolution operation is required for four of continuous input data. For example, when the image is enlarged by (10/7) times, as shown in FIG. 31, the input data Ri is not densely arranged, and therefore, for example, the input data R1 and R2 required when calculating the output data Q3. , R3, R4
R1, R3, and R4 are adjacent to the left two and to the right one from the element processor 31 that calculates the output data Q3,
And are held by the three element processors 31 adjacent to the right.

On the other hand, of the input data R2, R3, R4, and R5 necessary for calculating the output data Q4, R2, R4, R5
5 is held by the element processors 31 that are immediately adjacent to the left, adjacent to the right, and adjacent to the right.
Also, input data R2, necessary for calculating output data Q5,
R3, R4, and R5 are held in the element processors 31 that are two adjacent left, one adjacent left, one adjacent right, and two adjacent right of the element processor 31 that is the base point.

As described above, the positional relationship between the element processor 31 holding the input data necessary for calculating each output data and the element processor 31 calculating the output data changes for each output data.

FIG. 32 shows a pattern of the element processor 31 holding input data necessary for calculating each output data when the image is enlarged by (10/7). In this case, as shown in FIG. 32, the data is classified into five patterns.

When the above-described parallel processor is used, each element processor 31 calculates output data corresponding to one pixel.
It has the problem that different filter coefficients need to be supplied.

The present invention has been made in view of such a situation, and the type of a pattern of a positional relationship between a peripheral element processor having image data used by a predetermined element processor and the predetermined element processor is minimized. So that
The image data may be supplied to a plurality of element processors and the filter coefficients may be supplied from a predetermined memory, or the filter coefficients may be calculated by the element processors, and the image processing may be performed by the SIMD parallel processor. To make it possible.

[0116]

According to an image processing apparatus of the present invention, a pattern type of a positional relationship between a peripheral element processor having image data used by a predetermined element processor and a predetermined element processor is determined. To minimize
It is characterized in that image data is supplied to a plurality of element processors.

According to a sixth aspect of the present invention, there is provided the image processing method, wherein the type of the pattern of the positional relationship between the peripheral element processor having the image data used by the predetermined element processor and the predetermined element processor is minimized. It is characterized in that image data is supplied to a plurality of element processors.

The image processing apparatus according to claim 7 supplies a filter coefficient set used for interpolation to each of the element processors via the input bus, and the element processor uses the filter coefficient set to convert the image data. It is characterized in that interpolation processing is performed respectively.

According to the image processing method of the present invention, a filter coefficient set used for interpolation is supplied to each element processor via an input bus, and the element processor uses the filter coefficient set to convert the image data. It is characterized in that interpolation processing is performed respectively.

According to a fifteenth aspect of the present invention, a filter coefficient set used for interpolation is supplied to each of the element processors via a circuit different from the input bus, and the element processor uses the filter coefficient set. Thus, the image data is interpolated.

According to the image processing method of the present invention, a filter coefficient set used for interpolation is supplied to each of the element processors via a circuit different from the input bus, and the element processor uses the filter coefficient set. Thus, the image data is interpolated.

According to a twenty-fifth aspect of the present invention, the element processor calculates a filter coefficient set used for interpolation in accordance with the phase information of the image data assigned to the element processor. , And performs interpolation processing of image data.

The image processing method according to claim 31, wherein the element processor calculates a filter coefficient set used for interpolation in accordance with the phase information of the image data assigned to the element processor. , And performs interpolation processing of image data.

In the image processing apparatus according to the first aspect, the type of the pattern of the positional relationship between the peripheral element processor having the image data used by the predetermined element processor and the predetermined element processor is minimized. Supply image data to a plurality of element processors.

According to the image processing method of the present invention, the type of the pattern of the positional relationship between the peripheral element processor having the image data used by the predetermined element processor and the predetermined element processor is minimized. Supplies image data to a plurality of element processors.

In the image processing apparatus according to the present invention, a filter coefficient set used for interpolation is supplied to each of the element processors via an input bus, and the element processor uses the filter coefficient set to generate image data. Are respectively performed.

In the image processing method according to the present invention, a filter coefficient set used for interpolation is supplied to each element processor via an input bus, and the element processor uses the filter coefficient set to generate image data. Are respectively performed.

In the image processing apparatus according to the present invention, a filter coefficient set used for interpolation is supplied to each of the element processors via a circuit different from the input bus, and the element processor uses the filter coefficient set. Then, interpolation processing of the image data is performed.

In the image processing method according to the twenty-fourth aspect, a filter coefficient set used for interpolation is supplied to each of the element processors via a circuit different from the input bus, and the element processor uses the filter coefficient set. Then, interpolation processing of the image data is performed.

In the image processing apparatus according to the twenty-fifth aspect, the element processor calculates a filter coefficient set to be used for interpolation in accordance with the phase information of the image data assigned to the element processor. Each set is used to perform interpolation of image data.

In the image processing method according to the thirty-first aspect, the element processor calculates a filter coefficient set to be used for interpolation in accordance with the phase information of the image data assigned to the element processor. Each set is used to perform interpolation of image data.

[0132]

FIG. 1 shows the structure of an image processing apparatus according to a first embodiment of the present invention.

The input pointer 21 is the element processor 31
Each time, an input pointer signal indicating whether or not to receive input data is output to the input SAM unit 22. Note that this input pointer 21 is, for example,
Input data can be selectively supplied to the element processor 31 in the same manner as described in JP-A-123683.

The input SAM unit 22 has the element processor 31
Each storage device has a storage unit for holding predetermined input data, and stores the input data corresponding to the SIP signal supplied from the input pointer 21. Also, input S
When receiving the SIR signal from the program control unit 27A, the AM unit 22 outputs the held data to the data memory unit 23.

The data memory unit 23 stores the element processor 3
Each memory has a storage unit for holding predetermined data, and upon receiving a SWA signal from the program control unit 27A, stores the data supplied from the input SAM unit 22 or the ALU array unit 24 in the storage unit. When a read access signal (SRAA, SRBA) is received, the data is transferred to A
The data is output to the LU array unit 24.

The ALU array unit 24 includes the element processor 3
An arithmetic unit (ALU (Arithmetic and Logical
Unit) 81), and an operation corresponding to the ALU control signal (SALU-CONT) supplied from the program control unit 27A is performed on the data supplied from the data memory unit 23.

The output SAM unit 25 is connected to the element processor 31
Each memory has a storage unit for holding predetermined output data, and upon receiving an output SAM write signal (SOW) supplied from the program control unit 27A, stores the output data from the ALU array unit 24 in the storage unit. It has been made like that. The output SAM unit 25 outputs the held data in accordance with the output pointer signal (SOP) supplied from the output pointer 26.

The output pointer 26 corresponds to the element processor 31
Each time, an SOP signal indicating whether to output output data is output to the output SAM unit 25. The output pointer 26 is described in, for example, Japanese Patent Application Laid-Open No. 8-123.
Data can be selectively output from the element processor 31 in the same manner as described in Japanese Patent No. 683.

The program control section 27A controls each section in accordance with a predetermined program to perform various operations described later.

FIG. 2 shows a configuration example of the element processor 31. The element processor 31 in FIG. 2 is configured as a general-purpose processor that can be used for various purposes. The input buffer memory (IQ) 41 stores the input S of FIG.
Input data is stored corresponding to one element processor of the AM unit 22. The data memory (RF) 42 corresponds to one element processor of the data memory unit 23 in FIG. Output buffer memory (O
Q) 44 corresponds to one element processor of the output SAM unit 25 in FIG. 1 and stores output data.

The operation unit (ALU) 43 corresponds to one element processor of the ALU array unit 24 in FIG. 1 and performs various operations on data supplied from the data memory 42.
The calculation result is output to the data memory 42 or the output buffer memory 44.

In the element processor 31 shown in FIG. 2, input data is once input to the input buffer memory 41,
Thereafter, the data is transferred to the data memory 42. Arithmetic unit 43
Performs various operations on newly stored data, data stored in the past, data in the middle of operation, and the like, which are supplied as necessary from the data memory 42, and writes the data back into the data memory 42. Repeat for the program. The calculation result is output buffer memory 4
4 and output at a predetermined speed and format.

In the element processor 31, the input SAM unit 22, the data memory unit 23, and the output S
The AM unit 25 forms a “column” of the memory. The ALU array unit 24 is a 1-bit ALU and has a circuit configuration mainly using a full adder (full adder). Therefore, unlike a processor that performs processing in word units used in a general so-called personal computer or the like, the element processor 31 is a bit processing processor and performs processing in units of bits.

Since the bit processing processor has a small hardware scale per processor, the number of parallel processing can be increased. Therefore, the parallel processor for image processing is designed such that the number of parallel elements in the linear array of the element processors 31 is equal to or greater than the number H of pixels for one horizontal scanning period of the image signal.

FIG. 3 shows an example of a detailed circuit configuration of the element processor 31 described above. Note that the structure of each cell in FIG. 3 is described as a very general structure for easy understanding. A portion where a plurality of the same circuits are arranged is described as a single circuit (a circuit for one bit).

The part of the input SAM unit 22 corresponding to one element processor 31 is controlled by the input pointer 21.
According to the number of bits ISB of the input data,
Input SAM cells 22-1 to 22- storing one bit
It is composed of ISB. Note that, in FIG.
Instead of the B input SAM cells 22-1 to 22-ISB, one cell 22-i is described.

In the input SAM cell 22-i, the gate terminal of the transistor Tr1 is connected to the input pointer 21, and the other two terminals of the transistor Tr1 are connected to the input data bus 65 or the capacitor C1 for storing 1-bit data. Is connected to one end.

The gate terminal of the transistor Tr2 is connected to the program control unit 27A,
The signal is supplied, and the other two terminals of the transistor Tr2 are connected to the write bit line 63 and one end of the capacitor C1, respectively.

One end of the capacitor C1 is connected to the transistor T
r1 and Tr2, and the other end is grounded.

A portion corresponding to one element processor 31 of the data memory section 23 is composed of MB data memory cells 23-1 corresponding to the number of bits MB required as a working memory.
To 23-MB (storage unit). In FIG. 3, one cell 23-i is described instead of the MB data memory cells 23-1 to 23-MB.

Data memory cell 2 of data memory unit 23
3-i (i = 1,..., MB) is a three-port memory having two read bit lines 61 and 62 and one write bit line 63.

In the data memory cell 23-i, the gate terminal of the transistor Tr11 is connected to the program control unit 27A, supplied with the SWA signal, and the other two terminals of the transistor Tr11 are connected to the write bit line 63 and Capacitor C for storing 1-bit data
11 are respectively connected to one end.

One end of the capacitor C11 is connected to the gate terminal of the transistor Tr12 and the transistor Tr11, and the other end is grounded.

The other two terminals of the transistor Tr12 are connected to a ground point and a power supply (not shown) via a resistor R.
Connected to each other. Note that the resistor R is omitted,
The terminal of the transistor Tr12 may be directly connected to a power supply.

The gate terminal of the transistor Tr13 is connected to the program control unit 27A and supplied with the SRAA signal. The remaining two terminals of the transistor Tr13 are connected to the transistor Tr12, the resistor R, and the read bit line 61, respectively. It is connected.

The gate terminal of the transistor Tr14 is connected to the program control unit 27A and supplied with the SRBA signal. The remaining two terminals of the transistor Tr14 are connected to the transistor Tr12, the resistor R, and the read bit line 62, respectively. It is connected.

The part corresponding to one element processor 31 of the ALU array unit 24 is the ALU cell 24 shown in FIG.
A (ALU unit). ALU81 of ALU cell 24A
Is a 1-bit ALU, has a circuit configuration such as a full adder (full adder), and includes flip-flops 82-1 to 82-1.
An operation is performed on the 1-bit value supplied from 2-3, and the operation result is output to the selector 83.

The ALU cell 24A has a flip-flop 8 holding a 1-bit value input to the ALU 81.
2-1 to 82-3, flip-flops 82-1 to 8-8
Selector (SEL) 8 for selecting a value supplied to 2-3
4-1 to 84-3.

The part of the output SAM unit 25 corresponding to one element processor 31 is controlled by the output pointer 26,
It is composed of OSB output SAM cells 25-1 to 25-OSB corresponding to the number of output signal bits (OSB). In FIG. 3, one cell 25-i is described instead of the output SAM cells 25-1 to 25-OSB.

In the output SAM cell 25-i, the gate terminal of the transistor Tr7 is connected to the program control unit 27.
A, is supplied with the SOW signal, and the other two terminals of the transistor Tr7 are connected to the write bit line 63.
A and a capacitor C for storing 1-bit data
4 is connected to one end.

One end of the capacitor C4 is connected to the transistor T
r7 and Tr8, and the other end is grounded.

The gate terminal of the transistor Tr8 is connected to the output pointer 26, and the other two terminals of the transistor Tr8 are connected.
One terminal of the two terminals is connected to the capacitor C4 and the transistor Tr7, and the other terminal is connected to the output data bus 6
6 is connected.

All the word lines connected to the element processor 31 are connected to the other element processors 3 arranged.
1, the SIR signal, SWA signal, memory read access signal (SRAA, SRBA), SO
The W signal and the like are transmitted to all the element processors 31.
These word lines are connected to the program control unit 2 in FIG.
The address is decoded in 7A.

The input data bus 65 is connected to the input SAM cells 22-i of all the element processors 31, and the output data bus 66 is connected to all the element processors 3-3.
1 SAM cell 25-i.

Further, the memory 28 (storage means) in FIG.
At the time of startup, during a horizontal retrace period, a vertical retrace period, and the like, data of all interpolation filter coefficients required for a filter operation in all the element processors 31 and supplied from an external control CPU (not shown), The numbers are stored in the order of the element processors 31.

Next, data transfer and operation in element processor 31 will be described.

In the input SAM cell 22-i of the element processor 31 designated by the input pointer 21, the transistor Tr1 is turned on, and the terminal voltage of the capacitor C1 changes to the input data bus 65 (and the buffer 7).
The voltage becomes a voltage corresponding to the input data supplied via 1).

Thus, the input data is stored in the input SAM unit 22 of the specified element processor 31.

Next, the input SAM cell 22- selected by the SIR signal supplied from the program control unit 27A.
In i, the transistor Tr2 is turned on,
A transfer data signal corresponding to the voltage of the capacitor C1 is generated on the write bit line 63.

At this time, while the SBC signal is supplied to the buffer 72, the SWA signal is supplied to the transistor Tr11 of the predetermined data memory cell 23-i, and the transistor Tr11 is turned on. The voltage becomes a voltage corresponding to the data stored in the capacitor C1 of the input SAM cell 22-i.

When data is supplied from the ALU cell 24A, the SBCA signal is supplied to the buffer 73.

In this data transfer, the write bit line 63
Through one bit per cycle. Input S
The SIR signal used to read data from each input SAM cell 22-i of the AM unit 22 and the SWA signal used to write data to each data memory cell 23-i of the data memory unit 23 are the same. Addresses in the address space are shown, each being decoded by a row decoder and given as a word line.

The ALU cell 24A stores the input data written in the data memory section 23 as described above, the data being calculated, or the flip-flop 82.
Using the data stored in -1 to 82-3, the arithmetic processing in bit units is sequentially advanced.

For example, the data of the data memory cell 23-i corresponding to a predetermined bit of the data memory unit 23 and the data of the data memory cell 23-i corresponding to another bit are added, and further added to another bit. When writing the addition result to the corresponding data memory cell 23-i, the following operation is performed.

The program control unit 27A operates the data memory cell 23 corresponding to a predetermined bit of the data memory unit 23.
-I, the transistor Tr13 of the cell is turned on, and the data stored in the capacitor C11 is transferred to one of the read bit lines 61 or 6
2 is output.

At the same time, program control unit 27A stores SRBA in data memory cell 23-i corresponding to another bit.
A signal is supplied, the transistor Tr14 of the cell is turned on, and the data stored in the capacitor C11 is output to the other read bit line 62 or 61.

These two read data are AL
The data is supplied to the ALU 81 via the selectors 84-1 to 84-3 of the U cell 24A. Then, the ALU 81 performs a predetermined operation on the data, and supplies the operation result to the flip-flop 85 via the selector 83.

Then, the program control unit 27A
The CA signal is supplied, the operation result is output from the flip-flop 85 to the write bit line 63, and the SWA signal is
The data is supplied to the data memory cell 23-i corresponding to the predetermined bit, the transistor Tr11 of the cell 23-i is turned on, and the terminal voltage of the capacitor C11 is set to a voltage corresponding to the operation result.

The arithmetic operation in ALU cell 24A is performed according to an ALU control signal (SALU-CONT) supplied from program control unit 27A. ALU
The operation result in the cell 24A is written into the data memory unit 23 as described above, or is stored in the flip-flop 82-3 of the ALU cell 24A as necessary. When the operation in the ALU 81 is addition,
The ALU cell 24A outputs the carry in the operation result to the flip-flop 82-3 and outputs the sum to the data memory unit 23.

Next, when outputting data from the data memory cell 23-i, the program control unit 27A sets the data memory cell 23-i storing the data to be output.
And a memory access signal (SRAA or SRBA)
And the transistor Tr13 of the cell 23-i is supplied.
Alternatively, Tr14 is turned on to read the data stored in the capacitor C11 and read the bit line 61 or 6
Output to 2.

Then, the program control unit 27A
A predetermined control signal is supplied to the U cell 24A, and the data from the data memory cell 23-i is output to the output SAM cell 25-A.
i. At this time, the program control unit 27A
Outputs an SOW signal so that data is supplied to the capacitor C4 of the output SAM cell 25-i, turns on the transistor Tr17 of the cell, and changes the terminal voltage of the capacitor C4 according to the data. To voltage.

The data is transferred bit by bit via the write bit line 63. At this time, the ALU 81 may perform some processing on the data.

The SOW used when data is stored in each output SAM cell 25-i of the output SAM unit 25.
Signal and each data memory cell 23 of the data memory unit 23
Memory access signals (SRAA, SRBA) used when reading data from -i are addresses in the same address space, and are decoded by a row decoder and supplied via word lines.

In output SAM cell 25-i of element processor 31 designated by output pointer 26, transistor Tr8 is turned on in response to the output pointer signal, and the output signal corresponding to the potential of capacitor C4 is output to the output data bus. It is output to 66.

The value of the output pointer 26 is "H".
Is output to the leftmost element processor 31.
To the rightmost element processor 31 in accordance with the clock signal.
From the output SAM cell 25-i.

Thus, the output SAM cell 25-i
Is output to the output terminal DOUT via the output data bus 66.

Since the element processor 31 is provided with the number of pixels H or more in one horizontal scanning period of the image signal, by performing this operation, data of one horizontal scanning period of the output image signal is output to the output SAM. Output from the unit 25. This output operation is repeated every horizontal scanning period.

As described above, each element processor 31
Performs processes such as data input, data transfer, calculation, and data output in accordance with various control signals supplied from the program control unit 27A.

In the first embodiment, all the filter coefficient sets are supplied to the data memory units 23 of all the element processors 31 at the time of activation, during the horizontal retrace period or the vertical retrace period. . At this time, the filter coefficient set is supplied from the memory 28 to the input SAM unit 22 via a part (predetermined bit width) of the input data bus 65, and is transferred to the data memory unit 23. The operation at this time is the same as the operation of supplying the input data Ri to the data memory unit 23, which will be described next, and thus the description thereof is omitted.

Next, referring to the flowchart of FIG.
The operation of the first embodiment will be described.

First, in step S1, predetermined L-bit input data Ri (= 1) for one horizontal scanning period
{ _Ri0 , ..., _{ri (L-1)} }) are input to the input SAM unit 22.

When the image is enlarged by (10/7) times,
As described above, the positional relationship between the element processor 31 that holds input data necessary for calculating each output data and the element processor 31 that calculates the output data changes for each output data. For example, when calculating the output data of 10 pixels corresponding to the input data of 7 pixels, the pattern of the element processor 31 holding the input data necessary for the calculation of each output data is 5 as shown in FIG. Are classified into three patterns.

In this case, as shown in FIG.
Any of the input data is overlapped, and the seven input data are densely supplied to the ten element processors 31. That is, of the element processors 31 shown in FIG. 31 to which input data is not supplied, the same input data as the element processor 31 on the left side is supplied.

This input data supply procedure may be realized in the same manner as the data input in the apparatus shown in FIG. 27, or may be performed by using the method described in Japanese Patent Application Laid-Open No. 8-123683. Alternatively, data may be supplied once so as to be in a sparse state, and then predetermined data may be copied according to a program.

In FIG. 5, the input data Ri and the output data Qi are actually about 8 bits, but are each represented by 4 bits for convenience. Also,
In the input SAM unit 22, the data memory unit 23, and the output SAM unit 25, only the memory capacities necessary for explanation are shown.

By supplying the input data in this manner, as shown in FIG. 6, for example, in the case of the type 1 pattern in FIG. 6, the element processor 31 on the left and the element processor 31 on the left are adjacent to each other. 6, the same input data is supplied, and the same input data is supplied to the element processor 31 on the right side and the element processor 31 on the right side, so that the pattern of type 1 in FIG. Can be handled in the same way as the pattern of

In the case of the type 3 pattern of FIG. 6, the same input data is supplied to the predetermined element processor 31 and the element processor 31 on the left side thereof, so that the type 3 pattern of FIG. It can be handled in the same way as the type 4 pattern.

Further, in the case of the pattern of type 5 in FIG. 6, the same input data is supplied to the element processor 31 on the right side and the element processor 31 on the two right side. Can be handled in the same manner as the type 2 pattern.

Therefore, by supplying input data as shown in FIG. 5, the above five patterns are reduced to two patterns (type 2 and type 4) shown in FIG.

In the case of a conversion ratio other than (10/7), the positional relationship as described above is calculated in advance by calculating the input data supply method that minimizes the number of patterns described above. Can be degenerated.

Then, the program control section 27A supplies a one-bit value (0 or 1) indicating a pattern corresponding to the element processor 31 with respect to the two patterns to each element processor 31 together with the input data.

Next, in steps S2 to S5, the program control unit 27A
1 is supplied from the input SAM unit 22 to the data memory unit 2 via the write bit line 63.
3 is transferred one bit at a time.

In this case, for the sake of convenience, the input data Ri is 4
The bits are set in bits and are stored at addresses 0 to 4 of the input SAM unit 22. Therefore, as shown in FIG. 5, the content of the address 0 of the input SAM unit 22 is transferred to the address 8 of the data memory unit 23, and similarly, the input SA
The contents of addresses 1 to 3 of the M section 22 are transferred to addresses 9 to 11 of the data memory section 23, respectively.

Then, in step S6, each element processor 31 performs signal processing described later.

At steps S7 to S10, the program control unit 27A
The calculation result (output data Qi) calculated in is read out from the data memory unit 23 by the read bit lines 61, 62,
Then, the output SAM unit 25 is transferred one bit at a time via the ALU cell 24A.

In this case, the output data Qi (= q _i0 ,...)
., Q _i3 ) is set to 4 bits for convenience, and stored in addresses 16 to 19 of the data memory unit 23. Therefore, as shown in FIG.
Are transferred to the address 20 of the output SAM unit 25, and similarly, the contents of the addresses 17 to 19 of the data memory unit 23 are transferred to the addresses 21 to 23 of the output SAM unit 25, respectively.

Next, in step S11, the calculated output data Qi for one horizontal scanning period is output to the output SAM unit 2.
5 is output.

As described above, the filter operation is performed for each image data for one horizontal scanning period. The operation of step S1, the operations of steps S2 to S10, and the operation of step S11 are performed in parallel, and the operations of steps S2 to S10 are performed on image data for one predetermined horizontal scanning period. When the operation is performed, the operation of step S11 is performed on the image data of one horizontal scanning period one line before, and the operation of step S1 is performed on the image data of one horizontal scanning period after one line. .

Next, the details of the signal processing in step S6 in FIG. 4 will be described with reference to the flowcharts in FIGS.

First, in step S21, each element processor 31 holds the supplied data and copies it to the element processor 31 on the left.

Hereinafter, the data supplied to the predetermined element processor 31 is R ₀ , the data supplied to the left adjacent element processor 31 is R _−1, and the data supplied to the left two adjacent element processors 31 is R _−1. The obtained data is _defined as R- ₂ . Further, the data supplied to the right adjacent element processor 31 is R _{+ 1} , the data supplied to the right two adjacent element processors 31 is R _{+ 2} , and the three right adjacent element processors 31 are R _{+ 2.
Is} R _{+ 3} .

Next, in step S22, the element processor 31 outputs the data R _-1 of the element processor 31 on the left side.
And the product of the filter coefficient FC1 supplied in advance and substituting the calculation result into Y _1A (Y _1A ← R ₋₁ × FC
1). The calculation of the product is performed by performing a predetermined number of bit calculations.

In step S23, the element processor 31 calculates the product of the data R ₀ supplied thereto and the filter coefficient FC2, and substitutes the calculation result in Y _2A (Y _2A ← R ₀ × FC2).

Then, in step S24, the element processor 31 calculates the sum of Y _1A and Y _2A and substitutes the calculation result for Y _1A (Y _1A ← Y _1A + Y _2A ). The calculation of the sum is performed by performing a predetermined number of bit calculations.

Next, in step S25, the element processor 31 calculates the product of the data R ₊ 2 of the element processor 31 on the right two adjacent sides and the filter coefficient FC3, and substitutes the calculation result for Y _2A (Y _2A ← R ₊₂ × FC3).

Then, in step S26, the element processor 31 calculates the sum of Y _1A and Y _2A and substitutes the calculation result for Y _1A (Y _1A ← Y _1A + Y _2A ).

[0217] Next, in step S27, the element processor 31 determines the data R of the three right next element processors 31 that the two right adjacent element processors 31 have.
_+3, calculates the product of the filter coefficients FC4, and substitutes the calculation results to the _{Y 2A (Y 2A ← R +3} × FC4).

Then, in step S28, the element processor 31 calculates the sum of Y _1A and Y _2A and substitutes the calculation result for Y _1A (Y _1A ← Y _1A + Y _2A ). At this time,
The value of Y _1A is R _-1 × FC1 + R ₀ × FC2 + R ₊₂ × FC
3 + R ₊₃ × FC4, which corresponds to the type 2 pattern in FIG.

Next, in step S29, the element processor 31 calculates the product of the data R _{-2 of the} two adjacent left element processors 31 and the filter coefficient FC1, and substitutes the result of the calculation into Y _1B (Y _1B ← R _-2 × FC1).

In step S30, the element processor 31 calculates the product of the data R ₀ supplied thereto and the filter coefficient FC2, and substitutes the calculation result in Y _2B (Y _2B ← R ₀ × FC2).

Then, in step S31, the element processor 31 calculates the sum of Y _1B and Y _2B and substitutes the calculation result for Y _1B (Y _1B ← Y _1B + Y _2B ).

Next, in step S32, the element processor 31 outputs the data R _{+ 1} of the element processor 31 on the right.
If, calculates the product of the filter coefficient FC3, the calculation result is substituted into _{Y 2B (Y 2B ← R +1} × FC3).

Then, in step S33, the element processor 31 calculates the sum of Y _1B and Y _2B and substitutes the calculation result in Y _1B (Y _1B ← Y _1B + Y _2B ).

Next, in step S34, the element processor 31 calculates a product of the data R ₊ 2 of the two adjacent right element processors 31 and the filter coefficient FC4, and substitutes the calculation result into Y _2B (Y _2B ← R ₊₂ × FC4).

In step S35, the element processor 31 calculates the sum of Y _1B and Y _2B , and outputs the calculation result as Y _1B
(Y _1B ← Y _1B + Y _2B ). At this time, the value of Y _1B is R ₋₂ × FC1 + R ₀ × FC2 + R ₊₁ × FC3 + R ₊₂
× FC4, which corresponds to the pattern of type 4 in FIG.

Then, in step S36, the element processor 31 supplies the input data Ri with the input data Ri.
Referring to the value (0 or 1) indicating the above-mentioned positional relationship, it is determined whether or not the value is a first value (a value corresponding to type 2 in FIG. 7), and the value is determined to be the first value. If it is determined that the value is not the first value, the process proceeds to step S37, and the value indicating the above-described positional relationship is determined not to be the first value using Y _1A of step S28 as the calculation result (that is, the type shown in FIG. 7). If the value is a value corresponding to 4), Y _1B in step S35 is set as the calculation result.

As described above, the filter operation is performed using the data of the neighboring element processors 31 corresponding to the two types of positional relationships.

Although the memory 28 may store the filter coefficient sets corresponding to all the element processors 31 as described above, the element processors 31 for calculating the pixel values of the same phase may be stored. Uses the same filter coefficient set, so that only the filter coefficient sets of the number of phases to be used may be stored.
By doing so, the storage area of the memory 28 can be saved.

For example, when the image is enlarged by (10/7) times, since there are only 10 types of phases, the memory 28 stores 10 types of filter coefficient sets corresponding to the phases, Sets of filter coefficients
What is necessary is just to output repeatedly according to the order of the element processors 31. The order in that case is the filter selection number P in FIG.
This is the order of i.

Further, by providing a selector to supply either one of the filter coefficient set and the input data from the memory 28 to the input SAM unit 22, for example, an input SAM unit such as a vertical blanking period is provided. The filter coefficient set may be supplied in the same manner as the input data during a period when the input data 22 is not used for supplying the input data Ri.

By doing so, the filter coefficient can be supplied using the bus 65 having the same number of bits as the input data, so that the filter coefficient having a large number of bits (having a long word length) can be shortened. Can be supplied in time.

For example, when the number of bits of the filter coefficient is 10, the set of four filter coefficients is data of a total of 40 bits. It is entirely possible to supply the filter coefficients to H.23 within the vertical retrace interval.

Further, once all the filter coefficient sets have been supplied, the filter coefficients may be gradually changed using, for example, a bit width of about 4 bits of the input data bus 65. Good. In this case, in order to ensure the continuity of the filter operation, the filter coefficients used so far are used as they are in several horizontal scanning periods until the transfer is completed.

In the first embodiment, the filter coefficient set is supplied to the input SAM unit 22 in a pattern different from the input data Ri. In the case where the filter coefficient is supplied in parallel with the input data, two circuits for pointer control of the input SAM unit 22 are provided, and pointer control for the input data Ri is performed.
Pointer control for filter coefficients is performed independently.

FIG. 10 shows the configuration of the second embodiment of the present invention. In the second embodiment, the memory 29 (storage means) holds the data of the filter coefficient set corresponding to each phase of the calculated pixel. Further, the memory 29 includes a program control unit 27B.
During startup, a horizontal retrace period, a vertical retrace period, and the like, the filter coefficient set is converted via the ALU array unit 24 of the element processor 31 which calculates the value of a pixel having a phase corresponding to the filter coefficient set. The data is supplied to the data memory unit 23.

The memory 28A (second storage means) corresponds to each of the element processors 31.
Holds the filter selection number i corresponding to the pixel phase (filter selection signal Pi in FIG. 29) calculated by The filter selection number i is supplied to the data memory unit 23 via the input data bus 65 together with the input data Ri, similarly to the filter coefficient set of the first embodiment.

It is assumed that the data stored in the memories 28A and 29 is supplied in advance by the external control CPU at the time of startup or the like.

The program control section 27B controls each section to perform the operation described later.

The other components are the same as those of the first embodiment, and the description will not be repeated.

Note that the filter selection number i held in the memory 28A is, for example, the value of the input data bus 6 at the time of startup.
5 and the data memory unit 23 via the input SAM unit 22
Is supplied in advance.

For example, when the phases of the pixels are 10 types, the memory 28A stores
10 filter selection numbers i corresponding to 10 types of phases
What is necessary is just to memorize. That is, the filter selection number i is 1
If there are 0 filters, the filter selection number can be represented by a 4-bit binary number.
Stores 4-bit data as the filter selection number i.

Further, even if there are 1,000 filter selection numbers i, they can be represented by a 10-bit binary number, so that the filter coefficients are input to the input SAM unit 22 as in the first embodiment. Input S
The load on the AM unit 22 can be reduced.

FIG. 11 shows a filter selection number i (=) stored in the data memory unit 23 of each element processor 31.
{Φ _i0 ,..., Φ _i3 }). FIG.
, Ten types of filter selection numbers i (i = 0,..., 9) are stored as 4-bit data. For example, in the data memory unit 23 of the element processor 31 having the number 6, 4-bit data {φ ₂₀ ,.
φ ₂₃記憶 is stored.

Next, the operation of each unit when the filter coefficient set is supplied to the data memory unit 23 of each element processor 31 in the second embodiment will be described with reference to the flowchart of FIG.

First, in step S41, the program control section 27B sets a value of a counter j for counting a filter selection number i corresponding to a filter coefficient set to be supplied to 0.

Next, in step S42, the program control unit 27B sets the value of the counter m used when supplying the value of the counter j in bit units to 1.

Then, the program control unit 27B outputs the value of the m-th bit of the value of the counter j to the ALU cells 24A of all the element processors 31, and the ALU cell 24A of each element processor 31 Receives the value of

In step S44, the program control unit 27B determines whether or not the value of the counter m is equal to or greater than the bit length of the counter j.
Is determined to be smaller than the bit length of
After the value of the counter m is increased by 1, the flow returns to step S43 to supply the next bit.

As described above, the value of the counter j is supplied to each element processor 31 bit by bit.

On the other hand, in step S44, the counter m
Is determined to be greater than or equal to the bit length of the counter j, it means that the value of the counter j has been supplied. In step S46, each element processor 31 stores the value of the received counter j in the memory It is determined whether or not the value of the filter selection number i supplied from 28A is the same,
If they are the same, for example, a flag is set according to the determination, and the process proceeds to step S47.

At step S47, each element processor 31 sets the value of the counter k for counting the number of bits of the supplied filter coefficient set to 1 in accordance with the flag.

At step S48, each element processor 31 stores the value of the k-th bit of the filter coefficient set output from the memory 29 into the ALU cell 24.
A, and the data is stored in the data memory unit 23.

In the memory 29, a filter coefficient set corresponding to each phase (ie, the filter selection number i) is stored for each coefficient in order from the most significant bit (MSB) or the least significant bit (LSB). And the filter coefficient set is transmitted via the 1-bit line as described above.
The bits are sequentially output to the ALU cell 24A of the element processor 31 bit by bit.

In step S49, each element processor 31 determines whether or not the value of the counter k is equal to or greater than the bit length of the filter coefficient set, and determines that the value of the counter k is smaller than the bit length of the filter coefficient set. If it is determined that the value of the counter k is 1 in step S50.
Then, the process returns to step S48 to receive the next bit of the filter coefficient set.

On the other hand, in step S49, the counter k
Is determined to be greater than or equal to the bit length of the filter coefficient set, it means that the supply of the filter coefficient set corresponding to the value of the counter j has been completed.
Proceed to.

On the other hand, in step S46, when the element processor 31 determines that the value of the counter j is not the same as the value of the filter selection number i previously supplied from the memory 28A, the element processor 31
Steps S47 to S50 are skipped without receiving the output filter coefficient set.

Next, in step S51, the program control section 27B determines whether or not the value of the counter j is equal to or greater than a value obtained by subtracting 1 from the number N of the pixel phases. When it is determined that the value is equal to or more than the value obtained by subtracting 1 from the number N of pixels (j ≧ N−1), one of the N filter coefficient sets has been supplied to each element processor 31. Therefore, the process of supplying the filter coefficient set ends.

On the other hand, when the program control unit 27B determines that the value of the counter j is smaller than the value obtained by subtracting 1 from the number N of pixel phases (j <N−1), the program control unit 27B proceeds to step S5.
In step 2, the value of the counter j is increased by 1, and the process returns to step S42 to supply a filter coefficient set corresponding to the next filter selection number i.

Thus, each element processor 31
Receives the filter coefficient corresponding to the filter selection number i supplied in advance from the memory 29 and stores it in the data memory unit 23.

As described above, by supplying the filter coefficient set through a path different from the input data Ri, it is necessary to use a number of program steps to selectively supply the filter coefficient set to the element processor 31. And can be easily realized.

When any one of, for example, ten types of filter coefficient sets stored in the memory 29 is supplied to each element processor 31, one filter coefficient set is about one tenth of all the element processors 31. Are simultaneously supplied to the element processors 31. Therefore, when the filter coefficient set is, for example, 40 bits, regardless of the number of element processors 31, the operation of 400 (= 40 bits × 10) steps is performed to all the element processors 31. A set of filter coefficients can be provided.

The operation when processing image data is the same as that in the first embodiment, and a description thereof will be omitted.

As described above, in the second embodiment, the filter coefficient set is supplied through a different path from the input data, so that the filter coefficient set is supplied regardless of the operation status of the input SAM unit 22. be able to.

Next, a third embodiment of the present invention will be described. In the third embodiment, each element processor 31 calculates a filter coefficient set in each element processor 31 corresponding to the filter selection number i.

Note that the configuration of the third embodiment and the operation at the time of filter operation are the same as those of the first embodiment, and a description thereof will be omitted. However, the memory 28
It is assumed that the filter selection number i is stored in the same manner as in the memory 28A of the embodiment.

Next, the operation of each unit when calculating a filter coefficient set in the third embodiment will be described with reference to the flowcharts of FIGS. Here, a filter coefficient set in the Cubic approximation method of Expression (4) is calculated. Of course, a filter coefficient set in another approximation method may be calculated.

First, in step S61, the element processor 31 sets the image conversion ratio to K / L times.
Than previously supplied by that filter selection number i and K, and calculates the phase i / K pixel for calculating the value, stored as X _0. Note that K and L are supplied from the program control unit 27A.

Next, the element processor 31 determines in step S
In step 62, X ₀ is substituted for X. In step S63, the square of X (X × X) is calculated, and the calculation result is expressed as X
Remember as ₂ .

Further, in step S64, the element processor 31 calculates the product of X ₂ and X (ie, the cube of X), and stores the calculation result as X ₃ .

Then, in step S65, the element processor 31 calculates the filter coefficient FC3 from X, X ₂ and X ₃ according to the following equation using equation (4). _{FC3 = -X 3 + 5X 2 -8X} + 4 (5)

Next, in step S66, the element processor 31 substitutes X with a value obtained by adding 1 to X ₀ (= i / K).

In step S67, the element processor 31 calculates the square of X (X × X), substitutes the calculation result for X ₂ , and in step S68, calculates the product of X ₂ and X (ie, X raised to the third power), and the result of the calculation is X
Substitute for ₃ .

In step S69, the element processor 31 obtains X, X ₂ and X ₃ using the equation (4).
The filter coefficient FC4 is calculated according to the following equation. FC4 = X ₃ -2X ₂ +1 (6)

Next, in step S70, the element processor 31 substitutes a value obtained by subtracting X ₀ from 1 into X.

Then, in step S71, the element processor 31 calculates the square of X (X × X), substitutes the calculation result for X ₂ , and in step S72, calculates the product of X ₂ and X (ie, X raised to the third power), and the result of the calculation is X
Substitute for ₃ .

In step S73, the element processor 31 obtains X, X ₂ and X ₃ from equation (4) using
The filter coefficient FC2 is calculated according to the following equation. _{FC2 = -X 3 + 5X 2 -8X} + 4 (7)

Next, in step S74, the element processor 31 calculates a value (2-i / K) obtained by adding 1 to X, and substitutes the calculation result for X.

Then, in step S75, the element processor 31 calculates the square of X (X × X) and substitutes the calculation result in X _{2. In} step S76, the product of X ₂ and X (ie, X raised to the third power), and the result of the calculation is X
Substitute for ₃ .

In step S77, the element processor 31 obtains X, X _2, and X ₃ by using the equation (4).
The filter coefficient FC1 is calculated according to the following equation. _{FC1 = X 3 -2X 2 +1 (} 8)

As described above, in the third embodiment, the filter coefficient set (FC1, FC2, F2
C3, FC4) are calculated.

As described above, by calculating the filter coefficient set by each element processor 31, there is no need to supply the filter coefficient set from a memory (memory 28, 29, etc.) external to the element processor 31. There is no need to consider supply timing and the like.

FIG. 15 shows the configuration of the fourth embodiment of the present invention.

In the fourth embodiment, the memory 28A of the second embodiment is removed, and the filter selection number i
Is calculated by each element processor 31.

The program of the program control unit 27C has been modified so as to perform the operation described later.
The other components, the operation at the time of supplying the filter coefficient, and the operation at the time of the filter operation are the same as those of the second embodiment, and thus the description thereof is omitted.

Next, the operation when calculating the filter selection number i will be described with reference to the flowchart in FIG.

First, in step S81, the element processor 31 sets the registers ZA ₀ , ZB ₀ ,
ZC ₀ is secured respectively.

Next, in step S82, each element processor 31 substitutes zero for ZA ₀ , ZB ₀ , and ZC ₀ respectively.

In step S83, each element processor 31 determines the value ZA ₀ of the element processor 31 on the left side.
The sum of A _-1 and L when the conversion ratio is K / L times (that is, K: L) is calculated, and the calculation result is stored in ZA ₀ . Since the leftmost element processor 31 has no element processor 31 on the left side, the calculation is performed with ZA- _{1 set} to 0.

In step S84, each element processor 31 determines whether or not the value of ZA ₀ is greater than K.
If it is determined that the value of ZA ₀ is larger than K,
At 85, the remainder when the value of ZA ₀ is divided by K is calculated, and the calculation result is substituted into ZA ₀ .

On the other hand, when each element processor 31 determines that the value of ZA ₀ is equal to or smaller than K, it skips step S85.

Then, in step S86, each element processor 31 executes steps S83 to S85.
Is determined to have been repeated more times than the number of pixels in the horizontal direction of the image format currently being handled, and the operations of steps S83 to S85 are repeated only for the number of pixels in the horizontal direction of the currently handled image format. If it is determined that there is not, the process returns to step S83, and the operations of steps S83 to S85 are performed again.

On the other hand, when each element processor 31 determines that the operations of steps S83 to S85 have been repeated more times than the number of pixels in the horizontal direction of the image format currently being handled, the process proceeds to step S87.

In step S87, each element processor 31 determines the value ZB ₀ of the element processor 31 on the left side.
The sum of B _-1 and L is calculated, and the calculation result is stored in ZC ₀ . Note that the leftmost element processor 31 does not have the element processor 31 on the left side, and therefore performs the operation with ZB ₋₁ as 0.

[0294] Next, in step S88, the element processor 31 determines whether the value of the ZC ₀ is greater than 2 times the value of K, determines the value of the ZC ₀ is greater than 2 times the value of K If you, at step S90, and substitutes a value obtained by subtracting K from the value of ZB ₀ to ZB _0.

On the other hand, if the element processor 31 determines that the value of ZC ₀ is equal to or less than twice the value of K, the process proceeds to step S.
In 89 substitutes the value obtained by subtracting K from the values of ZC ₀ to ZB _0.

Then, in step S91, each element processor 31 executes steps S87 to S90.
Is determined to have been repeated more times than the number of pixels in the horizontal direction of the currently handled image format, and the operations of steps S87 to S90 are repeated only for the number of pixels in the horizontal direction of the currently handled image format. If it is determined that there is not, the process returns to step S87, and the operations of steps S87 to S90 are performed again.

On the other hand, when each element processor 31 determines that the operations of steps S87 to S90 have been repeated more times than the number of pixels in the horizontal direction of the image format currently being handled, the process proceeds to step S92.

Then, in step S92, each element processor 31 determines whether or not K is larger than L, that is, whether or not the process is an image enlargement process. If the value of ZA ₀ is used as the filter selection number i and it is determined that K is equal to or less than L, the value of ZB ₀ is used as the filter selection number i in step S93.

The filter selection number i is calculated as described above. Although division (calculation of remainder) is performed in step S85, subtraction is repeatedly performed in practice. Although the above-described processing has many processing steps, there is no particular problem if the processing is performed before performing the real-time processing or during the vertical blanking period.

Steps S84 and S8
8, corresponding to the input data or output data and the element processor 31 (Ri in FIG. 31).
May be set. That is, in step S85, the same processing as the above-described modulo operation of the phase is performed, and accordingly, in response to the determination in step S84, the number at which the modulo operation is performed is compared with the pixel number calculated by the element processor. By doing so, input data assigned to the element processor 31 can be determined.

FIG. 17 shows the configuration of the fifth embodiment of the present invention.

In the fifth embodiment, the filter selection number i
And the corresponding filter coefficient sets are calculated by the respective element processors 31 in the same manner as in the third embodiment or the fourth embodiment, so that the memories 28, 28
A and 29 are unnecessary.

The program control unit 27D controls each element processor 31 and, like the program control unit of the third or fourth embodiment, stores the filter selection number i and the corresponding filter coefficient set. It is made to calculate.

The other components are the same as in the fourth embodiment, and a description thereof will not be repeated. The operation when calculating the filter coefficient set is the same as that of the third embodiment, and the other operation is the same as that of the fourth embodiment.

As shown in FIG. 29, of the sum of the four filter coefficients (of 8-bit representation) corresponding to each phase, those that are not 128 (that is, 1.0 in real number representation) P1, P2, P3, and P7). This error is generated when the filter coefficient is quantized to 8 bits. If these coefficients are used as they are, for example, a pulsation occurs in output data corresponding to input data having a large DC component, and the It may deteriorate. Therefore, it is preferable to modify the filter coefficients FC1 to FC4 so that the above sum becomes 128.

In this case, FC1 or FC has less influence on the characteristics of the interpolation filter than FC2 and FC3.
It is more preferable to modify C4. For example, by changing the value of the filter coefficient FC1 corresponding to the phase P1 in FIG. 29 from −1 to −2, the sum of the filter coefficients becomes 1
28.

[0307] The one having the largest error when the filter coefficient is quantized to 8 bits may be corrected. For example, the filter coefficient FC corresponding to the phase P3
3 is 0.363 in the real number representation and 46 in the 8-bit representation. The error is 0.464 (= 0.3
63 × 128-46)
, The sum of the filter coefficients becomes 128.

In the above embodiment, the enlargement of an image is mainly described, but it is of course possible to reduce the image. In the case of image reduction, the input S
The input data is supplied densely to the AM unit 22 in order, and the output data is sparsely output to the output SAM unit 25.

In the element processor 31 near the end (right end, left end) of the above embodiment, there is a case where there is no peripheral element processor 31 having input data used for the operation. , With the value of the input data set to 0.

In addition, there are various methods for processing at the edge of the image, for example, assuming that the data at the edge is continuous outside the edge or that the data is symmetric about the edge. Can be considered. Of these methods, the method can be realized by writing a program corresponding to a predetermined method.

In the above embodiment, each element processor 31 performs only a filter operation corresponding to pixel interpolation. However, for example, various filter processes, color operations, and data of a predetermined transmission system are performed. Conversion, noise reduction,
In response to various image processing and TV (television) signal processing that you want to execute simultaneously with the conversion of the number of pixels, such as contour enhancement,
By changing or adding the program of the program control unit, these processes can be performed without changing the hardware configuration.

The capacity of the memories 28, 28A, and 29 is proportional to the number of pixel phases and is not so large, so that the scale of the apparatus does not increase.

Further, the image conversion ratio can be changed by changing the program of the program control section.

[0314]

As described above, according to the image processing apparatus of the first aspect and the image processing method of the sixth aspect,
The image data is supplied to a plurality of element processors so that the type of the pattern of the positional relation between the peripheral element processors having the image data used by the predetermined element processor and the predetermined element processor is minimized. The image processing can be performed by a SIMD-type parallel processor corresponding to the positional relationship between the pixels.

According to the image processing apparatus and the image processing method of the present invention, a filter coefficient set used for interpolation is supplied to each of the element processors via the input bus. The image data is interpolated by using the filter coefficient set, so that the image can be processed by the SIMD parallel processor using the filter coefficient corresponding to the positional relationship of each pixel. it can.

According to the image processing apparatus of the present invention, a filter coefficient set used for interpolation is supplied to each of the element processors via a circuit different from the input bus. Then, the element processors use the filter coefficient set to perform the interpolation processing of the image data, respectively. Therefore, the SIMD parallel processor of the image uses the filter coefficients corresponding to the positional relationship of each pixel. Processing can be performed.

According to the image processing device of the twenty-fifth aspect and the image processing method of the thirty-first aspect, the element processor is used for interpolation in accordance with the phase information of the image data allocated to the element processor. The filter coefficient sets are calculated, and the interpolation process of the image data is performed using the filter coefficient sets. Therefore, the parallel processor of the SIMD format is used by using the filter coefficients corresponding to the positional relationship of each pixel. Can perform image processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an element processor.

FIG. 3 is a circuit diagram illustrating a detailed configuration example of an element processor.

FIG. 4 is a flowchart illustrating an operation of the image processing apparatus of FIG. 1;

FIG. 5 is a diagram illustrating an example of data stored in each unit of the image processing apparatus in FIG. 1;

FIG. 6 is a diagram illustrating an example of a positional relationship with an element processor having data necessary for processing.

FIG. 7 is a diagram illustrating an example of a positional relationship obtained by degenerating the positional relationship of FIG. 6;

FIG. 8 is a flowchart illustrating a filter calculation process in the image processing apparatus of FIG. 1;

FIG. 9 is a flowchart illustrating a filter calculation process in the image processing apparatus of FIG. 1;

FIG. 10 is a block diagram illustrating a configuration of an image processing apparatus according to a second embodiment of the present invention.

FIG. 11 is a diagram showing an example of a filter selection number stored in a data memory unit.

FIG. 12 when supplying a filter coefficient set;
5 is a flowchart for explaining the operation of the image processing apparatus of FIG.

FIG. 13 is a flowchart illustrating an operation when each element processor calculates a filter coefficient set in the third embodiment.

FIG. 14 is a flowchart illustrating an operation when each element processor calculates a filter coefficient set in the third embodiment.

FIG. 15 is a block diagram illustrating a configuration of an image processing apparatus according to a fourth embodiment of the present invention.

FIG. 16 is a flowchart illustrating an operation of the image processing apparatus of FIG. 15 when each element processor calculates a filter selection number.

FIG. 17 is a block diagram illustrating a configuration of an image processing apparatus according to a fifth embodiment of the present invention.

FIG. 18 is a diagram illustrating an example of an original image.

FIG. 19 is a diagram illustrating an example of an image obtained by enlarging an original image.

FIG. 20 is a diagram illustrating an example of a positional relationship between pixels of an original image and pixels of an enlarged image.

FIG. 21 is a diagram illustrating an example of an image obtained by increasing the resolution of an original image.

FIG. 22 is a diagram illustrating an example of an image obtained by reducing an original image.

FIG. 23 is a diagram illustrating an example of a positional relationship between pixels of an original image and pixels of a reduced image.

FIG. 24 is a diagram illustrating an example of an image in which the resolution of an original image is reduced.

FIG. 25 is a diagram illustrating an example of a positional relationship between pixels of an original image and pixels generated by interpolation.

FIG. 26 is a diagram illustrating an example of an interpolation function.

FIG. 27 is a block diagram illustrating a configuration example of a device that performs a filter operation in hardware.

28 is a diagram illustrating an example of signals of each unit in each cycle of the filter operation performed in the device in FIG. 27.

FIG. 29 is a diagram illustrating an example of a correspondence relationship between a filter selection signal and a filter coefficient set.

FIG. 30 is a block diagram illustrating a configuration example of a device that performs a filter operation using software.

31 is a diagram illustrating an example of a supply pattern of input data when an image is enlarged in the apparatus in FIG. 30;

FIG. 32 is a diagram illustrating an example of a positional relationship with an element processor having data necessary for processing.

[Explanation of symbols]

21 input pointer, 22 input SAM part, 23
Data memory section, 24 ALU array section, 25 output SAM section, 26 output pointer, 27, 27A,
27B, 27C, 27D program control unit, 28,
28A, 29 memory

 ────────────────────────────────────────────────── ─── Continued from the front page (72) Inventor Kenichiro Nakamura 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (31)

[Claims] An image data is supplied to a plurality of element processors, and the plurality of element processors are controlled by SIMD.
An image processing apparatus in which each element processor performs processing of the image data in parallel using image data of a peripheral element processor, the peripheral element processor having image data used by a predetermined element processor, An image processing apparatus, wherein the image data is supplied to the plurality of element processors such that the type of the pattern of the positional relationship with the element processor is minimized. 2. An element processor is supplied with information corresponding to the pattern of the positional relationship, and in accordance with the information, image data to be used for processing is read from peripheral element processors to process the image data. The image processing apparatus according to claim 1, wherein: 3. The process of the image data is a process of interpolating a pixel value corresponding to enlargement or reduction of an image. In the process of the interpolation, information generated when calculating a phase of the pixel is used. 3. The image processing apparatus according to claim 2, wherein the information is used as information corresponding to the positional relationship pattern. 4. The apparatus according to claim 1, wherein the element processor is a one-bit processor that processes data one bit at a time. 5. The image processing apparatus according to claim 1, wherein the processing of the image data is processing of interpolating the pixel values in accordance with Cubic approximation. 6. An image data is supplied to a plurality of element processors, and the plurality of element processors are controlled by SIMD.
An image processing method in which each element processor performs processing of the image data in parallel using image data of a peripheral element processor, wherein the peripheral element processor having image data used by a predetermined element processor; An image processing method, comprising: supplying the image data to the plurality of element processors so that a type of a pattern of a positional relationship with the element processor is minimized. 7. Image data is supplied to a plurality of element processors via an input bus, and the plurality of element processors
An image processing apparatus that performs IMD control and performs pixel interpolation processing in parallel with image enlargement or reduction in each element processor. A filter coefficient set used for the interpolation is input to the element processor via the input bus. Wherein the element processor performs the interpolation processing of the image data by using the filter coefficient set. 8. The image processing apparatus according to claim 7, wherein the conversion ratio for enlarging or reducing the image is an integer ratio. 9. The image processing apparatus according to claim 7, further comprising storage means for storing the filter coefficient set and connected to the element processor via the input bus. 10. The image processing apparatus according to claim 9, wherein the storage unit stores K filter coefficient sets when a conversion ratio of enlargement or reduction of the image is K: L. apparatus. 11. The storage unit according to claim 10, wherein the storage unit stores the K filter coefficient sets in the order of phases corresponding to the filter coefficient sets.
An image processing apparatus according to claim 1. 12. The image processing apparatus according to claim 7, wherein said element processor is a one-bit processor that processes data one bit at a time. 13. The processing of the image data is performed by Cubic
The image processing apparatus according to claim 7, wherein the pixel value is interpolated according to approximation. 14. An image data is supplied to a plurality of element processors via an input bus, and the plurality of element processors are subjected to SIMD control so that each element processor performs a pixel interpolation process accompanying an enlargement or reduction of an image. In an image processing method performed in parallel, a filter coefficient set used for the interpolation is supplied to each of the element processors via the input bus, and the element processor uses the filter coefficient set to perform processing on the image data. An image processing method characterized by performing interpolation processing. 15. An image data is supplied to a plurality of element processors via an input bus, and the plurality of element processors are subjected to SIMD control so that each element processor performs a pixel interpolation process accompanying an enlargement or reduction of an image. In an image processing device that performs parallel processing, a filter coefficient set used for the interpolation is supplied to each of the element processors via a circuit different from the input bus, and the element processor uses the filter coefficient set. An image processing apparatus for performing interpolation processing of the image data. 16. The element processor includes a storage unit that stores the filter coefficient set, and an ALU unit that performs an operation. The element processor stores the filter coefficient set, and stores the filter coefficient set in the ALU unit of the element processor via the circuit. The image processing apparatus according to claim 15, further comprising a storage unit connected to the image processing apparatus. 17. The storage unit according to claim 16, wherein the storage unit stores K filter coefficient sets when a conversion ratio of enlargement or reduction of the image is K: L.
An image processing apparatus according to claim 1. 18. The image processing apparatus according to claim 17, wherein the storage unit stores the K filter coefficient sets in a phase order corresponding to the filter coefficient sets. . 19. The image processing apparatus according to claim 19, further comprising a second storage unit configured to store phase information corresponding to image data allocated to the element processor, wherein the storage unit stores the phase information corresponding to the phase information in the second storage unit. The image processing apparatus according to claim 16, wherein the filter coefficient set is supplied to a processor. 20. The element processor calculates phase information corresponding to image data assigned to the element processor, and the filter coefficient set is:
17. The image processing apparatus according to claim 16, wherein the image data is supplied from the storage unit to the element processor. 21. The element processor calculates the phase information by sequentially adding or subtracting one of K and L when a conversion ratio of enlargement or reduction of the image is K: L. 3. The method according to claim 2, wherein
0. The image processing apparatus according to 0. 22. The image processing apparatus according to claim 15, wherein said element processor is a one-bit processor that processes data one bit at a time. 23. The processing of the image data is performed by Cubic
The image processing apparatus according to claim 15, wherein the pixel value is interpolated according to approximation. 24. An image data is supplied to a plurality of element processors via an input bus, and the plurality of element processors are subjected to SIMD control so that each element processor performs a process of interpolating pixels accompanying enlargement or reduction of an image. In an image processing method performed in parallel, a filter coefficient set used for the interpolation is supplied to each of the element processors via a circuit different from the input bus, and the element processor uses the filter coefficient set. And an image processing method for performing interpolation processing of the image data. 25. An image data is supplied to a plurality of element processors via an input bus, and the plurality of element processors are subjected to SIMD control so that each element processor performs a process of interpolating pixels accompanying enlargement or reduction of an image. In an image processing device that performs the processing in parallel, the element processor calculates a filter coefficient set used for the interpolation in accordance with phase information of image data assigned to the element processor, and uses the filter coefficient set. An image processing apparatus that performs interpolation processing of the image data. 26. The image processing apparatus according to claim 25, further comprising a storage unit that stores the phase information. 27. The image processing apparatus according to claim 25, wherein the element processor calculates the phase information. 28. The image processing apparatus according to claim 27, wherein the element processor calculates the phase information using an interpolation function corresponding to the interpolation. 29. The image processing apparatus according to claim 25, wherein said element processor is a one-bit processor that processes data one bit at a time. 30. Processing of the image data is performed by Cubic
26. The image processing apparatus according to claim 25, wherein the pixel value is interpolated according to approximation. 31. Image data is supplied to a plurality of element processors via an input bus, and the plurality of element processors are subjected to SIMD control so that each element processor performs pixel interpolation processing accompanying enlargement or reduction of an image. In an image processing method performed in parallel, the element processor calculates a filter coefficient set used for the interpolation in accordance with phase information of image data assigned to the element processor, and uses the filter coefficient set. And performing an interpolation process on the image data.