JPH10242455A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having no lowering of breakdown voltage between a drain and a source, even in the case of wiring a high-potential drain electrode over an element separation region. SOLUTION: An n+ type drain region 5 is formed approximately in the center inside an element formation region 4, a p-type channel region 6 is formed inside the element formation region 4 explusive of a lower part of a drain electrode 11 and its neighborhood in contact with a p+ type element separation region 3 so as to enclose the n+ type drain region 5, and an n+ type drain region 5, and an n+ type source region 7 is formed inside an element formation region 4 so as to be involved inside the p-type channel region 6 and the p+ type element separation region 3. In the lower part of the drain electrode 11 and in an insulating layer 10 in its neighborhood, an electrode 13 of the long shape is formed approximately in the vertical direction with respect to the longitudinal direction of the drain electrode 11 for being connected to the element formation region 4 through an n+ type impurity region 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art As one of high withstand voltage semiconductor devices, a horizontal type 2 is used.
Double diffusion MOS field effect transistor, so-called LDMO
There is an SFET (Lateral Double Diffused MOSFET). 4A and 4B are schematic cross-sectional views showing an LDMOSFET according to a conventional example, in which FIG. 4A is a schematic plan view showing a state viewed from the surface, and FIG. 4B is a schematic cross-section taken along ZZ ′ in FIG. FIG. In this LDMOSFET, an n-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1, and a p + -type element isolation region 3 is formed so as to reach the p-type semiconductor substrate 1 from the surface of the n-type epitaxial layer 2. Then, a plurality of element forming regions 4 each formed of the n-type epitaxial layer 2 insulated and separated from each other by the p-type semiconductor substrate 1 and the p + -type element isolation region 3 are formed.

As an example of a method for forming the p + -type element isolation region 3, a p-type impurity such as boron (B) is deposited.
There is a method of forming by an oxidation and drive process.

An n-type impurity such as phosphorus (P) is ion-implanted substantially at the center of the element forming region 4 so as to be exposed on the surface of the element forming region 4 to thereby form an n + type drain region
Is formed, and is electrically connected to the n + -type drain region 5, and extends over the p + -type element isolation region 3 to another element formation region 4, and is formed of a drain electrode 11 made of aluminum (Al) or the like. Are formed.

An element formation region surrounds the n + type drain region 5 except for the lower portion of the drain electrode 11 and the vicinity thereof, and is exposed to the surface of the element formation region 4 adjacent to the p + type element isolation region 3. 4, a p-type channel region 6 having a lower concentration than the p + -type element isolation region 3 is formed. Then, an n-type impurity such as phosphorus (P) is ion-implanted so as to be exposed on the surface of the element formation region 4 and included in the p-type channel region 6 and the p + -type element isolation region 3. A source region 7 is formed.

On the p-type channel region 6 interposed between the n + -type drain region 5 and the n + -type source region 7,
An insulating gate 9 made of polysilicon or the like is formed via a gate oxide film 8.

On the n-type epitaxial layer 2, an insulating layer 10 is formed, and a gate electrode (not shown) made of aluminum (Al) or the like is formed so as to be electrically connected to the insulating gate 9. , N + type source region 7 and p +
Source electrode 12 made of aluminum (Al) or the like is formed so as to be electrically connected to mold element isolation region 3.

In such an LDMOSFET, a high potential is applied to the drain electrode 11 and a low potential is applied to the source electrode 12 to deplete the entire element forming region 4 and to form the element forming region 4.
The electric field strength on the surface of the substrate is alleviated to maintain the breakdown voltage between the drain and the source at a high voltage. This is the so-called RESUR
F (Reduced SURface Field) principle is used and "I
nternational Electoronic Device Meeting Techni
cal Digest ", Dec., pp. 238-240 (1979).

The above-mentioned LDMOSFET is useful because a level shifter or the like of a high-side driver circuit can be realized by integrating it on the same chip as other signal processing circuits. When the LDMOSFET is integrated as an IC, as shown in FIG. 4A, an n + type drain region 5 is formed substantially at the center of the element forming region 4 and the periphery thereof is surrounded by an n + type source region 7. When a high voltage is applied to the n + type drain region 5, p
It is necessary to arrange the drain electrode 11 from the outside of the + type element isolation region 3 to the n + type drain region 5 across the p + type element isolation region 3.

[0010]

However, in the LDMOSFET having the above structure, the drain electrode 1
There is a problem that the potential of 1 affects the potential distribution on the surface of the element formation region 4 under the insulating layer 10 immediately below.

FIG. 5 is a schematic diagram showing a potential distribution in an element forming region 4 of an LDMOSFET according to a conventional example.
Is a schematic diagram showing a potential distribution when the drain electrode 11 is not drawn out across the p + -type element formation region 3;
(B) is a schematic diagram showing a potential distribution when the drain electrode 11 is drawn out across the p + -type element formation region 3. As shown in FIG. 5, when the drain electrode 11 is drawn out across the p + -type element formation region 3, the n + -type drain region 5 is extended along the drain electrode 11 by the drain electrode 11 to which a high potential is applied. As a result, an inversion layer is generated in the element formation region 4, and the potential distribution on the surface of the element formation region 4 is concentrated near the p + -type element isolation region 3, which exceeds the critical electric field and lowers the drain-source breakdown voltage. There was a problem of doing.

The present invention has been made in view of the above points, and an object of the present invention is to provide a high withstand voltage between a drain and a source even when a high potential drain electrode is wired across an element isolation region. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which are not reduced.

[0013]

According to the first aspect of the present invention,
A first conductivity type semiconductor substrate, and a high concentration first conductivity type element isolation region formed on one main surface of the first conductivity type semiconductor substrate and formed so as to reach the first conductivity type semiconductor substrate from the surface. An element formation region including a second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate; and a high portion formed substantially at the center of the element formation region so as to be exposed on the surface of the element formation region. A second-concentration second-conductivity-type drain region, and a drain electrically connected to the high-concentration second-conductivity-type drain region and drawn out to another element formation region across the high-concentration first-conductivity-type element isolation region. An electrode, surrounding the high-concentration second-conductivity-type drain region except for the lower part of the drain electrode and its vicinity, and adjacent to the high-concentration first-conductivity-type element isolation region and exposed to the surface of the element formation region; A first conductivity type channel region formed in the element formation region, the high-concentration first conductivity type element isolation region and the first conductivity type channel region so as to be exposed on the surface of the element formation region. A high-concentration second-conductivity-type source region formed in the element formation region; and the first-conductivity-type channel interposed between the high-concentration second-conductivity-type source region and the high-concentration second-conductivity-type drain region. An insulating gate formed on the region via a gate oxide film, a gate electrode formed to be electrically connected to the insulating gate, the high-concentration second conductivity type source region and the high-concentration first conductivity In a semiconductor device having a source electrode formed so as to be electrically connected to a mold element isolation region and an insulating layer formed on the element formation region, a semiconductor device includes Said de The elongated electrode substantially vertically to form a plurality to the longitudinal direction of the in-electrode,
The electrode is brought into contact with the element formation region via a high-concentration second conductivity type impurity region.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the length of the drain electrode in the longitudinal direction is increased from a substantially center of the element forming region toward the outer periphery. It is characterized by having made it.

According to a third aspect of the present invention, there is provided a high-concentration first conductivity type element isolation region formed on a first conductivity type semiconductor substrate so as to reach the first conductivity type semiconductor substrate from a surface. Forming an element formation region composed of a second conductivity type epitaxial layer insulated and separated by a conductivity type semiconductor substrate,
Forming a high-concentration second-conductivity-type drain region substantially at the center of the device-forming region so as to be exposed on the surface of the device-forming region; electrically connecting to the high-concentration second-conductivity-type drain region; Forming a drain electrode extending to the other element formation region across the first concentration type first conductivity type element isolation region, and surrounding the high concentration second conductivity type drain region except for a lower portion of the drain electrode and its vicinity; Forming a first conductivity type channel region in the element formation region adjacent to the high concentration first conductivity type element isolation region and exposed on a surface of the element formation region; Forming a high-concentration second-conductivity-type source region in the element formation region so as to be included in the isolation region and the first-conductivity-type channel region and to be exposed on the surface of the element formation region; Area and front Forming an insulating gate on the first conductive type channel region interposed between the high-concentration second conductive type drain region via a gate oxide film, and forming a gate electrode so as to be electrically connected to the insulating gate. Forming, forming a source electrode so as to be electrically connected to the high concentration second conductivity type source region and the high concentration first conductivity type element isolation region,
In a method of manufacturing a semiconductor device, comprising forming an insulating layer on the element formation region, a second conductive type having a shape elongated in a direction substantially perpendicular to a longitudinal direction of the drain electrode below and near the drain electrode. A plurality of electrodes including impurities are formed, and a second-conductivity-type impurity contained in the electrodes is diffused into the element formation region to form a high-concentration second-conductivity-type impurity region. The semiconductor device is characterized in that it is in contact with the element formation region via a second conductivity type impurity region.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. 1A and 1B are schematic views showing an LDMOSFET according to an embodiment of the present invention, wherein FIG. 1A is a schematic plan view showing a state viewed from above, and FIG. FIG. In this embodiment, the first conductivity type is set to p for convenience of explanation.
Although the type and the second conductivity type will be described as n-type, the invention is also applied to the case where the p-type and the n-type are reversed. Further, the LD according to the present embodiment
The overall structure of a MOSFET is shown in FIG.
Since the overall configuration is the same as that of the DMOSFET, the same portions are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The LDMOSFET according to the present embodiment is different from the LDMOSFET shown in FIG. 4 as a conventional example in that the drain electrode 1 is provided in the insulating layer 10 below the drain electrode 11.
A plurality of electrodes 13 made of polysilicon are formed perpendicularly to the longitudinal direction of the n + -type impurity region 1.
4, it is electrically connected to the element forming region 4 made of the n-type epitaxial layer 2.

Hereinafter, the LDMOSFET according to the present embodiment will be described.
Will be described with reference to the drawings. FIG. 2 is a schematic cross-sectional view illustrating a manufacturing process of the LDMOSFET according to the present embodiment. First, an n-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1, and an insulating layer 10 such as a silicon oxide film is formed on the n-type epitaxial layer 2.

Next, a photoresist (not shown) is applied on the insulating layer 10 and is exposed and developed to pattern the photoresist into a predetermined shape. The patterned photoresist is used as a mask to form the insulating layer 10. An opening (not shown) is formed in the insulating layer 10 on the location where the p + -type element isolation region 3 is formed by etching, and the photoresist is removed by plasma ashing or the like.

Next, a p-type impurity such as boron (B) is deposited, and an n-type epitaxial layer 2 is formed by oxidation and drive steps.
A p + -type element isolation region 3 is formed so as to reach the p-type semiconductor substrate 1 from the surface of the device, and an element formation region including the n-type epitaxial layer 2 insulated and separated by the p-type semiconductor substrate 1 and the p + -type element isolation region 3 4 (FIG. 2)
(A)).

Next, the insulating layer 10 on the element forming region 4 is removed by etching, and the gate oxide film 8 is formed by thermal oxidation or the like.
Is formed, and the gate oxide film 8 below and in the vicinity of a portion where a drain electrode 11 is formed, which will be described later, is removed by etching to form an opening 13a.

A photoresist (not shown) is formed by forming polysilicon in which a large amount of n-type impurities are diffused over the entire surface of the n-type epitaxial layer 2 where the opening 13a is formed, and patterned into a predetermined shape. 2 is used as a mask to form an insulating gate 9 and an electrode 13 made of polysilicon.
(B)). At this time, the electrode 13 is patterned so as to be perpendicular to the longitudinal direction of the drain electrode 11.

Next, a photoresist (not shown) is applied to the surface of the n-type epitaxial layer 2 on which the insulating gate 9 is formed, and the photoresist is patterned into a predetermined shape by performing exposure and development.

Then, using the patterned photoresist and the insulating gate 9 as a mask, a p-type impurity such as boron (B) is ion-implanted, and the photoresist is removed. Among them, the portion excluding the lower portion of the drain electrode 11 and the vicinity thereof is exposed on the surface of the element forming region 4 adjacent to the p + -type element isolation region 3 and is included in the element forming region 4. A p-type channel region 6 is formed.

Next, an n-type impurity such as phosphorus (P) is ion-implanted using a photoresist (not shown) patterned in a predetermined shape as a mask, the photoresist is removed, and annealing is performed to form an element. An n + -type drain region 5 is formed substantially at the center of the region 4 so as to be exposed on the surface of the element formation region 4, and is included in the p + -type device isolation region 3 and the p-type channel region 6. An n + type source region 7 is formed so as to be exposed on the surface (FIG. 2C). By this annealing treatment, the electrode 13
The n-type impurity diffused in a large amount is diffused into the element formation region 4 to form an n + -type impurity region 14.

Finally, an insulating layer 10 such as a silicon oxide film is formed on the entire surface of the n-type epitaxial layer 2 on which the insulating gate 9 is formed, and is electrically connected to the n + -type drain region 5. A drain electrode 11 made of aluminum (Al) or the like is formed so as to extend to the adjacent element formation region 4 across the isolation region 3 and to form an n + type source region 7.
And a source electrode 12 made of aluminum (Al) or the like so as to be electrically connected to the p + -type element isolation region 3, and a gate made of aluminum (Al) or the like so as to be electrically connected to the insulated gate 9. An electrode (not shown) is formed. The insulating gate 9 is arranged on the p-type channel region 6 interposed between the n + -type drain region 5 and the n + -type source region 7 via the gate oxide film 8.

Therefore, in this embodiment, the electrode 13
Is in contact with a region other than the lower portion of the drain electrode 11 and its vicinity in the element formation region 4 via the n + -type impurity region 14, so that the electrode 13 is a region of the element formation region where the drain electrode 11 is not drawn out. 4, the potential of the element forming region 4 under the drain electrode 11 and the vicinity thereof is suppressed, and the potential distribution is made uniform, so that a high breakdown voltage can be achieved.

In this embodiment, the electrode 13 is formed to have the same length in the direction perpendicular to the longitudinal direction of the drain electrode 11. However, the present invention is not limited to this. As shown in FIG.
From the approximate center to the outer periphery of the element forming region 4,
The electrode 13 may be formed such that the length in the direction perpendicular to the longitudinal direction of the drain electrode 11 is increased. That is,
As the potential difference between the drain electrode 11 and the element formation region 4 increases toward the outer periphery of the element formation region 4 and the depletion layer further extends, the electrode 13 is connected to the element formation region 4 farther from the drain electrode 11 and the n + type. Impurity region 14
, The influence of the potential on the lower part of the drain electrode 11 and the element forming region 4 near the drain electrode 11 is further suppressed, the potential distribution is made uniform, and the breakdown voltage can be increased.

Further, in the present embodiment, the p-type channel region 6 is not formed below the drain electrode 11 and in the vicinity thereof, but it is not necessarily limited to this.

[0029]

According to the first aspect of the present invention, the first conductive type semiconductor substrate is formed on one main surface of the first conductive type semiconductor substrate and formed so as to reach the first conductive type semiconductor substrate from the surface. An element formation region comprising a high-concentration first conductivity type device isolation region and a second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate; The high-concentration second conductivity type drain region formed substantially at the center of the semiconductor device and the high-concentration second conductivity type drain region are electrically connected to the other element formation regions across the high-concentration first conductivity type element isolation region. The extracted drain electrode and the high-concentration second-conductivity-type drain region are surrounded except for the lower portion and the vicinity of the drain electrode, and are adjacent to the high-concentration first-conductivity-type element isolation region and exposed on the surface of the element formation region. like The first conductivity type channel region formed in the element formation region, the high concentration first conductivity type element isolation region and the first conductivity type channel region are included in the element formation region so as to be exposed on the surface of the element formation region. A high-concentration second conductivity type source region formed on the first conductivity type channel region interposed between the high-concentration second conductivity type source region and the high-concentration second conductivity type drain region. An insulating gate formed through the gate, a gate electrode formed to be electrically connected to the insulating gate, and electrically connected to the high-concentration second conductivity type source region and the high-concentration first conductivity type element isolation region A semiconductor device having a source electrode formed so as to be formed, and an insulating layer formed on an element formation region, in a direction substantially perpendicular to a longitudinal direction of the drain electrode at and below the drain electrode. Long A plurality of electrodes are formed, and the electrodes are brought into contact with the element formation region via the high-concentration second conductivity type impurity region, so that the electrodes have the same potential as the element formation region where the drain electrode is not drawn out, and the drain The influence of the potential on the element formation region below the electrode and in the vicinity thereof is suppressed, the potential distribution is made uniform, and even when a high-potential drain electrode is wired across the element isolation region, the drain-source A semiconductor device without a decrease in breakdown voltage can be provided.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the length of the drain electrode in the longitudinal direction increases from substantially the center to the outer periphery of the element formation region. Further, the influence of the potential on the lower part of the drain electrode and the element formation region in the vicinity thereof is suppressed, and the potential distribution is made uniform.

According to a third aspect of the present invention, there is provided a high-concentration first conductivity type element isolation region formed on a first conductivity type semiconductor substrate so as to reach the first conductivity type semiconductor substrate from a surface. Forming an element formation region comprising a second conductivity type epitaxial layer insulated and separated by a semiconductor substrate, and forming a high concentration second conductivity type drain region substantially at the center of the element formation region so as to be exposed on the surface of the element formation region Forming a drain electrode that is electrically connected to the high-concentration second conductivity type drain region and is drawn out to another element formation region across the high-concentration first conductivity type element isolation region; Except for the vicinity of the high-concentration second-conductivity-type drain region except for the vicinity thereof, the first-conductivity-type channel region is adjacent to the high-concentration first-conductivity-type element isolation region and is exposed in the element formation region so as to be exposed on the surface of the element formation region. Forming a high-concentration second-conductivity-type source region in the element formation region so as to be included in the high-concentration first-conductivity-type element isolation region and the first-conductivity-type channel region and exposed on the surface of the element formation region. Forming an insulating gate via a gate oxide film on the first conductivity type channel region interposed between the high concentration second conductivity type source region and the high concentration second conductivity type drain region, and electrically connecting to the insulation gate. A gate electrode is formed so as to be connected, and a source electrode is formed so as to be electrically connected to the high-concentration second conductivity type source region and the high-concentration first conductivity type element isolation region, and is insulated on the element formation region. In a method of manufacturing a semiconductor device comprising forming a layer, a plurality of electrodes including a second conductivity type impurity are formed below and in the vicinity of the drain electrode, the shape being long in a direction substantially perpendicular to the longitudinal direction of the drain electrode. To the electrode Since the high concentration second conductivity type impurity region was formed by diffusing the doped second conductivity type impurity into the element formation region, and the electrode was brought into contact with the element formation region via the high concentration second conductivity type impurity region, The electrode has the same potential as the element formation region in the region where the drain electrode is not drawn out, and the influence of the potential on the element formation region below the drain electrode and in the vicinity thereof is suppressed,
It is possible to provide a method for manufacturing a semiconductor device in which the potential distribution is made uniform and the withstand voltage between the drain and the source does not decrease even when a high-potential drain electrode is wired across element isolation regions. Was.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic views showing an LDMOSFET according to an embodiment of the present invention, wherein FIG. 1A is a schematic plan view showing a state viewed from above, and FIG. FIG.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the LDMOSFET according to the embodiment.

FIG. 3 shows an LDMOSFET according to another embodiment of the present invention.
(A) is a schematic plan view showing a state viewed from above, and (b) is a schematic cross-sectional view taken along the line YY 'in (a).

4A and 4B are schematic views showing an LDMOSFET according to a conventional example, in which FIG. 4A is a schematic plan view showing a state viewed from above, and FIG. 4B is a schematic cross-sectional view taken along line ZZ ′ in FIG. It is.

5A and 5B are schematic diagrams showing a potential distribution in an element formation region of an LDMOSFET according to a conventional example, and FIG. 5A is a schematic diagram showing a potential distribution when a drain electrode is not drawn out across ap + -type element formation region. (B) is a schematic diagram showing a potential distribution when the drain electrode is drawn out to the outside across the p + -type element formation region.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type semiconductor substrate 2 n-type epitaxial layer 3 p + -type element isolation region 4 element formation region 5 n + -type drain region 6 p-type channel region 7 n + -type source region 8 gate oxide film 9 insulated gate 10 insulating layer 11 drain electrode 12 source Electrode 13 Electrode 13a Opening 14 n + type impurity region

Claims (3)

[Claims] A first conductive type semiconductor substrate; and a high-concentration first semiconductor substrate formed on one main surface of the first conductive type semiconductor substrate and formed to reach the first conductive type semiconductor substrate from the surface. An element formation region including a conductive type element isolation region and a second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate; and a substantially center in the element formation region so as to be exposed on a surface of the element formation region. The high-concentration second conductivity type drain region formed in the, and is electrically connected to the high-concentration second conductivity type drain region, straddling the high-concentration first conductivity type element isolation region to the other element formation region A drain electrode that is drawn out, surrounds the high-concentration second conductivity type drain region except for a lower portion of the drain electrode and its vicinity, and is adjacent to the high-concentration first conductivity type element isolation region; surface A first conductivity type channel region formed in the element formation region so as to be exposed to the high concentration first conductivity type device isolation region and the first conductivity type channel region; A high-concentration second-conductivity-type source region formed in the element formation region so as to be exposed, and the second high-concentration second-conductivity-type drain region interposed between the high-concentration second-conductivity-type source region and the high-concentration second-conductivity-type drain region. An insulated gate formed on the one conductivity type channel region via a gate oxide film; a gate electrode formed to be electrically connected to the insulated gate; In a semiconductor device having a source electrode formed so as to be electrically connected to a first conductivity type element isolation region and an insulating layer formed on the element formation region, a lower portion of the drain electrode And its A plurality of electrodes having a shape that is long in a direction substantially perpendicular to the longitudinal direction of the drain electrode are formed on the side, and the electrodes are brought into contact with the element formation region via a high-concentration second conductivity type impurity region. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the length of the drain electrode in the longitudinal direction increases from a substantially center of the element formation region to an outer periphery of the element formation region. 3. A high-concentration first-conductivity-type element isolation region formed on a first-conductivity-type semiconductor substrate so as to reach the first-conductivity-type semiconductor substrate from the surface and insulated by the first-conductivity-type semiconductor substrate. Forming an element formation region consisting of the separated second conductivity type epitaxial layer, forming a high concentration second conductivity type drain region substantially at the center of the element formation region so as to be exposed on the surface of the element formation region; A drain electrode electrically connected to the high-concentration second-conductivity-type drain region and extending to the other element formation region across the high-concentration first-conductivity-type element isolation region; Except for the lower part and the vicinity thereof, surrounding the high-concentration second conductivity type drain region, adjacent to the high-concentration first conductivity type element isolation region, and inside the element formation region so as to be exposed on the surface of the element formation region. Forming a first conductivity type channel region,
Included in the high-concentration first-conductivity-type element isolation region and the first-conductivity-type channel region, forming a high-concentration second-conductivity-type source region in the element formation region so as to be exposed on the surface of the element formation region, Forming an insulating gate via a gate oxide film on the first conductivity type channel region interposed between the high concentration second conductivity type source region and the high concentration second conductivity type drain region; Forming a gate electrode so as to be electrically connected; forming a source electrode so as to be electrically connected to the high-concentration second conductivity type source region and the high-concentration first conductivity type element isolation region; In a method for manufacturing a semiconductor device in which an insulating layer is formed on a formation region, a second conductivity type impurity having a shape elongated in a direction substantially perpendicular to a longitudinal direction of the drain electrode is provided below and near the drain electrode. Comprise A plurality of electrodes, and forming a high-concentration second-conductivity-type impurity region by diffusing a second-conductivity-type impurity contained in the electrode into the element formation region. A method for manufacturing a semiconductor device, comprising: contacting the element formation region via an impurity region.