JPH10242305A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the gate width of a bank cell as much as possible, without increasing the area of the bank region by connecting a conductive layer to an impurity-diffused layer through openings of gate electrodes existing on this diffused layer. SOLUTION: Bank regions BANK0-2 corresponding to blocks are provided on a predetermined surface region of a first-conductivity-type (p-type) semiconductor substrate. The region BANK1 comprises a plurality of width bit lines SB1A-SB7A of a second-conductivity-type diffused layer on the substrate, a plurality of polysilicon word lines WL1A-WL32A crossing the width bit lines and memory cells disposed between the adjacent width bit lines; the cells using the word lines as gate electrodes. Auxiliary conductive regions BB11, 12, BB21, 22 are connected to main bit lines and main ground lines of metal wrings through contact holes C11, 12, C21, 22 formed at each opening, thereby increasing the bit line current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor memory device having a mask programmable ROM, and more particularly to a hierarchical bit line system having a main bit line and a sub bit line as bit lines. RO
More specifically, the present invention relates to a semiconductor memory device including a high density ROM memory cell circuit using double poly gate electrodes.

[0002]

2. Description of the Related Art As a memory cell system of a mask ROM, a directly connected cell transistor is connected in parallel with a NAND type ROM for writing ROM data by selecting an enhancement type transistor and a depletion type transistor. There is a NOR-type ROM in which the threshold voltage is selectively set to be equal to or higher than the power supply voltage and the ROM data is written to the selected cell transistor. In general, NAND ROM is excellent in high integration and NOR ROM
Is superior in speeding up, but the opposite is inferior to each other.

[0003] Therefore, developments have been made to further increase the integration by using a NAND type ROM by utilizing this feature. However, in the NAND type ROM, a dimensional shift or a level difference of an element isolation region occurs, which causes a failure. Has become. In addition, the conventional N
A high-density NOR-type ROM memory cell system having both the advantages of the OR-type ROM and the NAND-type ROM is partially adopted.

In this memory cell, a plurality of high-concentration diffusion regions serving as source / drain regions of cell transistors and bit line wirings are formed in parallel in a memory cell region having no element isolation oxide film. A plurality of gate electrodes are formed in parallel on the region so as to be orthogonal to the high-concentration diffusion region serving as a bit line wiring via a gate insulating film.

Thus, in the above memory cell,
Since an element isolation oxide film such as a LOCOS film is not used, the substrate surface is flat, and a processing pitch equal to or less than the processing limit usually used can be obtained. In addition, after the gate electrode is formed, this gate electrode is used as a mask. Since element isolation is performed by self-aligned ion implantation into the element isolation region, there is a great effect on high integration.

[0006] However, the demand for increasing the capacity of a semiconductor device is very severe, and further higher integration is being studied. For example, NAN suitable for high integration as described above
In a D-type ROM or a high-density NOR-type ROM, there is a method of increasing the density of memory cells by forming a gate electrode in a multilayer structure in order to achieve higher integration. JP-A-53-41
No. 188 discloses a NAND-type ROM,
No. 131568 proposes a semiconductor device using a two-layer gate electrode for a high density NOR type ROM.

Further, Japanese Patent Laid-Open No.
No. 4,104,406 proposes a hierarchical bit line system. In this method, a plurality of sub-bit lines are connected to a main bit line via a selection transistor to form a hierarchical structure. Hereinafter, the hierarchical bit line system will be described.
FIG. 21 shows a layout pattern of a memory adopting the hierarchical bit line system, and FIG. 22 shows an equivalent circuit diagram of the memory.

In FIG. 21, reference numeral 200 denotes a hierarchical bit line type ROM which includes a semiconductor substrate 200a of a first conductivity type, and a predetermined surface area of the semiconductor substrate 200a is divided into a plurality of blocks. Correspondingly, bank areas BANK0, BANK1, BANK2,... Are provided. For example, the bank region BANK1 includes a plurality of sub-bit lines SB1A to SB7A formed of a diffusion layer of the second conductivity type formed on the semiconductor substrate 200a and a plurality of word lines formed of polysilicon crossing the sub-bit lines SB1A to SB7A. WL
1A, WL2A... WL32A, and memory cells M arranged between adjacent sub-bit lines and having word lines as gate electrodes. Here, the memory cells M1 to M7 use the word line WL2A as a gate electrode.

The bank region BANK1 includes auxiliary conductive regions BB11 and BB12 of the same conductivity type as the sub-bit line, which are disposed at one end of the sub-bit line, and sub-bits, which are disposed at the other end of the sub-bit line. Auxiliary conductive region B of the same conductivity type as the line
B21, BB22, and a bank selection transistor (bank cell) BT1 formed between the auxiliary conductive region and the sub-bit line.
A to BT4A, and bank selection lines BS1A to BS4A made of polysilicon to be gate electrodes of the bank cells. Here, a bank cell BT3A is formed between the other end of the sub-bit line SB2A and the auxiliary conductive region BB21, and a bank cell BT3A is formed between the one end of the sub-bit line SB3A and the auxiliary conductive region BB11. BT2
A is formed, and a bank cell BT1 is provided between one end of the sub-bit line SB5A and the auxiliary conductive region BB11.
A is formed, and a bank cell BT4A is formed between the other end of the sub-bit line SB4A and the auxiliary conductive region BB22. The word lines WL1A, WL1
Bank selection lines BS1A-B arranged in parallel with 2A.
S4A is a gate of each of the bank cells BT1A to BT4A.

The auxiliary conductive regions BB11 and BB12 are connected to main bit lines MB1 and MB2, which are metal wirings, via contact holes C11 and C12, respectively. The auxiliary conductive regions BB21 and BB22 are connected to the contact holes C21 and C22, respectively. Through the main ground lines MG1 and MG2, which are metal wirings. The bank region BANK2 is formed on the second semiconductor substrate 200a.
A plurality of sub-bit lines SB1B-S made of conductive diffusion layers
B7B, a plurality of word lines WL1B made of polysilicon intersecting with this, and a memory cell M formed between adjacent sub-bit lines and having the word line as a gate electrode. .

The bank region BANK2 shares the same conductivity type auxiliary conductive regions BB11 and BB12 as the sub-bit lines, which are arranged on the other end side of the sub-bit lines SB1B to SB7B, with the bank region BANK1. . Here, the other end portion of the sub-bit line SB3B and the auxiliary conductive region BB1
1, a bank cell BT2B is formed, and a bank cell BT1B is formed between the other end portion of the sub-bit line SB5B and the auxiliary conductive region BB11. Further, bank selection lines BS1B, which are arranged in parallel with the word lines,
BS2B is the gate of bank cell BT1B and bank cell BT2B, respectively.

Next, the operation will be briefly described. In addition,
In the following description, it is assumed that the conductivity type of the semiconductor substrate is P-type, and the sub-bit lines and the auxiliary conductive regions are N ⁺ -type. Selection of a bank cell or a memory cell can be performed by setting the potential of a corresponding bank selection line or word line to a high level. Further, the threshold value of the bank cell or the memory cell increases with an increase in the amount of boron ions implanted into the gate region, and can be adjusted by the amount of ions implanted. A bank cell or a memory cell whose threshold value has been raised can be an off cell that maintains an off state even when the word line potential is at a high level, while the other bank cell or memory cell can be an on cell. The region BAR of the arrangement region of the bank selection line where the bank cell is not formed is set to be in an off state by ion implantation regardless of the potential of the bank selection line.

When one memory cell included in one bank region is selected, a word line serving as a gate electrode of the memory cell is set to a high level, and is connected to a sole and a drain of the memory cell. The bank select line, which is the gate electrode of the bank cell connected to the sub-bit line, is set to a high level. Specifically, when selecting the memory cell M4 in the bank area BANK1, the word line WL2
A, the bank selection lines BS1A and BS4A are set to a high level,
Select the bank cells BT1A and BT4A. As a result, these sub-bit lines SB5A and SB4A are connected to main bit line MB1 and main ground line MG2 via contact holes C11 and C22. At this time, the main ground line MG2 is connected to GND, and the main bit line MB1 is connected to the data line, and the information of the memory cell is read.

The above-described hierarchical bit line type ROM memory array configuration has been used in the above-described two-layer poly gate ROM.

[0015]

As described above, in the conventional hierarchical bit line system, a bank cell is provided for each sub-bit line, and as many bank selection lines as the number of bank cells connected to the common auxiliary conductive region are required. As a result, the area occupied by the bank cells in the memory cell array increases. Further, since the sub-bit line and the main bit line are connected via the bank cell, when the gate width of the bank cell is reduced, the bit line current decreases and the read time increases. Therefore, the gate width of the bank cell needs to be as large as possible. However, an increase in the gate width causes an increase in the area of the bank region, that is, an increase in the area of the memory cell array.

That is, by increasing the gate width of the bank cell, the bit line current can be increased, and the read margin of the memory cell can be increased.
On the other hand, the area of the memory cell array was increased. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a semiconductor memory device which can maximize the gate width of a bank cell without increasing the area of a bank region and which is effective for high speed operation. It is an object.

[0017]

According to the present invention, an impurity diffusion layer formed on a surface of a semiconductor substrate, a gate electrode formed on a semiconductor substrate including the impurity diffusion layer via an insulating film, A conductive layer formed above the gate electrode, wherein the conductive layer is connected to the impurity diffusion layer through an opening formed in the gate electrode existing on the impurity diffusion layer. A semiconductor device is provided.

A hierarchical bit line system having a memory cell array arranged in a matrix and a bit line including a main bit line and a plurality of sub-bit lines connected to the main bit line via selection transistors, respectively. Wherein the memory cell and the selection transistor forming the memory cell array have a two-layer gate electrode structure in which first gate electrodes and second gate electrodes are alternately arranged in parallel. Provided.

Furthermore, a hierarchical bit line system having a memory cell array arranged in a matrix and a bit line composed of a main bit line and a plurality of sub-bit lines connected to the main bit line via selection transistors, respectively. The semiconductor device according to claim 1, wherein the main bit line is connected to one terminal of the selection transistor through an opening formed in the selection line constituting the selection transistor.

Further, according to the present invention, there are provided memory cell arrays having a plurality of word lines arranged in parallel in a row direction and arranged in rows and columns, and arbitrary word lines arranged at both ends of the memory cell array. A plurality of select transistors for selecting a memory cell column, a plurality of sub-bit lines formed by a plurality of diffusion layers in parallel in the column direction and connected to the memory cell arrays, respectively, and for each two columns of the memory cell array, A main bit line formed of a metal layer and extending in the column direction; and a sub-bit line adjacent in the row direction is alternately connected to one terminal of the selection transistor at one end or the other end. And the other terminals of the select transistors connected to the adjacent sub-bit lines are respectively passed through openings formed in select lines constituting the select transistors.
A semiconductor device connected to different main bit lines is provided.

Furthermore, according to the present invention, a plurality of memory cell arrays having word lines arranged in parallel in the row direction and arranged in rows and columns at both ends of the memory cell array are provided. A plurality of select transistors for selecting a memory cell column, a plurality of sub-bit lines formed by a plurality of diffusion layers in parallel in the column direction and connected to the memory cell arrays, respectively, and for each two columns of the memory cell array, A main bit line formed of a metal layer and extending in the column direction, and a sub-bit line adjacent in the row direction is alternately connected to one terminal of the selection transistor at one end or the other end. The first sub-bit line of the four sub-bit lines adjacent in the row direction is arranged on one end side of the memory cell array so as to straddle the bank adjacent in the column direction, and The first sub-bit line is connected to one terminal of the first transistor by the first sub-bit line and shares the first selection transistor, and the third sub-bit line of the four sub-bit lines adjacent in the row direction is: One end of the memory cell array is connected to one terminal of a second selection transistor, and the second and fourth sub-bit lines of the four sub-bit lines adjacent in the row direction are connected to the other end of the memory cell array. On the side, each is connected to one terminal of a third and fourth selection transistor, and the other terminal of the first and second selection transistors is passed through an opening formed in a selection line constituting the first selection transistor. And a semiconductor device connected to the same main bit line.

According to the method of the present invention, a source / drain, a sub-bit line, and an auxiliary conductive region forming a memory cell array are formed on a semiconductor substrate, and the semiconductor substrate is provided with:
A plurality of parallel word lines and select lines constituting a memory cell array are formed via a gate insulating film, an opening is formed in a select line above a part of the auxiliary conductive region, and the word lines and select lines are formed. Forming a sidewall insulating film on the wire,
An interlayer insulating film is deposited on the entire surface of the obtained semiconductor substrate, a resist pattern for forming a contact is formed on the opening of the selection line, and the resist pattern is self-aligned by using the opening. There is provided a method of manufacturing a semiconductor device, comprising forming a small contact opening.

According to the method of the present invention, a source / drain constituting a memory cell array is formed on a semiconductor substrate.
Forming a plurality of parallel first word lines and a first selection line forming a memory cell array on the semiconductor substrate via a first gate insulating film; An opening is formed in a first selection line above a part of the auxiliary conductive region, a sidewall insulating film is formed in the first word line and the first selection line, and a second gate is formed on the obtained semiconductor substrate. A plurality of parallel second word lines and second word lines constituting a memory cell array are interposed via an insulating film.
Forming a selection line, forming an opening in the second selection line above a part of the auxiliary conductive region, forming a sidewall insulating film in the opening of the second selection line, Depositing an interlayer insulating film over the entire surface, forming a resist pattern for forming a contact with the openings of the first and second selection lines, and using the openings of the first and second selection lines;
There is provided a method of manufacturing a semiconductor device, comprising forming a contact opening smaller than the resist pattern in a self-aligned manner.

Further, according to the manufacturing method of the present invention, a source / drain, a sub-bit line, and an auxiliary conductive region forming a memory cell array are formed on a semiconductor substrate, and a first gate is formed on the semiconductor substrate. Forming, via an insulating film, a plurality of first word lines and a first selection line that are parallel to each other and forming a memory cell array; forming an opening in the first selection line on a part of the auxiliary conductive region; The first word line and the first word line;
A side wall insulating film is formed on the selection line, and a plurality of second word lines and a second selection line parallel to each other forming a memory cell array are formed on the obtained semiconductor substrate via a second gate insulating film. Depositing an interlayer insulating film over the entire surface of the obtained semiconductor substrate, forming a resist pattern for forming a contact with the opening of the first selection line, and utilizing the opening of the first selection line. A method for manufacturing a semiconductor device, comprising forming a contact opening smaller than the resist pattern in a self-aligned manner.

According to the manufacturing method of the present invention, a source / drain, a sub-bit line, and an auxiliary conductive region forming a memory cell array are formed on a semiconductor substrate, and a first gate is formed on the semiconductor substrate. Forming a plurality of first word lines and first selection lines parallel to each other forming a memory cell array via an insulating film, and forming a side wall insulating film on the first word lines and the first selection lines; A plurality of parallel second word lines and second selection lines forming a memory cell array are formed on a semiconductor substrate via a second gate insulating film, and a second word line and a second selection line are formed on a part of the auxiliary conductive region. An opening is formed in the selection line, a sidewall insulating film is formed in the opening of the second selection line, an interlayer insulating film is deposited on the entire surface of the obtained semiconductor substrate, and an opening is formed in the opening of the second selection line. Contact formation Forming a fit of the resist pattern, using an aperture of the second select line, the method of manufacturing a semiconductor device comprises forming a small contact openings from the resist pattern by self-alignment is provided.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention comprises at least an impurity diffusion layer formed on a surface of a semiconductor substrate, a gate electrode formed on a semiconductor substrate including the impurity diffusion layer via an insulating film, and Any semiconductor device may be used as long as it includes a conductive layer formed above the gate electrode. In such a semiconductor device, the conductive layer is formed through the opening formed in the gate electrode over the impurity diffusion layer. One of its features is that it has a structure for taking out a contact portion connected to a layer. Such a contact portion take-out structure includes ROM, DRA
The present invention can be applied to various semiconductor devices such as a memory device such as M and other logic devices.

The semiconductor substrate forming this semiconductor device may have any conductivity type of N-type or P-type. Further, the semiconductor substrate may include a high-concentration region containing N-type or P-type impurities, A well or the like may be formed. The semiconductor device of the present invention not only has a structure for taking out a contact portion connecting the impurity diffusion layer and the conductive layer,
The semiconductor device in the case where this contact take-out structure is used in a hierarchical bit line type memory or the like applied to the connection between a sub-bit line made of an impurity diffusion layer and a main bit line made of a metal layer. You may. Such a hierarchical bit type semiconductor device including a memory cell array and main and sub-bit lines generally has a sub-bit line connected to each memory cell forming the memory cell array at both ends of the memory cell array. And a connection to the main bit line via the The main bit line may be connected to one terminal of the selection transistor through an opening formed in the selection line constituting the selection transistor, or when a plurality of selection transistors are formed around the opening. May be connected to one terminal of a select transistor constituted by another select line other than the select line in which the opening is formed. In addition,
The diffusion layer forming the sub-bit line preferably has the ion species forming the diffusion layer at a concentration of about 10 ²⁰ cm ⁻³ , and the metal layer forming the main bit line is preferably A
l, Cu, Pt, refractory metals (eg, W, Ta, Ti
Etc.) can be used. The number of sub-bit lines connected to one main bit line is not particularly limited, but is preferably, for example, about 2 to 8, and the main bit line and each sub-bit line are The connection may be through a selection transistor, or may be through two or more selection transistors connected in parallel.

The semiconductor device of the present invention has a single-layer gate electrode structure and a two-layer gate electrode in which first and second gate electrodes are alternately formed in parallel as long as it has such a contact portion extraction structure. It can be used as a memory cell having a structure or a multilayer gate electrode structure. For example, in the case of a single-layer gate electrode structure, a word line (gate electrode) forming a memory cell array and a selection line (gate electrode) forming a selection transistor are formed by patterning the same gate electrode layer. Therefore, at both ends of the memory cell array, openings are respectively formed in the selection lines. In the case of a two-layer gate electrode structure,
Depending on the number of word lines in the memory cell array, a selection line having an opening may be formed by the same gate electrode layer at both ends of the memory cell array, or the opening may be formed by different gate electrode layers, as described above. May be formed. The gate electrode can be formed by a known method such as a CVD method using a material which can be generally used as a gate electrode or a word line, for example, polysilicon, silicide, or the like.

Further, the semiconductor device of the present invention mainly comprises
The present invention can be applied to a memory such as a ROM including one or a plurality of banks each including a memory cell array, a selection transistor, a sub-bit line, and a main bit line arranged in a matrix. In a semiconductor device used as this memory, a plurality of sub-bit lines are formed in a row direction, and a plurality of selection transistors in which adjacent sub-bit lines are alternately formed at one end or the other end. Is connected to one terminal of one of the selection transistors.

In the above-described semiconductor device used as a memory, the other terminals of the select transistors connected to adjacent sub-bit lines are different from each other through openings formed in the select lines constituting the select transistors. It has a contact take-out structure connected to the main bit line. Note that the selection line here is 1 as described above.
It may have any of a layer gate electrode structure and a two-layer gate electrode structure, and its shape is the same as that of the gate electrode in the memory cell array, line width, in terms of ease of processing. These are preferably formed in parallel with each other. However, for example, depending on the case where the drive capability of the select transistor is changed, or the layout of the select transistor, the shape may be changed so that the line width of one select line is partially different,
The line width of each selection line may be changed variously.

Further, in the above-described semiconductor device used as a memory, for example, four sub-bit lines in a memory cell array are taken as one unit, and one sub-bit line is extended to an adjacent bank. And may be shared and used. Further, two or more sub-bit lines may be shared with an adjacent bank. For example, when two sub-bit lines are shared with an adjacent bank, it is preferable to share the two adjacent bit lines with adjacent banks on different sides. Preferably, two of the four sub-bit lines are connected to one end of the memory cell array, and the other two are connected to a select transistor arranged at the other end of the memory cell array. In the connection between the contact and the main bit line, the above-described contact extraction structure is used. The number of sub-bit lines as one unit is not particularly limited to four, and may be laid out with more than that, for example, six or eight. Further, the number of sub-bit lines connected to the same main bit line may be changed correspondingly. Furthermore, a separation band may be provided for each predetermined number of sub-bit lines, that is, for each predetermined number of memory cell array columns, to prevent conduction of the memory cells. For such a separation band, various methods usually used for element isolation can be used.
It is preferable to arrange at a concentration of about ^{18 ~10 19} cm ^-3.

In the semiconductor device as described above, each step itself is a known method, for example, lamination of a conductive film or an insulating film by ion implantation, CVD or vapor deposition, patterning or opening formation by photolithography and etching, and the like. , And the details will be described in the following examples. Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments.

Embodiment 1 A plan view and a circuit diagram of a memory cell of a mask ROM which is an example of a semiconductor device of the present invention are shown in FIG.
These are shown in FIGS. 1 and 2, respectively. FIG. 3 is a sectional view taken along the line AA 'of FIG.

The memory cell of this mask ROM is a high-density NOR type ROM as disclosed in Japanese Patent Laid-Open No. 6-104406.
In a memory cell, the present invention relates to a configuration of a bank selection line connected to a high-concentration diffusion wiring portion, which is a sub-bit line, and a contact region between the bank selection line and a main bit line. As shown in FIG. 1, reference numeral 101 denotes a hierarchical bit line type ROM, and a first conductivity type P-type semiconductor substrate 200.
a, the predetermined surface area of the semiconductor substrate 200a is divided into a plurality of blocks, and bank areas BANK0, BANK1, BANK2,... are provided corresponding to each block.

For example, the bank region BANK1 is composed of a plurality of sub-bit lines SB1A to SB7A formed of a diffusion layer of the second conductivity type formed on the semiconductor substrate 200a and a plurality of polysilicon lines intersecting the sub-bit lines SB1A to SB7A. Word line W
., WL32A, and a memory cell M disposed between adjacent sub-bit lines and having a word line as a gate electrode. Here, the memory cells M1 to M7 are
The word line WL2A is used as a gate electrode.

The bank region BANK1 is composed of auxiliary conductive regions BB11 and BB12 of the same conductivity type as the sub-bit line, arranged on one end of the sub-bit line, and sub-bits arranged on the other end of the sub-bit line. Auxiliary conductive region B of the same conductivity type as the line
B21, BB22, and a bank selection transistor (bank cell) BT1 formed between the auxiliary conductive region and the sub-bit line.
A to BT4A, and bank selection lines BS1A to BS4A made of polysilicon to be gate electrodes of the bank cells. Here, a bank cell BT3A is formed between the other end of the sub-bit line SB2A and the auxiliary conductive region BB21, and a bank cell BT3A is formed between the one end of the sub-bit line SB3A and the auxiliary conductive region BB11. BT2
A is formed, a bank cell BT1A is formed between the sub-bit line SB5A and the auxiliary conductive region BB11, and a bank cell BT4A is formed between the sub-bit line SB4A and the auxiliary conductive region BB22. The bank selection lines BS1B, BS2A to BS4A arranged in parallel with the word lines WL1A, WL2A... Are gates of the bank cells BT1A to BS4A. Note that an element isolation region FD is formed in a desired region below the bank selection line.

The auxiliary conductive regions BB11 and BB12 are connected to main bit lines MB1 and MB2 (not shown), which are metal wirings, via contact holes C11 and C12, respectively. The auxiliary conductive regions BB21 and BB22 are Via holes C21 and C22, they are connected to main ground lines MG1 and MG2 (not shown) which are metal wirings.

Further, the bank area BANK2 is
1 and the sub-bit lines SB1B to SB1
7B, the auxiliary conductive regions BB11 and BB12 of the same conductivity type as the sub-bit line are connected to the bank region BANK.
Share with one. Here, the sub-bit line SB3
A bank cell BT2B is formed between the other end portion of B and the auxiliary conductive region BB11, and a bank cell BT1A is formed between the sub-bit line SB5B and the auxiliary conductive region BB11. The bank selection lines BS1B and BS2B arranged in parallel with the word lines serve as gates of the bank cells BT1A and BT2B, respectively.

The bank area BANK0 is also the bank area BAN
Like K1 and BANK2, it has a plurality of sub-bit lines, a plurality of word lines, and a plurality of bank selection lines, and further shares auxiliary conductive regions BB21 and BB22 with the bank region BANK1. The sub-bit lines SB1A to SB7A of the bank area BANK1 and the bank area BANK2
Of the sub-bit lines SB1B to SB7B are partially adjacent to each other (SB1A and SB1B, SB5A).
And SB5B) are extended and connected to each other. Therefore, the phase-connected sub-bit lines SB5A and SB5
Bank cells BT1A formed between B and the auxiliary conductive region BB11 are shared with each other.

Hereinafter, the features of the mask ROM will be described in more detail. The bank selection lines BS1B (3 in FIG. 3) and BS which are also used in adjacent bank areas
4A are auxiliary conductive regions BB11 (2 in FIG. 3), BB12
BB21, BB21, and BB22, and the auxiliary conductive regions BB11, BB12, B
The main bit lines (in FIG. 2, MB1: FIG. 3) are connected to B21 and BB22.
Middle 4), contact holes C11 and C with ground line
12, C21 and C22 are formed. Note that the word lines 3c of the memory cells are formed in parallel with the bank selection lines 3a and 3b, respectively, at a constant interval.

With such a structure, the gate width of the bank cell BT1A can be maximized efficiently and the bit line current can be increased. If the gate width of the bank cell BT1A and the gate widths of the bank cells BT2A and BT2B are set to be the same, the bit line current can be equal regardless of the selected bank cell.
Thereby, the read margin can be increased.

In such a memory cell, for example, when reading the memory cell M4, the word line WL2A and the bank selection lines BS1B and BS4A are set to the high level, and the bank cells BT1A and BT4A are selected. Thereby, the sub-bit lines SB5A, SB4 connected to both ends of the memory cell M4
A is connected to the main bit line MB1 and the ground line MG2 via the contact holes C11 and C22.

Embodiment 2 FIGS. 4 to 6 are plan views of memory cells of a mask ROM which is another example of the semiconductor device of the present invention.
Shown in 4 to 6 are sectional views taken along line BB 'of FIG.
7 to 9 are sectional views taken along the line C ′ and line DD ′, respectively.
Shown in The circuit diagrams of the memory cells of the mask ROM of FIGS. 4 to 6 are the same as those of FIG.

This hierarchical bit line type mask ROM 10
The first memory cell is a high-density NOR type ROM memory cell using a two-layer gate electrode as shown in JP-A-63-131568. This relates to the configuration of the contact region between the bank selection line and the main bit line.

As shown in FIGS. 4 and 7, the mask ROM of FIG. 1 has a single-layer gate electrode, whereas the word lines WL1A, WL2A...
The gate electrodes used for B, BS2A,... Are the first gate electrodes 3a, 3c and the second gate electrodes 9b, 9 of the second layer.
The other configurations and operations are substantially the same as those of the mask RO shown in FIG.
Same as M.

With such a configuration, the memory cell area is reduced, and it is not necessary to take a space between gate wirings as compared with the single-layer gate structure of FIG. 1, so that the size of the bank selection transistors BT1A and BT4A is reduced. It can be bigger, and the ability can be even bigger. Further, since the gate electrodes can be arranged without gaps, the second-layer gate electrode 9
During processing of b and 9c, it is possible to use a configuration in which the second-layer gate oxide film 8 is not exposed without using the thin gate oxide film 8 as an etching stopper, so that the second-layer gate electrodes 9b and 9c are processed. (E.g., no high-selective etch is required). Although the contact peripheral region is exposed, since the contact peripheral region is a high concentration region, the oxide film here has almost three times the thickness of the gate oxide film, so that there is no problem.

Further, the mask ROM shown in FIGS.
, The bank selection line BS1B in which the opening is formed
.. Are composed of the first gate electrode 3a,
5 and 8 show examples in which the bank selection lines BS1B in which the openings are formed are constituted by the second gate electrodes 9a. 6 and 9 show an example in which bank selection lines BS1B... In which openings are formed are alternately formed by second gate electrodes 9a and bank selection lines BS4A.

The bank selection line in which the opening is formed is shown in FIG.
As shown in FIG. 5, if one of the first and second gate electrodes is used, the alignment margin of the contact portion can be further reduced, and the size of the mask ROM itself can be reduced. In such a configuration, the number of word lines becomes odd, and one word line becomes a dummy line. Further, if the bank selection line in which the opening is formed is composed of both the first layer and the second layer gate electrodes as shown in FIG. Need not be formed, and the area can be further reduced.

Embodiment 3 FIGS. 10 and 11 are a plan view and a circuit diagram, respectively, of a memory cell of a mask ROM as still another example of the semiconductor device of the present invention. The difference between the mask ROM of FIG. 1 and the memory cells of the mask ROM of FIG. 1 is that the mask ROM of FIG.
2 (SB1A and SB1B, SB5
A, SB5B) are extended and connected to each other, and a bank cell BT shared between the phase-connected sub-bit lines SB5A, SB5B and the auxiliary conductive region BB11.
1A is formed, whereas the mask ROM of FIG.
Is that the mutually adjacent sub-bit lines are not connected, are independent, do not share bank cells, and are formed independently. For example, in FIG. 10, the bank cells BS are respectively provided for the sub-bit lines SB3 and SB4.
O1 and BSE2 are connected.

Embodiment 4 FIG. 12 is a plan view of a bank select transistor in a memory cell of a mask ROM, which is still another example of the semiconductor device of the present invention. The bank selection transistor BT2A on the right side of the bank selection transistors of FIG. 12 is the same as the bank selection transistor BT2A of the first and second embodiments, and is substantially the same as the bank selection transistor BSO1 of the third embodiment. ~
The third bank selection transistor may be formed like the left bank selection transistor BT0A. In such a selection transistor BT0A, the capacity of the bank cell can be increased as the line width of the bank selection line BS2A is increased.

Embodiment 5: FIG. 13 is a plan view of a bank select transistor in a memory cell of a mask ROM, which is still another example of the semiconductor device of the present invention, and FIG.
14 is shown in FIG. This mask ROM is shown in FIG.
As shown in FIGS. 14 and 14, two bank select transistors BSO1 and BSO2 are formed in a part of the bank cell in parallel with the bank select line BO1. With such a configuration, the area of the auxiliary conductive region can be reduced, and the junction capacitance of the substrate diffusion portion connected to the bit line can be reduced. Therefore, the speed of the semiconductor device can be increased by reducing the bit line wiring capacitance. Can be planned.

Embodiment 6: A connection portion between a high-concentration diffusion layer and a select line of a semiconductor memory cell, which is still another example of the semiconductor device of the present invention, is shown. This memory cell is a plan view of FIG. 15A and a cross-sectional view taken along line EE 'in FIG.
As shown in FIG. 5B, the substrate 20 may be connected to the diffusion layer 21 of the opposite conductivity type, or the substrate 20 and the well 23 of the opposite conductivity type may be formed. 20 and the diffusion layer 22 of the same conductivity type.

Embodiment 7: FIG. 1 is a plan view of a memory cell of a mask ROM as still another example of the semiconductor device of the present invention.
6 is shown. This memory cell has separation bands 14 and 15 for inhibiting conduction of the memory cell for each predetermined column of the memory cell column sandwiched between adjacent sub-bit lines. This memory cell uses a two-layer gate electrode, and separation bands 14 and 15 are separation bands corresponding to the first gate electrodes 3a, 3b, 3c and the second gate electrodes 9a, 9c, respectively.

One bank area B sandwiched between the separation bands
Auxiliary conductive region BB11 on one end side of ANK1 is shared by bank region BANK2 and bank region BAK2.
A sub-bit line SB1A shared by NK1 and BANK2,
SB5A is a bank selection transistor BT1.
A, BT1B, and bank selection transistor B
It is connected to the sub-bit line SB3A via T2A.
Further, auxiliary conductive region BB21 arranged on the other end side of SB1A to SB5A is shared with bank region BANK0, and this auxiliary conductive region BB21 and sub-bit line SB2
Bank selection transistors BT3A and BT4A are formed between A and SB4A on the other end side, respectively.

As described above, by forming the separation band in the bank region, it is possible to prevent a sneak current generated in a memory cell that is not intended for reading at the time of reading, thereby preventing a malfunction.

Embodiment 8: A method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 17 and 18 are sectional views taken along line AA 'of FIG.

First, as shown in FIG. 17A, an oxide film 16 is formed on a semiconductor substrate 200a.
A resist pattern 17 is formed as an ion implantation mask of impurities having a conductivity type opposite to that of 00a. Then, using the resist pattern 17 as a mask, ions of an impurity of the opposite conductivity type are implanted to form an N ⁺ diffusion layer 2 serving as a sub-bit line and an auxiliary conductive region on the semiconductor substrate 200a. For example, in the case of an NMOS, arsenic ions (As ⁺ ) are implanted at an implantation amount of 10 ¹⁵ cm ^{−2 and} an implantation energy of 40 keV.

Next, as shown in FIG. 17B, a gate oxide film 12 having a thickness of about 50 to 300 ° is formed on the semiconductor substrate 200a, and the gate electrode 3 is formed on the gate oxide film 12.
Are arranged in parallel in the memory cell area. The gate electrode 3 is made of, for example, N ⁺ Po having a thickness of 2000 to 3000 mm.
A lySi film or a two-layer structure having a 1000-nm thick lower N ⁺ PolySi film and a 1000-mm thick upper tungsten silicide film is used. In addition, the gate electrode 3
An insulating film 18 used as a mask at the time of etching the gate electrode 3 is formed on the upper surface. This insulating film 1
Reference numeral 8 is also used as an interlayer insulating film with a later metal wiring. The gate electrode 3 is formed in a pattern having an opening in a contact formation region, as shown in FIG.

Further, as shown in FIG. 17C, a sidewall insulating film 19 is formed on the side wall of the gate electrode 3. This sidewall insulating film 19 can also be used as an interlayer insulating film with a later metal wiring, and can also be used for forming a self-aligned contact in a later step. Next, an interlayer insulating film 14 is formed on the entire surface of the obtained semiconductor substrate 200a. In the contact formation region, a recess is formed on the surface of the interlayer insulating film 14 due to the opening of the gate electrode 3.

Then, as shown in FIG. 17D, a resist pattern 29 having an opening larger than the actual contact hole diameter is formed, and anisotropic etching is performed to form a contact hole. Since the contact holes can be formed by cell alignment by the recesses formed in advance, it is not necessary to provide a large alignment margin, which is effective for reducing the memorial array.

Further, as shown in FIG. 17E, the first half process of the semiconductor device is completed through the formation process of the metal wiring 4 and the formation process of the protection film 17, and the assembly process of the second half process is performed. The semiconductor device is completed. Although omitted in the above description, Vth control implantation of a transistor, element isolation ion implantation, and mask RO
If it is M, a ROM data writing step and the like are appropriately performed. In the case of a CMOS structure, a well forming step and a reverse type transistor forming step may be added by a similar process.

FIGS. 18 (a) to 18 (e) correspond to FIGS.
17A to 17E are substantially different from FIGS. 17A to 17E only in that the step of forming the sidewall insulating film 19 is omitted.
Since it can be formed in the same manner as in the manufacturing process, description thereof will be omitted. In the manufacturing steps of FIGS. 18A to 18E, the reliability of the insulating property between the gate electrode 3 and the metal wiring 4 may be slightly inferior, but is very effective in simplifying the steps.

Embodiment 9: A method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 19 is a cross-sectional view of FIG.
It is B 'line sectional drawing.

First, an oxide film is formed on the semiconductor substrate 200a, a resist pattern is formed as an ion implantation mask for impurities of the opposite conductivity type to the semiconductor substrate 200a, and ions of impurities of the opposite conductivity type are implanted. An N ⁺ diffusion layer 2 serving as a sub-bit line and an auxiliary conductive region as shown in FIG. 19A is formed on 200a. For example, in the case of an NMOS, the ion implantation is performed by implanting arsenic ions (As ⁺ ) at a dose of 10 ¹⁵ cm ^{−2 and} an implantation energy of 40 keV. Further, a film thickness of 50 to 3 is formed on the semiconductor substrate 200a.
A first gate oxide film 12 of about 00 ° is formed, and a plurality of first gate electrodes 3 are arranged on the gate oxide film 12 in a memory cell region in parallel. As the gate electrode 3, for example, an N ⁺ PolySi film having a thickness of 2000 to 3000 nm or a lower N ⁺ PolySi film having a thickness of 1000
A two-layer structure having a thick upper tungsten silicide film is used. An insulating film 18 used as a mask when etching the first gate electrode 3 is formed on the first gate electrode 3. This film is later
It is also used as an interlayer insulating film between the gate electrodes 9. Also,
As shown in FIG. 4, for the first gate electrode 3, a pattern having an opening in a contact formation region is used. Note that a sidewall insulating film 19 is formed on the side wall of the first gate electrode 3. This film is also used as an interlayer insulating film between the second gate electrodes 9 later, and is also used for forming a self-aligned contact in a later step.

Further, as shown in FIG.
A second gate oxide film 28 is formed in a region serving as a channel portion of a transistor using the gate electrode 9, and the second gate electrode 9 is formed on insulating films 18 and 19 between the gate electrodes and the second gate oxide film 28. Is formed using the resist pattern as a mask, and is formed in parallel between the first gate electrodes 3 in the memory cell region. Further, similarly to the transistor using the first gate electrode, a transistor using the second gate electrode may be formed in a peripheral circuit portion. As the gate electrode 9, for example, an N ⁺ PolySi film having a thickness of 2000 to 3000 nm or a lower N ⁺ Pol film having a thickness of 1000
A two-layer structure composed of a ySi film and an upper tungsten silicide film having a thickness of 1000 ° is used. Also, the second
An insulating film 31 used as a mask when etching the second gate electrode 9 is formed on the gate electrode 9. This film is also used as an interlayer insulating film between later metal wirings.

When used as a mask ROM, the first gate electrode 5 should be
It is desired to simultaneously implant the transistor on the side of the second gate electrode 11 and the transistor on the side of the second gate electrode 11. It is desirable to select and set the film thickness. As a method of forming the second gate electrode 9, in addition to the usual photolithography and dry etching methods, a method such as buried etch back is used. The electrodes 9 can be prevented from overlapping, and the R
At the time of OM data write ion implantation, it is possible to prevent a defect that implantation is insufficient at an overlapping portion.

Next, as shown in FIG. 19C, an interlayer insulating film 34 is formed on the entire surface of the obtained semiconductor substrate 200a. In the contact formation region, a recess is formed on the surface of the interlayer insulating film 34 due to the opening of the gate electrode 3. Then, as shown in FIG. 19D, a resist pattern 29 having an opening larger than the actual contact hole diameter is formed, and anisotropic etching is performed to form a contact hole. Since the contact holes can be formed in a self-aligned manner by the recesses formed in advance, it is not necessary to provide a large alignment margin, which is effective for reducing the memory cell array.

Further, as shown in FIG. 19E, the first half of the semiconductor device is completed through the steps of forming the metal wiring 4, forming the protective film 17, and the like, and further performing the second half of the assembly step. Then, the semiconductor device is completed. Although omitted in the above description, the transistor V
The th control implantation, the blocking separation ion implantation, and, in the case of a mask ROM, a ROM data writing step and the like are appropriately performed. In the case of a CMOS structure, a well forming step and a reverse type transistor forming step may be added by a similar process.

Embodiment 10 A method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG. 20 shows D- in FIG.
It is D 'line sectional drawing.

First, as shown in FIG. 20A, similarly to the ninth embodiment, the semiconductor substrate 20 on which the diffusion layer 2 is formed is formed.
First gate electrode 3 having insulating film 18 and sidewall insulating film 19 is formed on Oa. Here, for the first gate electrode 3, a pattern having an opening in a contact formation region every other bank region is used. Next, as shown in FIG. 20B, similarly to Embodiment 9, after forming the second gate electrode 9 having the insulating film 31, the sidewall insulating film 32 is formed on the second gate electrode 9. This insulating film 31 is used as an interlayer insulating film between metal wirings to be described later, and is also used for forming a self-aligned contact in a later step. Here, the second gate electrode 9 has a contact 5 every other bank region different from the first gate electrode 3.
A pattern having an opening in the formation region is used.
That is, a pattern having an opening in the contact formation region is formed alternately for each bank by the first gate electrode 3 and the second gate electrode 9.

Next, as shown in FIG. 20C, an interlayer insulating film 34 is formed on the entire surface of the obtained semiconductor substrate 200a. A recess is formed in the contact formation region by the opening of the first gate electrode 3 or the opening of the second gate electrode 9, respectively. Then, as shown in FIG. 20D, a resist pattern 29 having an opening larger than the actual contact hole diameter is formed, and anisotropic etching is performed to form a contact hole. Since the contact holes can be formed in a self-aligned manner by the recesses formed in advance, it is not necessary to provide a large alignment margin, which is effective for reducing the memory cell array.

Similarly, as shown in FIG.
Through the steps of forming the metal wiring 4 and forming the protective film 17, the first half of the process of the semiconductor device is completed, and the assembly process of the second half is further performed to complete the semiconductor device. Although omitted in the above description, Vth control implantation of the transistor, element isolation ion implantation, and a ROM data writing step for a mask ROM are appropriately performed in the middle of the process. In the case of a CMOS structure, a well forming step,
A reverse transistor formation step may be added by a similar process.

[0073]

According to the present invention, since the contact portion can be formed through the opening formed in the gate electrode, it is not necessary to form the gate electrode and the contact portion in separate regions, and the contact portion can be formed. Occupied area can be minimized. In other words, a circuit capable of maximizing the width of the gate electrode adjacent to the contact portion, that is, the effective gate width can be realized.

In a semiconductor device of a hierarchical bit line type and having a two-layer gate electrode structure, the gap between the gate electrodes can be minimized, and the gate width of each select transistor can be made as large as possible. , Driving ability can be maximized. Further, in the case of the hierarchical bit line method and the above-described contact extraction structure, the occupation area of the contact portion is minimized, the gate width of the selection transistor is increased, and the driving capability is maximized, and the bit capacity is increased. Since the line current can be maximized, the speed of the semiconductor device can be increased.

In a two-layer gate electrode structure, usually, even numbers of word lines and selection lines of a memory cell array are used, so that a selection line having an opening is formed at one end at both ends of the memory cell array. In the case where the gate electrode is formed by the layer and the two-layer gate electrode, it is not necessary to form an unnecessary dummy gate, and the integration of the semiconductor device can be further increased.
In this case, applying the self-aligned contact method is effective in reducing the memory cell array, and the chip size can be reduced, so that a low-cost device can be realized.

Further, when the semiconductor device of the present invention is applied to a storage device employing a hierarchical bit line system, the drive capability of the selection transistor can be maximized, and the speed of the semiconductor storage device can be increased. Can be. When the effective gate widths of the select transistors are the same, the bit line currents can be made equal regardless of the selected bank select transistor, thereby increasing the read time margin.

Further, when a separation band is provided for each predetermined column of the memory cell column, even if a plurality of memory cells continuously arranged along one word line are turned on, the selected sub-bit line It is possible to prevent a leak current generated between the two, and it is possible to improve a read margin. According to the manufacturing method of the present invention, the opening of the gate electrode is formed by utilizing the self-aligned contact formation.
There is no need to provide an alignment margin, and the memory cell array can be reduced accordingly, and the connection of the contact portion can be reliably performed, so that a highly reliable semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing an embodiment of a semiconductor device of the present invention.

FIG. 2 is a circuit diagram of the semiconductor device of FIG. 1;

FIG. 3 is a schematic sectional view taken along line A-A 'of FIG.

FIG. 4 is a schematic plan view showing another embodiment of the semiconductor device of the present invention.

FIG. 5 is a schematic plan view showing still another embodiment of the semiconductor device of the present invention.

FIG. 6 is a schematic plan view showing still another embodiment of the semiconductor device of the present invention.

FIG. 7 is a sectional view taken along line B-B 'of FIG.

8 is a sectional view taken along line C-C 'of FIG.

FIG. 9 is a sectional view taken along line D-D ′ of FIG. 6;

FIG. 10 is a schematic plan view showing still another embodiment of the semiconductor device of the present invention.

FIG. 11 is a circuit diagram of the semiconductor device of FIG. 10;

FIG. 12 is a schematic plan view of a main part showing still another embodiment of the semiconductor device of the present invention.

FIG. 13 is a schematic plan view of a main part showing still another embodiment of the semiconductor device of the present invention.

FIG. 14 is a circuit diagram of the semiconductor device of FIG. 13;

FIG. 15 is a schematic plan view of a main part and a schematic cross-sectional view of a main part showing still another embodiment of the semiconductor device of the present invention.

FIG. 16 is a schematic plan view showing still another embodiment of the semiconductor device of the present invention.

FIG. 17 is a schematic sectional view taken along the line AA 'for illustrating the manufacturing process of the semiconductor device shown in FIG. 1;

FIG. 18 is a schematic sectional view taken along the line AA 'for explaining another manufacturing step of the semiconductor device shown in FIG. 1;

19 is a schematic sectional view taken along the line BB 'for explaining the manufacturing process of the semiconductor device shown in FIG. 4;

20 is a schematic sectional view taken along the line DD 'for illustrating the manufacturing process of the semiconductor device shown in FIG. 6;

FIG. 21 is a plan view of a memory cell of a conventional semiconductor device.

FIG. 22 is an equivalent circuit diagram of FIG. 21;

[Explanation of symbols]

101, 200 Hierarchical bit line type ROM 20, 200a Semiconductor substrate 2, 21, 22 Auxiliary conductive region 3a First select line 3b First select line 3, 3c First gate electrode 4 Metal wiring 8 Second gate insulating film 9a Second Select line 9b second select line 9, 9c second gate electrode 12 first gate insulating film 14, 17, 34 interlayer insulating film 15, 29 resist 16 oxide film 18, 31 insulating film 19, 32 sidewall insulating film 23 well 24 Separation band for first gate electrode 25 Separation band for second gate electrode BANK1 Bank region SB1A, SB1B, SB1 Sub-bit line WL1A, WL1B, WL1 Word line M1, M, M1J Memory cell BB11, BB22 Auxiliary conductive region BT1A, BT1B, BSO1, BSE1 Bank selection transistor (bank cell) BS 1A, BS1B, BO1, BE1 Bank select line CC11, CC22 Contact hole MB1 Main bit line MG1 Main ground line FD, FD1 Element isolation section

Claims (19)

[Claims] An impurity diffusion layer formed on a surface of a semiconductor substrate, a gate electrode formed on a semiconductor substrate including the impurity diffusion layer via an insulating film, and a conductive layer formed above the gate electrode A semiconductor device comprising: a conductive layer connected to an impurity diffusion layer through an opening formed in a gate electrode present on the impurity diffusion layer; 2. A hierarchical bit line system having a memory cell array arranged in a matrix and a bit line including a main bit line and a plurality of sub-bit lines connected to the main bit line via a selection transistor. Wherein the memory cells and the select transistors constituting the memory cell array are configured in a two-layer gate electrode structure in which first gate electrodes and second gate electrodes are alternately arranged in parallel. Semiconductor device. 3. A hierarchical bit line system having a memory cell array arranged in a matrix and a bit line including a main bit line and a plurality of sub-bit lines connected to the main bit line via selection transistors, respectively. The semiconductor device according to claim 1, wherein the main bit line is connected to one terminal of the selection transistor through an opening formed in the selection line constituting the selection transistor. 4. The semiconductor according to claim 3, wherein the memory cells and the select transistors constituting the memory cell array are formed in a two-layer gate electrode structure in which first gate electrodes and second gate electrodes are alternately arranged. apparatus. 5. The memory cell according to claim 4, wherein the selection line of the selection transistor having the opening is formed by the first gate electrode at one end of the memory cell and by the second gate electrode at the other end. Semiconductor device. 6. A memory cell array having a plurality of word lines arranged in parallel in a row direction and arranged in a matrix, and an arbitrary memory cell column arranged at both ends of the memory cell array. And a plurality of sub-bit lines formed by a plurality of diffusion layers parallel to each other in the column direction and connected to the memory cell array, respectively, and formed by a metal layer for every two columns of the memory cell array.
A main bit line extending in the column direction is provided, and a sub bit line adjacent in the row direction is alternately connected to one terminal of the selection transistor at one end or the other end, and is adjacent to the other. The semiconductor device according to claim 1, wherein the other terminals of the selection transistors connected to the sub-bit lines are connected to different main bit lines through openings formed in the selection lines forming the selection transistors. 7. The semiconductor device according to claim 6, wherein the selection transistor connected to the sub-bit line is two selection transistors connected in parallel. 8. A two-layer gate electrode structure in which a word line forming a memory cell array and a selection line forming a selection transistor have a first gate electrode and a second gate electrode alternately arranged in parallel. 8. The semiconductor device according to any one of 7. 9. The memory cell according to claim 8, wherein the selection line of the selection transistor having the opening is formed by a first gate electrode at one end of the memory cell and by a second gate electrode at the other end. Semiconductor device. 10. A memory cell array having a plurality of word lines arranged in parallel in a row direction and arranged in a matrix, and an arbitrary memory cell column arranged at both ends of the memory cell array. And a plurality of sub-bit lines formed by a plurality of diffusion layers parallel to each other in the column direction and connected to the memory cell array, respectively, and formed by a metal layer for every two columns of the memory cell array.
A main bit line extending in the column direction, and sub-bit lines adjacent in the row direction are alternately connected to one terminal of a selection transistor at one end or the other end, and The first sub-bit line of the four sub-bit lines adjacent in the direction is arranged on one end side of the memory cell array so as to straddle the bank adjacent in the column direction, and the adjacent bank is the first sub-bit line. The bit line is connected to one terminal of the first transistor to share the first selection transistor, and the third sub-bit line of the four sub-bit lines adjacent in the row direction is connected to one end of the memory cell array. , The second and fourth sub-bit lines of the four sub-bit lines adjacent in the row direction are connected to the other end of the memory cell array at the third and fourth terminals, respectively. 4th choice tran The other terminal of the first and second select transistors is connected to the same main bit line through an opening formed in a select line constituting the first select transistor. A semiconductor device, comprising: 11. The word line forming the memory cell array and the selection line forming the selection transistor have a two-layer gate electrode structure in which first gate electrodes and second gate electrodes are alternately arranged in parallel. 13. The semiconductor device according to claim 1. 12. The memory cell according to claim 10, wherein the selection line of the selection transistor having the opening is formed by a first gate electrode at one end of the memory cell and by a second gate electrode at the other end. The semiconductor device according to any one of the above. 13. The semiconductor device according to claim 6, wherein a selection line width of the selection transistor is made equal, and a bit line current for each sub-bit line is made equal. 14. The semiconductor device according to claim 6, further comprising a separation band arranged for each predetermined column of the memory cell array in parallel with the sub-bit line and for preventing conduction of the memory cell. 15. A source / drain, a sub-bit line, and an auxiliary conductive region forming a memory cell array are formed on a semiconductor substrate, and the source / drain forming a memory cell array are formed on the semiconductor substrate via a gate insulating film. Forming a plurality of parallel word lines and selection lines, forming an opening in the selection line above a part of the auxiliary conductive region, forming a sidewall insulating film in the word lines and the selection lines, Depositing an interlayer insulating film over the entire surface of the semiconductor substrate, forming a resist pattern for forming a contact with the opening of the selection line, and making a self-aligned contact opening smaller than the resist pattern using the opening; A method for manufacturing a semiconductor device, comprising: forming a portion. 16. A source / drain, a sub-bit line, and an auxiliary conductive region forming a memory cell array are formed on a semiconductor substrate, and the memory cell array is formed on the semiconductor substrate via a first gate insulating film. Forming a plurality of first word lines and a first selection line which are parallel to each other, forming an opening in the first selection line above a part of the auxiliary conductive region, and forming the first word line and the first selection line; Forming a side wall insulating film on the line, and forming a second gate insulating film on the obtained semiconductor substrate,
Forming a plurality of second word lines and second selection lines parallel to each other forming a memory cell array; forming an opening in the second selection line above a part of the auxiliary conductive region; Forming a sidewall insulating film in the opening; depositing an interlayer insulating film on the entire surface of the obtained semiconductor substrate; forming a resist pattern for forming a contact with the opening of the first and second selection lines; Forming a contact opening smaller than the resist pattern by self-alignment using the openings of the first and second selection lines. 17. A source / drain, a sub-bit line, and an auxiliary conductive region forming a memory cell array are formed on a semiconductor substrate, and the memory cell array is formed on the semiconductor substrate via a first gate insulating film. Forming a plurality of first word lines and a first selection line which are parallel to each other, forming an opening in the first selection line above a part of the auxiliary conductive region, and forming the first word line and the first selection line; Forming a side wall insulating film on the line, and forming a second gate insulating film on the obtained semiconductor substrate,
A plurality of parallel second word lines and second selection lines forming a memory cell array are formed, an interlayer insulating film is deposited on the entire surface of the obtained semiconductor substrate, and a contact is made with the opening of the first selection line. A method of manufacturing a semiconductor device, comprising: forming a resist pattern for forming; and forming a contact opening smaller than the resist pattern in a self-aligned manner by using an opening of the first selection line. 18. A source / drain forming a memory cell array, a sub-bit line, and an auxiliary conductive region are formed on a semiconductor substrate. The memory cell array is formed on the semiconductor substrate via a first gate insulating film. Forming a plurality of first word lines and a first selection line parallel to each other, forming a sidewall insulating film on the first word line and the first selection line, forming a second gate on the obtained semiconductor substrate; Through the insulating film,
Forming a plurality of second word lines and second selection lines parallel to each other forming a memory cell array; forming an opening in the second selection line above a part of the auxiliary conductive region; Forming a sidewall insulating film in the opening; depositing an interlayer insulating film on the entire surface of the obtained semiconductor substrate; forming a resist pattern for forming a contact with the opening of the second selection line; A method of manufacturing a semiconductor device, comprising forming a contact opening smaller than the resist pattern in a self-aligned manner by using an opening of a two-selection line. 19. The method of manufacturing a semiconductor device according to claim 15, further comprising a step of forming an insulating film on the first word line and the first selection line.