JPH10241355A - Synchronous semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely perform initial setting of all inside circuits at a normal voltage level after a power source is inputted by generating an internal clock signal at the time of activating a power-on reset period regulating signal and stopping the generation of the internal clock under the inactive state of the inside circuits and also at the time when a reset period is completed. SOLUTION: When the power source is inputted, a power-on reset signal/POR is activated by a power source input detecting circuit 102, and the reset period regulating signal RAR as an output of a latch circuit 104 is activated during a period until a prescribed operation mode specifying signal ϕmode is given. An internal clock intCLK is passed by a sequential clock circuit 130 in receipt of a clock enable signal CLKEN during an active period of the reset period regulating signal RAR, and a signal ϕCLK is supplied to sequential control circuit. Thus, at the time of initializing operation, circuits to be operated in synchronization with the internal clock signal can surely be operated, and at least circuits to receive this internal clock can be initialized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device which inputs and outputs data in synchronization with a clock signal. Synchronous DRAM (Dynamic Random Access
Memory: SDRAM). More specifically, the present invention relates to a configuration for initializing a synchronous DRAM when power is turned on.

[0002]

2. Description of the Related Art In order to eliminate the difference in operation speed between a microprocessor and a standard DRAM and to perform high-speed data transfer between the microprocessor and a DRAM as a main memory, for example, in synchronization with a clock signal which is a system clock. Synchronous DRAMs that take in external control signals, address signals and write data, and output data have been widely used. By performing data input / output in synchronization with the clock signal, data can be transferred between the microprocessor and the synchronous DRAM as main memory at an operating speed that is effectively the same as the operating frequency of the microprocessor. High-speed data transfer becomes possible. Further, since the external signal is taken in synchronization with the clock signal, there is no need to consider a margin for the skew of the external control signal and the address signal.
Since the internal operation start timing can be advanced, a memory that operates at high speed can be realized.

FIG. 26 shows a conventional synchronous DRAM.
FIG. 1 is a diagram schematically showing an entire configuration of an (SDRAM).
Referring to FIG. 26, a conventional synchronous DRAM has a memory cell array 1 having a plurality of memory cells arranged in a matrix and, when activated, decodes a given internal row address signal to specify the address of memory cell array 1. Row selection circuit 2 for driving a selected row to a selected state;
A column selecting circuit 3 for selecting an addressed column of memory cell array 1 according to a given internal column address signal, and writing and writing of data to a memory cell column selected by column selecting circuit 3 when activated. Write / read circuit 4 for reading data from the selected column, and input / output circuit 5 for inputting / outputting data between write / read circuit 4 and the outside of the device when activated.

A memory cell included in the memory cell array 1 is a one-transistor / one-capacitor type dynamic memory cell. Row select circuit 2 includes a row decode circuit for decoding a given internal row address signal, and a word line drive circuit for driving a corresponding row of memory cell array 1 to a selected state according to an output signal of the row decode circuit. The word line is connected to the memory cell array 1
, And the memory cells of the corresponding row are connected to the respective rows.

Column selection circuit 3 decodes a given internal column address signal and generates a column selection signal in accordance with the result of the decoding. Including an IO gate circuit connected to the data line.

Write / read circuit 4 includes a write drive circuit provided for each internal data line for writing data and a preamplifier for reading data. Input / output circuit 5 includes an input buffer for generating internal write data from external data and an output buffer for generating external read data from internal read data.

The synchronous DRAM further includes a refresh address counter 6 for generating a refresh address designating a memory cell to be refreshed during a refresh operation, and an externally applied address signal AD.
An address input buffer 7 for generating an internal row address signal and an internal column address signal, and one of a refresh address signal from a refresh address counter 6 and an internal row address signal from the address input buffer 7 to select a row select circuit 2 And a multiplexer 8 for providing the data to The internal column address signal from address input buffer 7 is not applied to multiplexer 8,
Directly applied to column selection circuit 3.

When a refresh operation is designated,
The multiplexer 8 selects a refresh address signal from the refresh address counter 6, and in the normal operation mode, the multiplexer 8 selects the address input buffer 7
Select the internal row address signal.

The synchronous DRAM further includes a clock input buffer 10 for buffering an external clock signal extCLK to generate an internal clock signal intCLK, and a control signal externally applied in synchronization with the rising of the internal clock signal intCLK. That is, a control input buffer 12 for taking in a row address strobe / RAS, a column address strobe signal / CAS and a write enable signal / WE, and the control input buffer 1
The command decoder 14 determines the state of the internal control signal supplied from the memory cell array 2 and determines the designated operation mode. A control signal required for data writing / reading is generated in synchronization with internal clock signal intCLK in accordance with a row-related control circuit 16 for controlling an operation to be performed and an access instruction signal instructing data writing / reading from command decoder 14. And a refresh control circuit 20 that generates a control signal necessary for refreshing in response to a refresh operation instruction signal from the command decoder 14. Column-related control circuit 18 will be described in detail later, but only when necessary for its operation, that is, only during the period from when the array activation is performed to when the required data is written / read and completed. Enable the internal clock signal intCLK,
It operates according to the valid internal clock signal intCLK.

A row-related control circuit 16 controls the operation of the row selection circuit 2, activation / inactivation of a sense amplifier (not shown), and activation / inactivation of a bit line equalize / precharge circuit. Column-related control circuit 18 controls operations of column selection circuit 3, write / read circuit, and input / output circuit 5.

During the refresh operation, the refresh control circuit 20 activates the row control circuit 16 and controls the multiplexer 8 to select the refresh address signal from the refresh address counter 6. The refresh address of the refresh address counter 6 is updated under the control of the refresh control circuit 20. Address input buffer 7 takes in an address signal applied in synchronization with the rising of internal clock signal intCLK, and generates an internal row address signal and an internal column address signal in accordance with an internal operation mode instruction signal output from command decoder 14.

[0012] The synchronous SDRAM further includes a mode register 22 for storing burst length data, CAS latency data, and the like. Next, the operation of the conventional SDRAM shown in FIG. 26 will be described with reference to a timing chart shown in FIG.

In clock cycle 0 of external clock signal extCLK, external clock signal extCL
At the rising edge of K, row address strobe signal / RAS is set to L level, and column address strobe signal / CAS and write enable signal / WE are set.
Is set to the H level. This combination of control signal states is called an active command.
Activation of the memory cell array, that is, start of a selection operation of two rows of the memory cell array 1 is instructed. The address input buffer 7 takes in the address AD when the active command is given as a row address signal (X), and the row selection circuit 2
The corresponding row of the memory cell array 1 is driven to a selected state.
By this active command, in the memory cell array 1, detection of memory cell data connected to the selected row,
Amplification and latching are performed.

In clock cycle 2, at the rising edge of external clock signal extCLK, row address strobe signal / RAS and write enable signal / WE are both set to H level, and column address strobe signal / CAS is set to L level. This combination of control signal states is called a read command, and data reading is instructed. When this read command is applied, the address signal AD at that time is taken in by the address input buffer 7 as a column address signal (Y),
Under the control of the column related control circuit 18, the column selecting circuit 3 performs a column selecting operation. The data of the memory cell selected by the column selection circuit 3 is read by the write / read circuit 4 and output via the input / output circuit 5. Data transfer by write / read circuit 4 and input / output circuit 5 requires a certain time. At the rising edge of the clock signal extCLK in the clock cycle 4 two clock cycles after the application of the read command, the first data Q
“0” is in the determined state. According to this read command, 4
One data is settled at the rising edge of each external clock signal extCLK in clock cycles 5, 6, and 7. The period required from the application of this read command to the output of valid data to the outside is defined as CAS.
Called latency. In FIG. 27, therefore, C
The AS latency is 2. The number of data read continuously after one read command is applied is called a burst length. In FIG. 27, the burst length is 4
Is shown as an example.

In clock cycle 8, at the rising edge of external clock signal extCLK, row address strobe signal / RAS is set to H level, and both column address strobe signal / CAS and write enable / WE are set to L level. This combination of states of the external control signal is called a write command, and data writing is instructed. At the time of data writing, the operation of column selecting circuit 3 is the same as that of data reading. However,
Input / output circuit 5 and write / read circuit 4 take in external write data D0 from clock cycle 8 to which the write command is applied, and sequentially receive data D1, D applied in clock cycles 9, 10 and 11, respectively.
Capture 2 and D3. These captured D0-D3
Are written into the memory cells selected by the column selection circuit 3 according to a predetermined sequence.

In clock cycle 12, at the rising edge of external clock signal extCLK, row address strobe signal / RAS and write enable signal / WE are both set to L level, and column address strobe signal / CAS is set to H level. This combination of states of the external control signal is called a precharge command, and the memory cell array 1 in the selected state is driven to the non-selected state. This precharge command drives row-related control circuit 6 to an inactive state, and accordingly drives row select circuit 2 to a non-selected state. Even when a precharge command is applied, column related control circuit 18 maintains an active state until a predetermined burst length and a latency period elapse. Therefore, when reading burst length data,
Even if a precharge command is applied, data is reliably read. For example, even when a precharge command is applied in clock cycle 6, column related control circuit 18 maintains an active state, and data read and selected when memory cell array 1 is shifted to a non-selected state is written / read. The data is sequentially transferred and output by the readout circuit 4 and the input / output circuit 5.

In clock cycle 15, at the rising edge of external clock signal extCLK, row address strobe signal / RAS and column address strobe signal / CAS are set to L level, and write enable signal / WE is set to H level. This condition is a standard DR
This corresponds to the “CBR (CAS before RAS)” condition in AM. This combination of control signal states is called an auto-refresh command. The refresh control circuit 20 is activated internally, and the refresh row in the memory cell array 1 is refreshed according to the refresh address generated by the refresh address counter 6.

FIG. 28 shows the command decoder 14, row control circuit 16 and refresh control circuit 2 shown in FIG.
FIG. 3 is a block diagram more specifically showing the configuration of a zero. FIG.
, The command decoder 14 includes a row address strobe signal / RAS and a column address strobe signal / RAS.
In accordance with CAS and write enable signal / WE, array activating signal φac and precharge instructing signal φp
r, and a command decode circuit 14b that outputs an auto-refresh operation instruction signal φar in accordance with external control signals / RAS, / CAS and / WE. These command decoder circuits 14a and 14b are connected to an internal clock signal i (not shown).
external control signal / R at the rising edge of ntCLK
The states of AS, / CAS and / WE are determined, and an array activation signal φac, a precharge instruction signal φpr, and an auto-refresh operation instruction signal φar are output according to the determination result. Array activation instruction signal φac instructs start of a memory cell row selection operation. Precharge instructing signal φpr instructs return of the array to a precharged state. The auto refresh operation instruction signal φar is
Instruct auto refresh. These signals φac,
φpr and φar are one-shot pulse signals.

Row-related control circuit 16 receives an array activation signal φ.
set in response to activation of ac and reset in response to activation of precharge instruction signal φpr /
A reset flip-flop 16a and an OR circuit 16 receiving an activation signal ACT from the flip-flop 16a and a refresh activation signal RFACT described later.
b, and a row-related drive circuit 16c for sequentially driving a circuit related to row selection (row-related circuit) to a selected state in a predetermined sequence in accordance with an array activation signal ACTR output from the OR circuit 16b. Row-related drive circuit 16c selects a word line in a memory cell array, activates a sense amplifier, deactivates precharge / equalize bit lines, and deactivates / activates them.

Refresh control circuit 20 sets / resets flip-flop 20a which is set in response to activation of auto-refresh operation instruction signal φar and outputs refresh activation signal RFACT, and refresh activation signal RACT for a predetermined time. Set with delay /
A delay circuit 20b for applying a reset input to a reset flip-flop 20a;
A refresh address control circuit 20c for controlling the operation of the refresh address counter and the multiplexer for switching the refresh address when T is activated is included. With the delay time of delay circuit 20b, a word line is selected in a memory cell array, and then, by activation of a sense amplifier, detection, amplification, latching and rewriting of memory cell data connected to the selected word line are performed. Is the time needed by Next, the operation of the circuit shown in FIG. 28 will be described with reference to the timing chart shown in FIG.

In clock cycle 0 of external clock signal extCLK, an active command is applied. In accordance with this active command, array activation instruction signal φac from command decode circuit 14a rises to the H level for a predetermined period, and set / reset flip-flop 16a is set. Thereby, the activation signal A
CT rises to the H level, and array activation signal ACTR from OR circuit 16b rises to the H level. According to activation of array activation signal ACTR, row-related driving circuit 16c sequentially drives row-related circuits such as a row selecting circuit to a selected state in a predetermined sequence. At this time, the bit line equalize / precharge circuit is inactivated again. While the array activation signal ACTR is in the active state of the H level, the memory cell array is maintained in the selected state.

In clock cycle 4 of external clock signal extCLK, when a precharge command is applied, precharge instructing signal φpr from command decode circuit 14a rises to H level for a predetermined time. In response to the rise of precharge instruction signal φpr, set / reset flip-flop 16a is reset,
Activation signal ACT is driven to an inactive state of L level,
In response, array activation signal ACTR is driven to an inactive state. Thereby, row-related driving circuit 16c sequentially drives the active row-related circuits to the inactive state in a predetermined sequence, and then activates the bit line equalize / precharge circuit. As a result, the memory cell array returns to the precharge state.

In clock cycle 7 of external clock signal extCLK, when an auto-refresh command is applied, auto-refresh operation instructing signal φar rises to H level for a predetermined period, set / reset flip-flop 20a is set, and refresh activation signal RFACT is activated. Rises to the H level. In response, array activation signal ACTR rises to the H level, and row-related drive circuit 16c sequentially drives the row-related circuits to the selected state in a predetermined sequence. In accordance with activation of refresh activation signal RFACT, refresh address control circuit 20c
Causes the multiplexer to select the refresh address from the refresh address counter.

In the memory cell array, row selection is performed according to a refresh address from a refresh address counter, and memory cell data is refreshed.

When the delay time of delay circuit 20b elapses after rising of refresh activation signal RFACT, set / reset flip-flop 20a is reset, refresh activation signal RFACT is deactivated, and row driving circuit is activated. 16c returns the memory cell array to the precharged state. The refresh address control circuit 20c updates the count value of the refresh address counter. The delay time of the delay circuit 20b determines the activation period of the refresh activation signal RFACT. Therefore, by applying an auto-refresh command from the outside, a refresh address is generated internally to refresh the memory cell data, and after completion of the auto-refresh operation, the memory cell array returns to the precharge state.

FIG. 30 shows the column related control circuit 18 shown in FIG.
FIG. 2 is a block diagram schematically showing the configuration of FIG. In FIG. 30, read instructing signal φr is applied to column related control circuit 18.
A command decode circuit 16c that outputs read and write instruction signal φwrite is also shown. This command decode circuit 16c is a command decoder 1 shown in FIG.
6 and external control signals / RAS, / C
Read operation instructing signal φrea according to a combination of states at the rising edge of clock signals AS and / WE.
d and write operation instruction signal φwrite are output in the form of a one-shot pulse.

The column related control circuit 18 counts a long period of a burst in accordance with activation of the read operation instruction signal φread, and outputs a signal which becomes active during the burst period. A shifter 18b for shifting an output signal for a period defined by CAS latency, and a column selecting circuit 3 shown in FIG. 26 according to output signals of burst length defining circuit 18a and shifter 18b.
Read control circuit 18c for controlling the operation of a read circuit included in write / read circuit 4, and output control for controlling the operation of an output circuit included in input / output circuit 5 shown in FIG. 26 according to an output signal from shifter 18b. And a circuit 18d.

A burst length defining circuit 18a is provided in response to activation of a read operation instruction signal φread to provide a burst length counter which counts a period set by the burst length and provides an output signal to the burst length counter.
And a set / reset flip-flop reset according to the count-up signal of the burst length counter. Both the burst length counter and shifter 18b operate in synchronization with an internal clock signal (not shown). The read control circuit 18c and the output control circuit 18d also output necessary control signals in synchronization with a clock signal (not shown) (with the rising edge of the clock signal as a trigger).

Column related control circuit 18 is further activated in response to activation of write operation instructing signal φwrite, and a burst length defining circuit 18e for holding its output signal in an active state for a long period of a burst at the time of writing. And burst length defining circuit 1
A shifter 18f for shifting the output signal of 8e for a predetermined period;
When the output signal of burst length defining circuit 18e is activated
26. An input control circuit 18g for controlling the operation of an input circuit included in input / output circuit 5 shown in FIG.
And a write control circuit 18h for controlling the operation of the column selection circuit 3.

Burst length defining circuit 18e, like burst length defining circuit 18a, includes a burst length counter and a set / reset flip-flop. These burst length defining circuit 18e, shifter 18f, input control circuit 18
g and the write control circuit 18h also generate necessary internal control signals in synchronization with a clock signal (not shown).
Next, the operation of column related control circuit 18 shown in FIG.
1 will be described with reference to the timing chart shown in FIG. FIG. 31 shows an activation period of each control circuit.

When a read command is applied in clock cycle 0 of external clock signal extCLK, read operation instructing signal φre is supplied from command decode circuit 16c.
ad is output in the form of a one-shot pulse. In response to activation of read operation instructing signal φread, burst length defining circuit 18a is activated, and outputs a signal which is active for a period defined by the burst length. Read control circuit 1
8c activates a column selection circuit according to activation of read operation instruction signal φread, and performs a column selection operation. The data of the selected memory cell is written /
It is transferred via the read circuit. The timing at which the output circuit is activated is determined by data called CAS latency. The CAS latency data is stored in the mode register. FIG. 31 shows the operation when the CAS latency is 2.

When the CAS latency is 2, output control circuit 18d is activated from clock cycle 1. That is, shifter 18b performs a (CAS latency-1) clock cycle shift operation to transmit the output signal of burst length defining circuit 18a. Under the control of the output control circuit 18d, the clock cycles 2, 3,
Data Q0, Q1, Q2, and Q3 are settled at the rising edge of each of clock signals extCLK of 4 and 5, and are sampled by an external device.
Here, a case where the burst length is 4 in FIG. 31 is shown as the burst length. When the reading of the data having the burst length is completed, the output control circuit 18d is deactivated. The transition of the read control circuit 18c to the inactive state is earlier than that of the output control circuit 18d, and the transition timing to the inactive state is determined by the CAS latency.
The circuit related to the read operation is kept active for a period given by the sum of the burst length and the CAS latency.

Next, in clock cycle 6, when a write command is applied, command decode circuit 16
Write operation instruction signal φwrite from c is output in the form of a one-shot pulse. This write operation instruction signal φw
burst length defining circuit 18e in response to activation of write
Is activated, and the input control circuit 18e is activated accordingly. By the activation of input control circuit 18e, an input circuit included in input / output circuit 5 shown in FIG. 26 is activated, and external write data is taken in in synchronization with a clock signal.
At the time of this writing, the case where the burst length is 4 is shown, and D0, D1, D2 and D3 brought into the definite state are taken in clock cycles 6, 7, 8 and 9, respectively. The input control circuit 18g is activated for a long period of the burst determined by the burst length defining circuit 18e. The timing at which the write control circuit 18h is activated differs depending on the transfer sequence of the fetched data. However, the write control circuit 1
8h shifts to the inactive state after a period defined by the burst length and the latency has elapsed since the write command was given. Since data transfer from the input circuit to the selected memory cell is required also at the time of data writing, a period called latency is required similarly to data reading.

FIG. 32 schematically shows a structure of a portion for generating an internal clock signal applied to the column related control circuit. In FIG. 32, a column related control clock generating unit is a set / reset flip-flop 1 shown in FIG.
OR circuit 3 receiving activation signal ACT output from 6a and output signals of shifters 18b and 18f shown in FIG.
0a, a set / reset flip-flop 30b which is set in response to the rise of the activation signal ACT and is reset in response to the fall of the output signal of the OR circuit 30a, and a set / reset flip-flop 30
clock enable signal CL output from the Q output of b
AND and KEN and internal clock signal intCLK supplied from clock input buffer 10 shown in FIG.
The circuit 30c is included. Internal clock signal φCLK applied to the column related control circuit is output from AND circuit 30c. Now, the operation of the column related control clock generator shown in FIG. 32 will be described with reference to the timing chart shown in FIG.

In FIG. 33, the CAS latency is 2
And the data read operation when the burst length is 4 is shown.

In clock cycle 1, an active command is applied, and activation signal ACT rises to H level. Depending on the set / reset flip-flop 3
0b is set and the clock enable signal CLKEN
Goes high, AND circuit 30c operates as a buffer, and outputs an internal clock signal φCLK to a column related control circuit in accordance with internal clock signal intCLK.

When a read command is applied in clock cycle 3, data is read in clock cycle 4, and clock signal e in clock cycle 5 is output.
At the rising edge of xtCLK, the first data Q0 is determined. Thereafter, in each of clock cycles 6 to 8, data Q is output at the rising edge of clock signal extCLK.
1 to Q3 are settled.

In clock cycle 7, a precharge command is applied. According to this precharge command, activation signal ACT falls to L level, and becomes inactive. In this clock cycle 7, the memory array returns to the precharge state, while the last selected burst length data Q3 is transferred, and is settled at the rising edge of clock signal extCLK in clock cycle 8. In this clock cycle 8,
The output signal of shifter 18b falls to L level, the output of the burst length data is completed, and the output signal of OR circuit 30a falls to L level. Accordingly, set / reset flip-flop 30b is reset, and clock enable signal CLKEN falls to L level. In clock cycle 8, AND circuit 30c generates internal clock signal φCLK, and after clock cycle 9, generation of internal clock signal φCLK is stopped. That is, while the semiconductor memory device is in the standby state and after the operation of the column related circuit is completed, generation of internal clock signal φCLK is stopped. Thereby, generation of internal clock signal φCLK in an unnecessary period is stopped, and current consumption is reduced.

FIG. 34 shows a structure of a portion for controlling data writing to the mode register shown in FIG.

In FIG. 34, data writing to the mode register is performed by a control signal from mode register control circuit 32. This mode register control circuit 3
2 generates a one-shot pulse signal having a predetermined time width according to activation of mode setting instruction signal φmode from command decode circuit 16 d included in command decoder 16, and provides it to mode register 22. The mode register 22 is a normal register circuit or a flip-flop. Under the control of the mode register control circuit 32, the input section is connected to an external terminal (address terminal or data input terminal), and the data of the given data is Acquire and latch.

The data set in the mode register includes CAS latency data, burst length data, data indicating a burst address generation sequence, and the like. When writing data to the mode register,
Row-related circuits and column-related circuits do not operate.

[0042]

FIG. 35 is a diagram showing an initialization sequence when the power supply of the synchronous semiconductor memory device (synchronous DRAM) is turned on. The initialization sequence shown in FIG. 35 is standardized by JEDEC (Joint Electronics Device Engineers Council).

As shown in FIG. 35, at time T0,
After the power supply voltage Vcc is applied to the synchronous DRAM, the synchronous DRAM is in a standby state during a period S1, that is, until the power supply voltage Vcc is stabilized. During this standby period, the voltage levels of the internal signal lines and internal nodes are stabilized. Then
In the period S2, when the synchronous DRAM has a plurality of banks, all banks are precharged. This is done by applying a precharge command. Thereby, synchronous DR
The internal circuit of the AM is returned to the precharge state. After the precharge operation, in a period S3, the auto refresh operation is repeated eight times or more by the auto refresh command. Even if bank precharge is performed, the internal signal lines or internal nodes may be precharged to the wrong potential. Performing auto-refresh and operating the internal circuit ensures active and inactive states. To return the internal signal lines and internal nodes to a predetermined initial state (precharged state).

After the auto-refresh has been performed eight times or more, in a period S3, the initial setting of the CAS latency data and the burst length data in the mode register is performed. Through a series of these initialization sequences, the internal circuit is set to a normal (predetermined) precharge potential level, and the subsequent operation is accurately started.

However, when the auto-refresh operation is performed, as shown in FIG.
Operate, and row-related circuits such as the row selection circuit operate. However, the refresh operation activation signal RFACT is
It is not provided to the column control circuit. That is, when an auto-refresh command is applied and an auto-refresh operation is performed, the row-related circuits operate but the column-related circuits do not operate. Therefore, when the power supply is turned on and the potential of the column related circuit is erroneously set for some reason, the internal nodes may not be initialized to the normal potential level by the auto-refresh operation in this period S3. Occurs.

As shown in FIG. 32, an internal clock signal φCLK applied to a column related control circuit is generated in accordance with an activation signal ACT, and is internally provided to this column control circuit in accordance with a refresh activation signal RFACT. No circuit φCLK is generated. Therefore, the burst length counter and the latency counter included in the column related control circuit do not operate in the period S3, and therefore, such a burst length counter and a latency counter (shifter) are not initialized to a predetermined voltage level, An incorrect voltage level may be set, and a malfunction may occur in subsequent operations.

Also in the mode register setting performed in period S4, the mode register set command
It is not supplied to the row related control circuit and the column related control circuit, and controls only the operation of the mode register. Therefore, even during this period, the column-related circuit does not operate, and the generation of the internal clock signal for the column-related control circuit is stopped.

As described above, in the initialization sequence after the power is turned on, there is a problem that the column-related circuit does not operate, the initial voltage is not accurately set to a predetermined voltage level, and a malfunction may occur.

An object of the present invention is to provide a synchronous semiconductor memory device in which all internal circuits can be reliably initialized to a normal voltage level after power is turned on.

Another object of the present invention is to provide a synchronous semiconductor memory device capable of reliably initializing a column circuit after power is turned on.

[0051]

A synchronous semiconductor memory device according to the present invention is coupled to a power supply node to which an external power supply voltage is supplied, and detects the input of an external power supply voltage according to the voltage level of the power supply node. Power-on detection means for generating a power-on detection signal, and a reset period definition activated in response to activation of the power-on detection signal and deactivated in response to a predetermined operation mode instruction signal A reset period defining means for generating a signal, an internal circuit operating in response to the internal clock signal when activated, and an internal clock generating means for generating an internal clock signal in synchronization with an external clock signal are provided. The internal clock generating means generates an internal clock signal when the reset period defining signal is activated, and stops generation of the internal clock signal when the internal circuit is inactive and the reset period defining signal is inactive. including.

The synchronous semiconductor memory device according to claim 2 is
2. A read circuit for reading data of a selected memory cell among a plurality of memory cells when activated, a refresh instruction for instructing a refresh of data of the plurality of memory cells, and a reset. A read control means for activating this read circuit in response to the active state of the period defining signal is included.

The synchronous semiconductor memory device according to claim 3 is
The internal circuit according to claim 2 activates the output circuit for outputting data from the readout circuit to the outside of the device when activated, and activates the output circuit in response to a refresh instruction and an active state of a reset period defining signal. Output control means is further provided.

The synchronous semiconductor memory device according to claim 4 is
And a write circuit for writing data to a selected memory cell of the plurality of memory cells when activated, a refresh instruction for instructing data refresh of the plurality of memory cells, and a reset period defining signal. Write control means for activating this write circuit in response to the active state is included.

According to a fifth aspect of the present invention, there is provided a synchronous semiconductor memory device, wherein the internal circuit according to the second or third aspect further comprises a write circuit for writing data to a selected one of the plurality of memory cells when activated. And write control means for activating the write circuit in response to the refresh instruction and the active state of the reset period defining signal.

The synchronous semiconductor memory device according to claim 6 is
2. A write circuit for writing data to a selected memory cell of a plurality of memory cells when activated, and data of a selected memory cell among the plurality of memory cells when activated, Circuit, and a refresh instruction for instructing data refresh of a plurality of memory cells and an active state of a reset period defining signal,
Write / read control means for alternately activating the write circuit and the read circuit in a predetermined sequence is included.

A synchronous semiconductor memory device according to claim 7 is
A plurality of memory cells according to claim 1 are divided into a plurality of memory banks which are activated and deactivated independently of each other, and an internal circuit is provided corresponding to each of said plurality of memory banks. A plurality of reading means for reading data to a selected memory cell of a corresponding memory bank; Read control means for sequentially activating the read circuits in a predetermined sequence.

The synchronous semiconductor memory device according to claim 8 is
A plurality of memory cells according to claim 1 are divided into a plurality of memory banks driven to an active state and an inactive state independently of each other, and an internal circuit is provided corresponding to each of the plurality of memory banks. In response to a plurality of writing means for writing data to a selected memory cell of a corresponding memory bank, a refresh instruction for instructing data refresh of the plurality of memory cells, and an active state of a reset period defining signal, Write control means for sequentially activating write circuits of a plurality of memory banks in a predetermined sequence is included.

The synchronous semiconductor memory device according to claim 9 is
A plurality of memory cells according to claim 1 are divided into a plurality of memory banks driven to an active state and an inactive state independently of each other, and an internal circuit is provided corresponding to each of the plurality of memory banks. A plurality of read circuits for reading data of a selected memory cell in the memory bank corresponding to the time, and a plurality of read circuits provided corresponding to each of the plurality of memory banks, for transferring data to the selected memory cell in the memory bank corresponding to the activation. A plurality of write circuits for writing, a plurality of read circuits provided corresponding to each of the plurality of memory banks, and a plurality of read circuits for reading data of a selected memory cell of the corresponding memory bank when activated; In response to a refresh instruction instructing data refresh of a memory cell and a reset period defining signal, write circuits and read circuits of these memory banks Including a read / write control means for sequentially activated Sequence.

According to a tenth aspect of the present invention, there is provided the synchronous semiconductor memory device, wherein the internal clock generating means according to the first to ninth aspects is such that when a reset period defining signal is inactivated, a selected one of the plurality of memory cells is in a selected state. Is activated in response to the activation of an internal activation signal defining a certain period, and when an access instruction instructing data writing / reading is applied, continuous writing is performed when the internal activation signal is inactivated. After the lapse of the sum of the period of the product of the number of data to be read / written and the cycle of the external clock signal and the latency indicating the number of clock cycles from when the access instruction is given to when valid data is output to the outside, the non- Activated state.

An internal clock signal is applied to the internal circuit during a period defined by the reset period defining signal from power-on, so that the internal circuit is clocked during the reset period. When the internal circuit is in the standby state during a period different from the reset period, the internal clock signal is not applied. Initialization of the internal circuit after power-on can be reliably performed without increasing current consumption in the normal operation mode.

[0062]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 shows a structure of a main part of a synchronous semiconductor memory device according to a first embodiment of the present invention.
FIG. 1 shows a configuration of an internal clock signal φCLK generation unit applied to a column related control circuit. The other configuration is the same as the configuration shown in FIG. In FIG. 1, a synchronous semiconductor memory device includes a power supply node 1 to which power supply voltage Vcc is applied.
00, a power-on detection circuit 102 for detecting that power to the synchronous semiconductor memory device has been turned on in accordance with the level of power supply voltage Vcc, and a power-on detection signal / Mode register setting instruction signal φmod set according to POR
e, and reset period defining signal RAR
Set / reset flip-flop 104 that generates
And internal clock signal φCL applied to the column related control circuit in accordance with reset period defining signal RAR, clock enable signal CLKEN and internal clock signal intCLK.
A column clock generating circuit 130 for generating K is included. Clock enable signal CLKEN is output from set / reset flip-flop 30b shown in FIG. Internal clock signal intCLK is output from clock input buffer 10 shown in FIG.

The reset period defining signal generation circuit 104
Inverter 104a receiving mode register setting instruction signal φmode, NAND circuit 104b receiving power-on detection signal / POR at one input, and inverter 104a
, Which receives NAND output signal at one input. Outputs and the other inputs of NAND circuits 104b and 104c are cross-coupled. The reset period defining signal RAR is output from the NAND circuit 104b.

The column related clock generation circuit 130 generates a reset period defining signal RAR and a clock enable signal CLKE.
And an internal clock signal intCLK synchronized with the output signal of the OR circuit 130a and the external clock signal extCLK from the clock input buffer.
And an AND circuit 130b receiving the same. AND circuit 130b outputs an internal clock signal φCLK for the column related control circuit. Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIGS.

First, the operation of the reset period defining signal generation circuit 104 will be described with reference to FIG.

At time T0, power is turned on, and power supply voltage Vcc applied to power supply node 100 rises in voltage level.

At time T1, power supply voltage Vcc reaches a prescribed voltage level. From time T0 to time T1, no mode register setting command is applied, and mode register setting instruction signal φmode maintains the L level. The power-on detection signal / POR changes from time T0 to time T1.
The reset period defining signal RAR output from the NAND circuit 104b rises in voltage as the power supply voltage Vcc rises.

When power supply voltage Vcc reaches a predetermined voltage level and a predetermined time elapses to enter a stable state, power-on detection signal / POR from power-on detection circuit 102 rises to H level, and set / reset flip-flop 104
Holds the set state. In the set state of set / reset flip-flop 104, reset period defining signal RAR maintains H level.

At time T3 after a lapse of a predetermined time from time T2, auto refresh is performed. The precharge operation by the precharge command has already been completed at time T3. This auto refresh is performed at time T
Performed 8 times or more during the period up to 4. By repeating the auto-refresh between time T3 and time T4, the internal circuits (the column-related control circuit and the row-related circuit in the first embodiment) are initialized. The reason why the auto-refresh is performed in the initialization sequence is that the row-related circuits automatically return from the active state to the precharge state internally by the auto-refresh command. If a normal active command and a precharge command are used, each of these commands requires one clock cycle, and the initialization period becomes longer.
The time required from power-on to the start of access for normal operation increases.

When the required number of auto refreshes has been executed by time T4, a mode register set command is applied at time T5. According to the mode register set command, mode register setting instruction signal φmode rises to H level for a predetermined period. Accordingly, the output signal of inverter 104a falls to L level,
The output signal of the AND circuit 104c becomes H level,
Reset period defining signal RAR output from ND circuit 104b rises to L level. Thereby, the reset period ends. Therefore, after this reset period,
According to clock enable signal CLKEN, internal clock signal φC according to internal clock signal intCLK (external clock signal extCLK) only for a required period.
LK is generated.

Next, the operation of column clock signal generating circuit 130 will be described with reference to FIG.

In FIG. 3, reset period defining signal R
The operation when AR is in the active state at the H level and in the reset period is shown. When reset period defining signal RAR is at H level, the output signal of OR circuit 130a is at H level even if clock enable signal CLKEN is set at L level, and AND circuit 13
0b outputs a column related clock signal φCLK according to the internal clock signal intCLK.

When a mode register set command is applied in clock cycle #, resetting of set / reset flip-flop 104 in response to mode register setting instruction signal φmode causes reset period defining signal RAR to fall to L level, causing internal clock signal φC
The occurrence of LK is stopped.

The column related control circuit has a configuration as shown in FIG. Therefore, according to the first embodiment, the burst length counter and the shifter can be operated by supplying clock signal φCLK to the period column control circuit specified by reset period specifying signal RAR immediately after power-on, and Can be reliably initialized. Therefore, even if the period T shown in FIG.
Even when auto-refresh is performed in accordance with the auto-refresh command from 3 to time T4 and only the row-related circuit is operating, the column-related control circuit is supplied with column-related clock signal φCLK, and has a burst length counter and The shifter operates, and the count value can be reliably initialized.

FIG. 4A is a diagram showing an example of the configuration of the power-on detection circuit 102 shown in FIG. 4A, a power-on detection circuit 102 includes a resistance element 102b connected between a power supply node 100 and an internal node 102a.
And a capacitor 102c connected between the internal node 102a and the ground node, an inverter 102d for inverting a signal potential on the internal node 102a, and an output signal of the inverter 102d to output a power-on detection signal / POR. Includes inverter 102e. Next, the operation of the power-on detection circuit 102 shown in FIG. 4A will be described with reference to a waveform diagram shown in FIG.

At time T0, power is turned on, and the voltage level of power supply voltage Vcc on power supply node 100 rises. The voltage level of internal node 102a is
It gradually increases with a time constant determined by the resistance value of the capacitor 02b and the capacitance value of the capacitor 102c.

At time T1, power supply voltage Vcc reaches a predetermined voltage level, and the voltage level becomes constant.
At this time, since the voltage level of internal node 102a is still low and lower than the input logic threshold value of inverter 102d, power-on detection signal / POR is at the L level.

At time T2, the internal node 102
When the voltage level of a becomes higher than the input logic threshold value of inverter 102d, the output signal of inverter 102d falls, and power-on detection signal / POR output from inverter 102e rises to H level.

By setting the resistance value of the resistance element 102b and the capacitance value of the capacitance element 102c to appropriate values, the time from time T1 to time T2 can be set to an appropriate value. When voltage Vcc attains a stable state, power on detection signal / POR can be driven to an active H level.

FIG. 5 is a diagram showing another configuration of the internal clock signal generator. In FIG. 5, an internal clock generator includes an AND circuit 140a receiving power-on detection signal / POR and reset period defining signal RAR, and an AND circuit 14a.
NOR circuit 140b receiving an output signal of 0a and activation signal ACT, an OR circuit 140c receiving output signals of shifters 18b and 18f shown in FIG. 30, and NOR circuit 14
0b is received at one input. NAND circuit 14
0d and a NAND circuit 140e receiving an output signal of the OR circuit 140c at one input. NAND circuit 140d
Outputs clock enable signal CLKEN.
The other inputs and outputs of NAND circuits 140d and 140e are cross-coupled.

Internal clock signal generating section further includes an inverter 140g receiving power on detection signal / POR,
Inverter 140g conducts when the output signal is at H level, and reset transistor 140h formed of an n-channel MOS transistor driving clock enable signal CLKEN to L level at the ground potential level; internal clock signal intCLK and clock enable signal CL
Includes an AND circuit 140f receiving KEN. AND circuit 140f outputs internal clock signal φCLK.

Next, the operation of the internal clock generator shown in FIG. 5 will be described with reference to a timing chart shown in FIG.

In FIG. 6, power is turned on at time T0, and the voltage level of power supply voltage Vcc rises.
As described above, the voltage level of the reset period defining signal RAR increases in accordance with the power-on. When the voltage level of power supply voltage Vcc becomes stable, power on detection signal / POR rises to H level at time T1.
From time T0 to time T1, the power-on detection signal / P
OR is at the L level. Therefore, even if reset period defining signal RAR rises to H level, AND circuit 14
0a is at the L level, and the NOR circuit 140b
Is at the H level (the activation signal ACT is also at the L level). On the other hand, during this period, the output signal of inverter 140e receiving power-on detection signal / POR attains H level, reset transistor 140h conducts, and resets clock enable signal CLKEN to L level.
Therefore, during this time, generation of internal clock signal φCLK is stopped.

At time T1, the power-on detection signal / P
When OR rises to H level, the output signal of AND circuit 140a goes to H level, and the output signal of NOR circuit 140b goes to L level in response. A flip-flop constituted by NAND circuits 140d and 140e is set, clock enable signal CLKEN from NAND circuit 140d attains an H level, and a column related internal clock signal φCLK is generated according to internal clock signal intCLK.

At time T2, when a mode register set command is applied, reset period defining signal RAR
Falls to the L level, and the output signal of NOR circuit 140b rises to the H level. The output signal of OR circuit 140c is at L level, and the output signal of NAND circuit 140e is at H level. Therefore, an H level signal is applied to both inputs of NAND circuit 140d, and clock enable signal CLKEN is supplied. Fall to L level.

In the normal operation mode, when an active command is applied at time T3, activation signal A
CT rises to the H level, the output signal of NOR circuit 140b falls from the H level to the L level, clock enable signal CLKEN rises to the H level, and column related internal clock signal φCLK is generated again according to internal clock signal intCLK. You.

At time T4, a read command or a write command is applied, and data reading or writing is performed.

At time T5, a precharge command is applied, and activation signal ACT falls to L level.
Accordingly, the output signal of NOR circuit 140b rises to H level. In this state, the shifter 18b or 18f
Is at the H level, and reading or writing of burst length data is being performed. Therefore, the output signal of NAND circuit 140e is at L level, and
Clock enable signal CLKE from D circuit 140d
N also maintains the H level.

At time T6, when all the burst length data is read or written, the output signal of shifter 18b or 18f falls to L level, and the output signal of OR circuit 140c falls to L level. Accordingly, N
The output signal of AND circuit 140e attains H level. NA
Since ND circuit 104d receives a signal of H level at both inputs, clock enable signal CLKEN which is an output signal thereof falls to L level, and generation of column related internal clock signal φCLK is stopped. That is, column-related internal clock signal φCLK is generated in accordance with internal clock signal intCLK from the time the active command is applied until the operation of the column-related circuit is completed.

Using the structure of the internal clock generating unit shown in FIG. 5, after power-on, clock enable signal CL
After KEN is surely reset to the L level and power supply voltage Vcc is stabilized during the reset period, column related internal clock signal φ according to internal clock signal intCLK.
CLK can be generated. During the reset period, the auto refresh is performed at time T
1 or later. Therefore, internal clock intCLK
Is in a stable state, the column internal clock signal φC
LK can occur during the reset period.

In the above description, the clock enable signal CLKEN is described so as to define the operation timing of the column related control circuit. However, internal clock signal φCLK is applied to only a necessary counter portion of a part of the column related control circuit, for example, a burst length counter and a latency counter and a burst address generation counter during the reset period. It may be configured as follows.

As described above, according to the first embodiment of the present invention, in the normal operation mode, when the circuit is in the standby state, the generation of the internal clock signal is stopped and during the reset period, the internal clock signal is stopped. Since the configuration is such that the internal clock signal is generated, it is possible to initialize the circuit that operates according to the internal clock signal after the power is reliably turned on.

[Second Embodiment] FIG. 7 shows a structure of a main part of a synchronous semiconductor memory device according to a second embodiment of the present invention. In FIG. 7, a command decoder (FIG. 2)
6) auto-refresh operation instruction signal φar
Read trigger signal generating circuit 17 for generating read trigger signal φrt in accordance with read operation instruction signal φread
0 and read / output control circuit 180 for controlling data read and output operations in accordance with read trigger signal φrt.
Is provided. This read / output control circuit 180 corresponds to FIG.
It includes a burst length defining circuit 18a, a shifter 18b, a read control circuit 18c, and an output control circuit 18d indicated by 0.
When read trigger signal φrt is activated, it is included in a column selection circuit, a read circuit included in a write / read circuit, and an input / output circuit under the control of read / output control circuit 180. Output circuit is internal clock signal φCL
It operates according to K.

In the structure shown in FIG. 7, internal clock signal φCLK described in the first embodiment is applied to read / output control circuit 180.

Read trigger signal generating circuit 170 delays auto-refresh operation instructing signal φar provided from a command decoder (not shown) by a predetermined time.
70a and the delay circuit 17 when the reset period defining signal RAR and the inverted reset period defining signal / RAR are activated.
0a from the delay auto-refresh operation instruction signal φar
and a read operation instructing signal φ from a command decoder (not shown) when signals RAR and / RAR are inactivated.
It includes a tri-state inverter buffer 170c for inverting and outputting read, and an inverter 170d for inverting signals output from these tri-state inverter buffers 170b and 170c. Tristate inverter buffers 170b and 170c are set to an output high impedance state when inactive. next,
The operation of the read trigger signal generation circuit shown in FIG. 7 will be described with reference to a timing chart shown in FIG.

Power is turned on in cycle 0 of external clock signal extCLK, and the voltage level of reset period defining signal RAR rises. In response to activation (H level) of reset period defining signal RAR, tri-state inverter buffer 170b is activated,
On the other hand, the tri-state inverter buffer 170c enters an output high impedance state.

After the precharge command is applied, in clock cycle 2, an auto refresh command for initialization is applied, and auto refresh operation instructing signal φar rises to the H level for a predetermined period. The refresh control circuit 20 performs control necessary for the refresh operation according to the auto-refresh operation instruction signal φar. After the generation of the auto-refresh operation instruction signal φar, the delay time T
When d elapses, delayed auto refresh operation instructing signal φard rises to H level. This delay circuit 170a
Is usually the RAS-CAS delay time t
Equal to the time called RAD. The delayed auto refresh operation instructing signal φard is inverted by the tri-state inverter buffer 170b,
0d.

In clock cycle 4, when read trigger signal φrt output from inverter 170d is activated, read / output control circuit 180 operates according to internal clock signal φCLK. When the read / output control circuit 180 operates in this initialization sequence,
The burst length and the CAS latency data are not set in the mode register. In the initialization sequence, the row-related circuit sets 1 according to the auto-refresh command.
Since the column-related circuit only needs to operate once each time it operates, the burst length and the CAS latency are the minimum values of 1
May be set respectively. For this setting, a configuration may be used in which the burst length data and the CAS latency data stored in the mode register are set to initial values in accordance with the rise of power-on detection signal / POR. Under the control of the read / output control circuit 180, FIG.
6, a read circuit included in the write / read circuit 4 and an output circuit included in the input / output circuit 5 operate. Thereafter, each time the auto-refresh command is given, the column-related circuit operates at least once.

When the initialization of the row related circuits and column related circuits is completed, a mode register set command is applied in clock cycle 6. By this mode register set command, the reset period defining signal RAR becomes inactive at L level, the tri-state inverter buffer 170b enters an output high impedance state, and the tri-state inverter buffer 170c enters an operating state. The mode register set command is a command independent of the read command and the write command. That is, even if the mode register set command is applied, the operation has no effect on the column related control circuit. Therefore, even if a mode register set command is applied when auto-refresh is performed and read trigger signal φrt is internally generated, the initial setting of the mode register has no adverse effect on data reading for initialization. Not affected. The mode register uses data applied to the address pins as CAS latency data and burst length data (this is to prevent the mode register setting operation from affecting the data input / output operation).

When these series of initialization sequences are completed, a normal operation cycle starts. In FIG. 8, a read command is applied in clock cycle 10. According to this read command, read operation instruction signal φ
read is generated from the command decoder, and the tri-state inverter buffer 170c and the inverter 17
Read trigger signal φrt is generated via 0d, and read / output control circuit 180 performs a control operation necessary for reading and outputting data. In clock cycle 10, an active command has already been applied, and internal clock signal φCLK has been generated (see FIG. 5).

As described above, according to the second embodiment of the present invention, since a read trigger signal is generated in an initialization sequence, a circuit portion for reading and outputting data is initialized. Operation can be performed in a sequence, and these circuits can be reliably initialized.

[Third Embodiment] FIG. 9 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a third embodiment of the present invention. FIG. 9 schematically shows a configuration of read / output control circuit 180 shown in FIG. The read / output control circuit 180 includes the read trigger signal generation circuit 1
Read control circuit 180 for controlling column selection and transfer of read data in accordance with read trigger signal φrt from.
a, AND circuit 180c receiving read trigger signal φrt and inverted reset period defining signal / RAR;
An output control circuit 180b for controlling the operation of the output circuit according to the signal OT output from the circuit 180c is included. Output control circuit 180b outputs an output permission signal OEM.
While the output permission signal OEM is active, the output circuit outputs data in synchronization with the clock signal.

The read trigger signal generation circuit 170 has the configuration shown in FIG.
Has the same configuration as the configuration shown in FIG. The inversion reset period defining signal / RAR is at L level during the reset period, and
The output signal of D circuit 180c is fixed at L level during this time. Therefore, the operation of output control circuit 180b is prohibited during this reset period.

FIG. 10 shows the read control circuit 180 shown in FIG.
FIG. 3A is a diagram schematically showing an example of the configuration of an output control circuit. In FIG. 10, read control circuit 180a includes a burst long term defining circuit 181 and a shifter 182 which shifts an output signal of burst long term defining circuit 181 for a period determined by CAS latency. This structure is the same as the structure shown in FIG. 30. This read control circuit includes a read control circuit for performing column selection and data transfer in addition to burst length defining circuit 181 and shifter 182 (see FIG. 30). . The burst length defining circuit 181 is activated in response to the read trigger signal φrt, and is set in response to the activation of the read trigger signal φrt and a burst length counter 181a for counting the long period of the burst. It includes a set / reset flip-flop 181b reset according to a signal.
Therefore, the output signal of burst length defining circuit 181 (the output signal of flip-flop 181b) is active for a long period of the burst period after application of read trigger signal φrt. Shifter 182 delays the output signal of burst length defining circuit 181 for a period defined by the CAS latency (accurately, CAS latency-1 clock cycle), and generates output enable signal OEMM.

The burst length counter 180a and the shifter 182 receive the internal clock signal φCLK in the first embodiment.

Output control circuit 180b provides output control signal O
In response to the set / reset flip-flop 183a set in response to the activation of T, the output signal of the set / reset flip-flop 183a and the output enable signal OEMM from the shifter 182, the output enable signal OEM is sent to the output circuit. And a one-shot pulse generation circuit 183c for generating a one-shot pulse signal in response to the fall of output permission signal OEM output from AND circuit 183b. The output signal of one-shot pulse generation circuit 183c is applied to the reset input of set / reset flip-flop 183a.

The operation of the circuits shown in FIGS. 9 and 10 will now be described with reference to the timing chart shown in FIG.

Power is turned on in clock cycle 0 of external clock signal extCLK, and reset period defining signal RAR rises to H level.

In clock cycle 2, an auto-refresh command for initialization is applied, auto-refresh operation instructing signal φar is at H level for a predetermined period, and refresh control circuit 20 performs a refresh operation. In response to the auto-refresh operation instruction signal φar, the read trigger signal generation circuit 170 generates a read trigger signal φrt (see FIG. 7). Read control circuit 180a is activated according to read trigger signal φrt, and performs a column selection operation and an internal data transfer operation. In a burst defining circuit included in read control circuit 180a, flip-flop 181b is set to a set state for a long period of a burst, and outputs a signal in an active state.
Shifter 182 delays the output signal of burst length defining circuit 181 by the number of clock cycles defined by CAS latency and outputs an output enable signal OEMM.

In this initialization operation, reset period defining signal / RAR is at L level, and AND circuit 180
The output control signal OT from c is at the L level. Therefore, flip-flop 183a is not set, and output enable signal OEM at L level is applied to the output circuit by AND circuit 183b. Thus, the operation of the output circuit is stopped during the initialization operation.

In clock cycle 6, a mode register set command is applied, the initialization operation is completed, and reset period defining signal RAR falls to L level. As a result, the inverted reset period defining signal / RAR rises to the H level, and the AND circuit 180c operates as a buffer.

In the normal operation cycle, when a read command is applied in clock cycle 10, read operation instruction signal φread is applied from the command decoder, and read trigger signal generation circuit 170 causes read trigger signal φrt in accordance with read operation instruction signal φread. Activate. The AND circuit 180c outputs the read trigger signal φ
rt, and the output control signal OT is activated. As a result, in the output control circuit 180b, the set / reset flip-flop is set, and the shifter 1
An output permission signal OEM is generated in accordance with the output permission signal OEMM provided from. In response, the output circuit operates to generate external read data from the internal read data and output it in synchronization with the clock signal.

By stopping the operation of the output circuit in the initialization sequence, the current consumption of the output circuit having a large current driving force for driving an external load at a high speed can be reduced. An increase in current consumption can be suppressed.

[Modification] FIG. 12 shows a structure of a modification of the third embodiment of the present invention. In FIG.
Output control circuit 180b includes an AND circuit 183d receiving output enable signal OEMM from shifter 182 and inverted reset period defining signal / RAR. In the configuration shown in FIG. 12, output enable signal OEM is fixed at L level during the reset operation period in which reset period defining signal / RAR is at L level. In a normal operation cycle, inverted reset period defining signal / RAR is at H level, and signal OEM is applied.
An output permission signal OEM is generated according to M.

The output permission signal OEM controls the activation / inactivation of the output buffer at the last stage of the output circuit. In accordance with output enable signal OEM, output data transfer instruction signal DOT for taking in and latching transfer data in the output circuit is generated. The generation of output data transfer instruction signal DOT may be stopped, or output data transfer instruction signal DOT may be generated (signal OEM).
An output data transfer instruction signal DOT is generated from M). It is the output buffer of the final output stage that consumes a large current in the output circuit, and even if the operation of only the output buffer of the final stage is stopped, the current consumption during the initialization operation can be sufficiently reduced. The internal nodes of the output circuit can be reliably initialized.

[Fourth Embodiment] FIG. 13 is a diagram schematically showing a configuration of a main portion of a synchronous semiconductor memory device according to a fourth embodiment of the present invention. FIG. 13 shows a configuration of a portion for controlling the data write operation. The write operation control unit receives an auto-refresh operation instruction signal φar and a write operation instruction signal φwrite, selects one according to reset period defining signals RAR and / RAR, and generates a write trigger signal φwt for generating a write trigger signal φwt. Circuit 190 and a write / input control circuit 200 for controlling a data write operation in accordance with write trigger signal φwt. This write / input circuit 200 includes a bar length defining circuit 18e, a shifter 18f, an input control circuit 18g, and a write control circuit 18h shown in FIG.

Write trigger signal generating circuit 190 includes a delay circuit 190a for delaying auto-refresh operation instructing signal φar for a predetermined time, an active state when reset period defining signals RAR and / RAR are active and a reset period is designated. A tri-state inverter buffer 190b for inverting and outputting the delayed auto-refresh operation instruction signal φard from the delay circuit 190a;
When reset period defining signals RAR and / RAR are inactive and indicate a period other than the reset period, they are activated, and a tri-state inverts and outputs write operation instruction signal φwrite provided from a command decoder (not shown). Inverter 190c and inverter 190d for inverting the output signals of tri-state inverter buffers 190b and 190c are included. Inverter 190d outputs a write trigger signal φwt. Delay circuit 190a has the same delay time as delay circuit 170a included in the read trigger signal generation circuit according to the second embodiment.

Also in this write operation, when an auto refresh command is applied, write / input control circuit 2
Under the control of 00, a write trigger signal φwt is generated, and a column address buffer included in the address buffer takes in an external address signal as a valid address signal and generates an internal column address signal. In the initialization sequence, the value of the address is arbitrary, and it is not necessary to specify a correct column. The selection is made according to the appropriate external column address.

The operation of write / input control circuit 200 in response to write trigger signal φwt from write trigger signal generation circuit shown in FIG. 13 is similar to that shown in FIG.
And read operation instruction signal φread is replaced with write operation instruction signal φ
It can be obtained by replacing with write. Therefore, if the read circuit and output circuit in the second embodiment are replaced with a write circuit and an input circuit, similar operations will be performed, and therefore detailed description will not be repeated.

Also in the fourth embodiment, when an auto refresh command is applied in the initialization sequence, tristate inverter buffer 190b
As a result, a write trigger signal φwt is generated, and column selection, input of external data, and transfer of internal data are performed. At the time of this data writing operation, appropriate arbitrary data is applied to the external terminal, and the writing operation is performed according to the data. What is needed in the initialization sequence is to repeatedly set the internal circuit to the initial state (precharge state) by repeating the active state and the precharge state. Therefore, whether or not accurate data writing is performed does not matter in the initialization sequence. Therefore, in this initialization sequence, no problem occurs even if the write circuits included in the column related circuits are operated, and these circuits can be reliably set to the initial state.

In the fourth embodiment also, internal clock signal φCLK generated in the first embodiment
Are provided as operation timing definition signals.

As described above, according to the fourth embodiment of the present invention, the configuration is such that a write trigger signal is generated when an auto refresh command is given in the initialization sequence. Can operate circuit portions related to data writing, and these circuit portions can be normally set to a predetermined initial state.

[Fifth Embodiment] FIG. 14 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a fifth embodiment of the present invention. FIG. 14 shows a configuration of a portion corresponding to the column control circuit shown in FIG. FIG.
4, the column related control circuit includes: a delay circuit 205 for delaying the auto-refresh operation instruction signal φar by a predetermined time;
One of the delayed auto refresh operation instruction signal φard and the read operation instruction signal φread is set to the reset period defining signal R
A read trigger signal generating circuit 170 for generating a read trigger signal φrt by selecting according to AR and / RAR;
Read / output control circuit 18 for controlling operations required for reading and outputting data according to read trigger signal φrt.
0, one of the delayed auto-refresh operation instruction signal φard and the write operation instruction signal φwrite in accordance with the reset period defining signals RAR and / RAR to generate a write trigger signal φwt.
90 and a write / input control circuit 200 for controlling operations required for inputting and writing data according to the write trigger signal φwt. Read / output control circuit 180 and write / input control circuit 200 operate in synchronization with column-related internal clock signal φCLK described in the first embodiment. The configurations of read / output control circuit 180 and write / input control circuit 200 are the same as those described in the second and fourth embodiments, respectively.

Read trigger signal generating circuit 170 is activated when reset period defining signals RAR and / RAR are activated, and inverts and transmits delayed auto refresh operation instructing signal φard from delay circuit 205. 170b, a tri-state inverter buffer 170c which is activated when the reset period defining signals RAR and / RAR are inactivated and inverts and transmits a read operation instruction signal φread provided from a command decoder (not shown); Includes an inverter 170d that inverts the output signals of 170b and 170c. Inverter 170d
Outputs read trigger signal φrt.

Write trigger signal generating circuit 190 is activated when reset period defining signals RAR and / RA are activated, and inverts and transmits delayed auto refresh operation instructing signal φard from delay circuit 205. 190b, a tri-state inverter buffer 190c which is activated when reset period defining signals RAR and / RAR are inactivated and inverts and transmits write operation instruction signal φwrite provided from a command decoder (not shown); Inverter 190d for inverting the output signals of buffers 190b and 190c is included. Inverter 190
d generates a write trigger signal φwt. Next, the operation of the column related control circuit shown in FIG. 14 will be described with reference to a timing chart shown in FIG.

Power is turned on in clock cycle 0 of external clock signal extCLK. As the power is turned on, the voltage level of reset period defining signal RAR rises and reaches H level. On the other hand, the inversion reset period defining signal / RAR maintains the L level.

In clock cycle 2 of external clock signal extCLK, an auto-refresh command for initialization is applied. According to the auto refresh command, the auto refresh operation instructing signal φar
Is generated in the form of a one-shot pulse. Reset period defining signal RAR is at an H level, inverted reset period defining signal / RAR is at an L level, and tri-state inverter buffers 170b and 190b are operating.
70c and 190c are in the output high impedance state. When delayed auto refresh operation instruction signal φard from delay circuit 205 is activated, read trigger signal φrt is activated in read trigger signal generation circuit 170 via tri-state inverter buffer 170b and inverter 170d. On the other hand, in write trigger signal generation circuit 190, tristate inverter buffer 190b and inverter 19
Through 0d, the write trigger signal φwt is activated according to the delayed auto-refresh operation instruction signal.
Therefore, read / output control circuit 180 and write / input control circuit 200 operate in accordance with an internal clock signal (not shown) to initialize a data read path and a data write path.

After a predetermined number of times (eight or more times) of the auto-refresh command is applied, a mode register set command is applied in clock cycle 4. By this mode register set command, reset period defining signal RAR is inactivated at L level, and inverted reset period defining signal / RAR is inactivated at H level. After the application of the mode register set command, tristate inverter buffers 170c and 190c are thus activated, while tristate inverter buffers 170b and 190b are in an output high impedance state.

In the normal operation mode, when a read command is applied in clock cycle 6, read operation instructing signal φread is applied from a command decoder (not shown). The read operation instruction signal φread is inverted by the tri-state inverter buffer 170c,
Then, it is inverted by inverter 170d to generate read trigger signal φrt. Thereby, read / output control circuit 180 is activated, and controls operations necessary for reading and outputting data.

In clock cycle 8, when a write command is applied, write operation instruction signal φwrite attains an active state of an H level for a predetermined period. In tristate inverter buffer 190c and inverter 190d, write trigger signal φwt is generated in accordance with write operation instruction signal φwrite and applied to write / input control circuit 200. Thereby, control operations required for data input and data writing are performed.

When access to the synchronous semiconductor memory device is not performed, an auto refresh command is applied in clock cycle 10. In accordance with the auto-refresh command, auto-refresh operation instructing signal φar is activated at H level for a predetermined period. Delayed auto-refresh operation instructing signal φard is output from delay circuit 205, but tri-state inverter buffers 170b and 190b are both in an output high impedance state. Therefore, read trigger signal φrt and write trigger signal φwt are not generated, and the column circuit does not operate.

Note that also in the fifth embodiment, the output circuit may be configured not to operate during the reset period. During the reset period, the read circuit and the write circuit operate simultaneously by the auto-refresh command. However, in the initialization sequence, it is necessary to set the internal nodes / signal lines to the initial state (precharge state), and correct data Is not a problem, and it does not matter if these read and write circuits operate simultaneously.

As described above, according to the fifth embodiment of the present invention, the write / input control circuit and the read control circuit are operated by the auto-refresh command in the initialization sequence, so that the data writing can be reliably performed. System and data reading system circuits can be set to the initial state.

[Sixth Embodiment] FIG. 16 shows a structure of a main portion of a synchronous semiconductor memory device according to a sixth embodiment of the present invention. FIG. 16 shows a configuration of a column related control circuit. The configuration of the column related control circuit shown in FIG.
It differs from the configuration of the column related control circuit according to the fifth embodiment shown in FIG. 14 in the following points.

That is, the read trigger signal generation circuit 17
0 is the least significant bit (LSB) / RFA of the refresh address counter 6 in addition to the configuration shown in FIG.
It further includes an OR circuit 170e receiving 0 and the inverted reset period defining signal / RAR, and an AND circuit 170f receiving a read trigger signal φrt output from the inverter 170a and an output signal of the OR circuit 170e. AND circuit 1
The second read trigger signal φrtd from 70a is read /
It is provided to output control circuit 180.

The write trigger signal generation circuit 190 has the structure shown in FIG.
In addition to the configuration shown in FIG. 4, inverter 190e receiving refresh address least significant bit / RFA0
An OR circuit 190f receiving an output signal of inverter 190e and a reset period defining signal / RAR, and OR circuit 1
An AND circuit 190g receives an output signal of 90f and a write trigger signal φwt output from inverter 190a. Second write trigger signal φwtd output from AND circuit 190g is applied to write / input control circuit 200.

In FIG. 16, another configuration is the same as that of FIG.
And the corresponding parts are denoted by the same reference numerals and detailed description thereof will not be repeated. The refresh address counter 6 updates the count value by 1 to generate a refresh address when an auto-refresh command is given for the control of the refresh control circuit 20. The refresh address from refresh address counter 6 is applied to the row selection circuit via the multiplexer shown in FIG. Next, FIG.
17 will be described with reference to an operation sequence diagram shown in FIG.

In clock cycle 0 of external clock signal extCLK, power is turned on, and the voltage level of reset period defining signal RAR rises and stabilizes at a predetermined voltage level of H level. On the other hand, the inversion reset period defining signal / RAR maintains the L level.

In clock cycle 2, an auto-refresh command is applied for initialization. In accordance with the auto-refresh command, an auto-refresh operation instructing signal φar is generated and applied to refresh control circuit 20 and delay circuit 205. The refresh address counter 6 includes the refresh control circuit 2
Under the control of 0, the count value is updated by 1. FIG.
, The least significant bit from refresh address counter 6 is set to 0,
An operation sequence in which RFA0 is set to the H level is shown as an example. An auto-refresh operation is performed under the control of the refresh control circuit 20.

On the other hand, delayed auto-refresh operation instructing signal φard from delay circuit 205 is supplied in clock cycle 3
Rises to the H level for a predetermined period. When reset period defining signal RAR is at the H level, tri-state inverters 170b and 190b are in operation, and tri-state inverter buffers 170c and 190b are inactive.
c is in the output high impedance state. Therefore,
In clock cycle 3, when delayed auto refresh operation instructing signal φard is generated, read trigger signal φrt from inverters 170d and 190d is generated.
And write trigger signal φwt rises to H level for a predetermined period.

The inversion reset period defining signal / RAR is at the L level, the OR circuits 170e and 190f operate as buffers, and the least significant bit / RFA0 from the refresh address counter is passed by the OR circuit 170e, while the OR circuit 190f Pass the inverted value of the least significant refresh address bit / RFA0 from the inverter 190e. This refresh address bit /
RFA0 is at the H level, and therefore AND circuit 17
0f receives an H-level signal at one input and the other A
ND circuit 190g receives an L level signal at one input. Therefore, in clock cycle 3, second read trigger signal φrtd is activated according to read trigger signal φrt, and read / output control circuit 18
Given to 0. Write / input control circuit 200 is supplied with a second circuit trigger signal φwtd in an inactive state of L level.
Is given. Therefore, read / output control circuit 180
Only operates to initialize the data read / output path.

In clock cycle 6, an auto refresh command is applied again. In response to the application of the auto refresh command, the refresh control circuit 2
“0” updates the count value of the refresh address counter 6. By this update, the least significant refresh address bit / RFA0 falls from H level to L level. Refresh control circuit 20 performs a refresh operation in accordance with auto-refresh operation instruction signal φar.

When delayed auto refresh operation instructing signal φard from delay circuit 205 rises to H level for a predetermined period in clock cycle 7, read trigger signal φrt and write trigger signal φwt attain H level for a predetermined period. Least significant refresh address bit / R
FA0 is at the L level, the output signal of the OR circuit 170e is at the L level, and the output signal of the OR circuit 190f is at the H level. Therefore, the second read trigger signal φrtd from AND circuit 170f maintains the inactive state of L level, while the second write trigger signal φwtd from AND circuit 190g is in the active state of H level for a predetermined period.
Thereby, write / input control circuit 200 is activated,
Perform a predetermined operation. The read / output control circuit 180
Maintain inactive state. Therefore, in accordance with the auto-refresh command applied in clock cycle 6, initialization of the data write path is executed in parallel with the auto-refresh operation.

In clock cycle 10, when an auto-refresh command is applied again, auto-refresh operation instructing signal φar is activated at an H level for a predetermined period. In response to the activation of refresh operation instruction signal φar, refresh control circuit 20 updates the count value of refresh address counter 6 again, and accordingly, least significant refresh address bit / RFA0 rises again from L level to H level.

In parallel with the refresh operation performed under the control of refresh control circuit 20, in clock cycle 11, delayed auto refresh operation instructing signal φard from delay circuit 205 rises to the H level for a predetermined period. This delayed auto refresh operation instructing signal φa
In response to activation of rd, read trigger signal φrt and write trigger signal φwt rise to H level for a predetermined period. The least significant refresh address bit / RFA0 is H
Level, the second signal from the AND circuit 170f
Read trigger signal φrtd attains an active state of H level for a predetermined period, while second write trigger signal φwtd from AND circuit 190g maintains an inactive state of L level. Therefore, in accordance with the auto-refresh command applied in clock cycle 10, read / read is performed.
Output control circuit 180 is activated to perform operations required for data reading and output. On the other hand, write / input control circuit 20
0 maintains the inactive state.

Each time the auto refresh command is applied, the data read path and the data write path are alternately initialized. Thus, compared to the configuration in which the data read path and the data write path are initialized simultaneously, the current consumption can be reduced and the data read paths and the data write paths can be initialized.

The auto-refresh command for initialization is applied eight times or more while the reset period defining signal RAR is at the H level.

In clock cycle 13, a mode register set command is applied, reset period defining signal RAR falls to L level, and inverted reset period defining signal / RAR rises to H level. With these series of operations, the initialization sequence is completed.

In the normal cycle, inverted refresh period defining signal / RAR is at H level, and OR circuit 17
The output signals of 0e and 190f are fixed at the H level. Therefore, AND circuits 170f and 190g always receive an H level signal at one of their inputs and operate as buffers. Further, tri-state inverter buffers 170b and 190b enter an output high impedance state, while tri-state inverter buffers 170c and 190c enter an operating state. Therefore, in the normal cycle, read operation instruction signal φrea
The read trigger signal φrt and the second read trigger signal φrtd are activated according to d, while the write trigger signal φwt and the second write trigger signal φwtd are activated according to the write operation instruction signal φwrite.
Therefore, one of read / output control circuit 180 and write / input control circuit 200 is activated according to the read command and the write command.

In the sixth embodiment shown in FIG. 16, read / output control circuit 180 may be configured such that its output control circuit is inactive during the reset period. Form 3).

As described above, according to the sixth embodiment of the present invention, the configuration is such that the read control circuit and the write control circuit are activated alternately each time the auto refresh command is applied in the initialization sequence. The write and read control circuits and the data read and data write related circuit portions can be reliably initialized without increasing the current.

[Structure of Synchronous Semiconductor Memory Device with Bank Structure] FIG. 18 schematically shows an entire structure of a synchronous semiconductor memory device according to the seventh to tenth embodiments described below. In FIG. 18, the synchronous semiconductor memory device includes two banks AB # A and BB # B. These banks A B {A and B B}
B can be driven to an active state and an inactive state independently of each other. When one bank is accessed, the other bank is precharged and activated again, and when the access to one bank is completed, access is subsequently made to the selected bank. By alternately accessing the bank AB # A and the bank BB # B, continuous access can be performed without waiting time even when switching pages (when selecting another word line).

FIG. 19 schematically shows an entire structure of a synchronous semiconductor memory device having a bank structure. In FIG. 19, the synchronous semiconductor memory device decodes a memory array 301a having a plurality of memory cells arranged in a matrix as a bank A, and an internal row address signal RA given at the time of activation, and specifies an address. Row selection circuit 302a for driving the word line corresponding to the selected row to the selected state, and column selection circuit 303a for decoding internal column address signal CA applied at the time of activation and selecting the addressed column of memory array 301a. And a write / read circuit 304a for writing / reading data in a column selected by column select circuit 303a in synchronization with an internal clock signal when activated.

Row select circuit 302a includes a row decode circuit for decoding a given internal row address signal, and a word line drive circuit for driving a corresponding word line to a selected state according to the output of the row decode circuit. Column selection circuit 3
03a includes a column decode circuit for decoding applied internal column address signal CA to generate a column select signal, and a column select circuit 303a for connecting a corresponding column to an internal data bus according to the column select signal. Write / read circuit 3
04a includes a preamplifier for amplifying internal read data, a write drive circuit for driving an internal data line according to internal write data, and a transfer gate for transferring internal read / write data.

In this synchronous semiconductor memory device, a memory array 301b having a plurality of memory cells arranged in rows and columns as a bank B, and a row address signal given at the time of activation are decoded and addressed. Selection circuit 302 for driving the word line corresponding to the selected row to the selected state
b and internal column address signal CA applied at the time of activation.
And a column selecting circuit 303b for selecting an addressed column of the memory array 301b.
It includes a write / read circuit 304b for exchanging data with the column selected by column select circuit 303b. The configurations of the memory array 301b, row selection circuit 302b, column selection circuit 303b, and write / read circuit 304b are as follows.
The configuration is the same as that of memory array 301a, row selection circuit 302a, column selection circuit 303a, and write / read circuit 304a provided for bank A.

An input / output circuit 305 for exchanging data with the outside is provided commonly to bank A and bank B.

The synchronous semiconductor memory device further includes, as a peripheral circuit, a refresh address counter 30 for generating a refresh address during an auto refresh operation.
6 and an address input buffer 3 which takes in an externally applied address signal Ad in synchronization with an internal clock signal intCLK and generates an internal row and column address signal.
07, a multiplexer 3 for selecting one of the refresh address from the refresh address counter 306 and the address given from the address input buffer 307.
08, and externally applied control signals / RAS, / CA
Input buffer 312 for taking in S and / WE in synchronization with internal clock signal intCLK;
The command decoder 314 determines the state of the internal control signal supplied from the controller 12 and generates an operation mode designating signal in accordance with the determination result, and is activated in response to an auto-refresh operation instruction signal φar from the command decoder 314. A refresh control circuit 320 for performing operation control necessary for refresh is included.

The internal row address signal and internal column address signal generated from address input buffer 308 each include a bank address bit designating a bank. Similarly, the refresh address counter 306 also
The least significant bit is used as a bank address. Multiplexer 310 outputs internal row address signal RA and bank address bit BA. Internal column address signal CA generated from address input buffer 308 is applied to column selection circuits 303a and 303b.

For these banks A and B,
A bank A control circuit 315a and a bank B control circuit 315b for performing necessary control operations on banks A and B according to address signal BA and an operation mode instruction signal from command decoder 314, respectively, are provided. When bit BA designates bank A, bank A control circuit 315a generates a required control signal according to an operation mode designating signal from command decoder 314. Bank B control circuit 315b is activated when bank address bit BA designates bank B, and generates a required control signal in accordance with an operation mode designating signal from command decoder 314. In the operation of input / output circuit 305, input / output operation instruction signals to bank A control circuit 315a and bank B control circuit 315b are both used (OR is taken).

Upon receiving the refresh operation instruction signal, refresh control circuit 320 updates the refresh address value of refresh address counter 306 and causes multiplexer 308 to select the refresh address from refresh address counter 306. Refresh control circuit 320 generates a refresh activation signal for determining a refresh operation period in accordance with auto-refresh operation instruction signal φar. The refresh address includes a bank address bit. Therefore, in the bank specified by the bank address, the refresh operation is performed in accordance with refresh activation signal RFACT from refresh control circuit 320.

Bank A and bank B include a row-related control circuit and a column-related control circuit driven independently of each other. These configurations are the same as those shown in FIGS. 28 and 30.

The synchronous semiconductor memory device further includes a mode register 322 for storing burst length data and CA latency data, and the like,
And a mode register control circuit 324 for controlling data writing to data register 314 in accordance with a mode register set operation instruction signal from command decoder 314. The mode register 322 and the mode register control circuit 324 are provided commonly to the banks A and B. Further, there is provided a reset period defining signal generation circuit 325 which is activated in response to power-on and inactivated in response to a mode register setting signal from command decoder 314. The bank A control circuit 315a and the bank D control circuit 315b are provided with an internal clock generation circuit described later.

FIG. 20 is a diagram schematically showing a configuration of a trigger signal generation section in bank A control circuit 315a and bank B control circuit 315b. Referring to FIG. 20, operation mode instruction signal φ applied from command decoder 314
A representative configuration of a portion for generating operation mode trigger signal φCDA for bank A and operation mode trigger signal φCDB for bank B according to CD is shown. FIG.
, Operation mode trigger signal φC for bank A
DA is generated from an AND circuit 330a receiving an operation mode trigger signal φCD from the command decoder and the bank address bit BA. The operation mode trigger signal φCDB for bank B is the same as operation mode trigger signal φCD from command decoder and bank address bit / B.
A is output from an AND circuit 330b receiving A. Bank address bits BA and / BA are complementary address bits. When one is at H level, the other is at L level.
Level. Therefore, the operation mode trigger signal is generated only for the bank specified by the bank address.

[Seventh Embodiment] FIG. 21 schematically shows a structure of an internal clock generation unit. In FIG. 21, an internal clock generation unit includes a clock enable circuit 340a for generating a clock enable signal CLKENA which is activated when an activation signal ACTA or a reset period definition signal RAR is activated, an activation signal ACTB or a reset period definition. When signal RAR is activated, a clock enable circuit 340b for driving clock enable signal CLKENB to an active state and an internal clock intC
AND circuit 342a receiving LK and clock enable signal CLKENA, and internal clock signal intCLK
Receiving clock and clock enable signal CLKENB
And a D circuit 342b.

Internal clock signal φCLKA for bank A is output from AND circuit 342a, and AND circuit 3
42b, the internal clock signal φC for bank B
LKB is output. The activation signal ACTA specifies the array activation of the bank A, and the activation signal ACTB specifies the array activation for the bank B. The configuration of clock enable circuits 340a and 340b is the same as the configuration shown in FIG. In the corresponding bank, an active command is applied, and the corresponding clock enable signal C
LKENA or CLKENB is driven to an active state,
When the operation of the column related circuit in the corresponding bank is completed, that is, when a period defined by the burst length and the latency has elapsed after the read command or the write command is applied, the clock enable signal is driven to the inactive state. Thus, internal clock signal φCLKA or φCLKB is applied only to the bank being accessed. The reset period defining signal RAR is commonly supplied to the clock enable circuits 340a and 340b, and in the initialization sequence during the reset period,
An internal clock signal is commonly applied to these banks A and B, so that the burst length counter and the latency counter (shifter) are reliably set to the initial state.

In the normal operation cycle, the clock enable signal is activated when an active command is applied, but the clock enable signal is inactive when an auto refresh command is applied (signal ACT is inactive).

As described above, according to the seventh embodiment of the present invention, even in a synchronous semiconductor memory device having a bank configuration, internal clock signals φCLKA and φCLKB are generated during the reset period. By operating the burst length counter and the latency counter provided for each bank in the bank configuration, the initial state can be reliably set.

[Eighth Embodiment] FIG. 22A shows a structure of a main part of a synchronous semiconductor memory device according to an eighth embodiment of the present invention. FIG. 22A shows a structure for a read control unit for each of bank A and bank B.

In FIG. 22A, the synchronous semiconductor memory device includes a delay circuit 350 for delaying an auto-refresh operation instruction signal φar provided from a command decoder (not shown) (see FIG. 19) for a predetermined time, Selector 352 that receives delayed auto refresh operation instruction signal φard and read operation instruction signal φread, selects one of them according to reset period defining signals RAR and / RAR, and generates global read trigger signal φrt.
And refresh bank address bit / RFBA which is the least significant bit of refresh address counter 306
And a selector 354 for receiving one of the received address bits according to reset period defining signals RAR and / RAR, and an output signal of selector 354 and global read trigger signal φrt. Circuit 356
And the read trigger signal φrta from the AND circuit 356
And a bank A read control circuit 358 for generating a signal for controlling the read operation for bank A according to Bank A read control circuit 358 controls the operation of the column selection circuit and the read circuit provided for bank A in synchronization with internal clock signal φCLK.

This synchronous semiconductor memory device further includes an inverter 3 receiving refresh bank address bit / RFBA from refresh address counter 306.
60a, an inverter 360b receiving a bank address bit / BA provided from an address input buffer,
A selector 362 for selecting one of the output signals of inverters 360a and 360b according to reset period defining signals RAR and / RAR, an AND circuit 364 receiving an output signal of selector 362 and global read trigger signal φrt, and an output from AND circuit 364 Bank B read control circuit 365 for performing control necessary for data read operation on bank B according to read trigger signal φrtb.
including. This bank B read control circuit 366
, And the operation of a readout circuit provided in response to the internal clock signal φCLKB.

Each of bank A read control circuit 358 and bank B read control circuit 366 includes a burst length defining circuit and a shifter for adjusting the CAS latency period. The operation of the output circuit may be controlled according to the output of the shifter provided for bank A and bank B. Further, the operation of the output circuit may be stopped during the reset period. That is, the output circuit may be configured to stop the operation when the reset period defining signal RAR is activated.

The selectors 352, 354 and 362 have the same structure, and in FIG.
Only the configuration of FIG. Selector 352 is activated when reset period defining signals RAR and / RAR are activated, tristate inverter buffer TV1 for inverting and transmitting delayed auto refresh operation instructing signal φard from delay circuit 350, and reset period defining signal. RAR and / RAR are activated when deactivated,
Read operation instruction signal φr applied from command decoder
tri-state inverter buffer TV2 and tri-state inverter buffer TV for inverting and transmitting read
1 and an inverter IV receiving an output signal of TV2. Global read trigger signal φ from inverter IV
rt is output.

The selector 354 selects the refresh bank address bit / RFBA from the refresh address counter 306 when the reset period defining signals RAR and / RAR are activated. When the reset period defining signals RAR and / RAR are inactive, the selector 354 selects the external bank. Select the bank address bit / BA given by The selector 362 is also
Similarly, when the reset period defining signals RAR and / RAR are activated, the refresh bank address bit applied via inverter 360a is selected, and when reset period defining signals RAR and / RAR are inactivated, inverter 3 is activated.
Select the bank address bits provided via 60b. Next, the operation of the circuit shown in FIG.
This will be described with reference to the timing chart shown in FIG.

In cycle 0 of external clock signal extCLK, power is turned on, and the voltage level of reset period defining signal RAR rises and is fixed at H level. The inversion reset period defining signal / RAR maintains the L level.

In clock cycle 2, an auto-refresh command is applied for initialization, and auto-refresh operation instructing signal φar attains an active state of H level for a predetermined period. Delayed auto-refresh operation instruction signal φard from delay circuit 350 is activated in clock cycle 3. In the selector 352, the tri-state inverter buffer TV1 is operating,
Tri-state inverter buffer TV2 is in an output high impedance state. Therefore, global write trigger signal φrt rises to H level for a prescribed period according to delayed auto refresh operation instructing signal φard. The refresh address counter 306 has its refresh address set to an initial value under the control of the refresh control circuit 320 according to the auto-refresh command given in clock cycle 2, and the refresh bank address becomes 0 (L level). Therefore, the inverted refresh address bit / RFBA has risen to the H level.

The selector 354 selects and outputs the refresh bank address bit / RFBA during this reset period. Similarly, the selector 362 selects and outputs the refresh bank address bit provided from the inverter 360a during this reset period. Since refresh bank address bit / RFBA is at H level, AND circuit 356 drives read trigger signal φrta to H level for a predetermined period according to global read trigger signal φrt. On the other hand, the AND circuit 364
Indicates that the refresh bank address bit supplied from the selector 362 is at the L level and the read trigger signal φ
Keep rtb inactive. As a result, bank A
Read control circuit 358 performs a control operation required at the time of data read in accordance with read trigger signal φrta. Accordingly, the circuits included in the data read path for bank A operate, and not only the initialization of bank A read control circuit 358 but also the data read path of bank A are initialized.

In clock cycle 6, an auto refresh command is applied again. According to the auto refresh command in clock cycle 6,
Refresh bank address bit / RFBA from refresh address counter 306 falls to L level (under the control of refresh control circuit 320). After the auto refresh operation instruction signal φar is given,
When the predetermined time has elapsed, in clock cycle 7,
Delayed auto-refresh operation instruction signal φard from delay circuit 350 is at the H level for a predetermined period. Accordingly, global read trigger signal φrt is driven to H level for a predetermined period. Now, the refresh operation bit / RFBA is L
Level, the AND circuit 356 selects the selector 354
Receives an L-level signal at one of its inputs, and maintains read trigger signal φrta in an inactive state. On the other hand, A
ND circuit 364 has a refresh address bit applied from selector 362 at H level, and activates read trigger signal φrtb to H level for a predetermined period according to global read trigger signal φrt. Thereby, bank B read control circuit 366 is activated, and performs the control required for the data read operation of bank B. Accordingly, not only the initialization of the bank B read control circuit 366 but also the initialization of the internal circuit provided on the data read path of the bank B is performed.

Then, in clock cycle 10 again, an auto-refresh command is applied, and auto-refresh operation instructing signal φar rises to the H level for a predetermined period. In response to activation of auto-refresh operation instruction signal φar, refresh address counter 306
Is updated under the control of the refresh control circuit 320,
It rises from L level to H level. Clock cycle 1
In 1, the delayed auto refresh operation instructing signal φard from the delay circuit 350 rises to the H level for a predetermined period, and the global read trigger signal φrt rises to the H level for a predetermined period. In clock cycle 11, refresh bank address bit / RFBA is at H level, and AND circuit 356 is enabled,
AND circuit 360 is disabled. Therefore, AND circuit 356 generates (activates) read trigger signal φrt according to global read trigger signal φrt, and applies the signal to bank A read control circuit 358. Read trigger signal φrtb for bank B maintains the inactive L level. Thereby, the data read operation is performed again in bank A, and the initialization of bank A read control circuit 358 and the initialization operation in the read path of bank A are performed.

Thereafter, this auto-refresh command is applied the required number of times, and bank A and bank B alternately activate their read control circuits. During the reset period, clock signals φCLKA and φCLKB are applied to external clock signal φe in accordance with reset period defining signal RAR.
It is generated in synchronization with xtCLK. Therefore, bank A read control circuit 358 and bank B read control circuit 366 are connected to clock signals φCLKA and φCL
The operation can be reliably performed according to the KB and the internal state can be set to the initial state.

After the cycle of applying the auto refresh command is completed and the internal state is set to the initial state, the burst length data and CAS of the synchronous semiconductor memory device are set.
A mode register set command for storing latency data is provided in clock cycle 14. According to this mode register set command, reset period defining signal RAR falls to L level, while
The inversion reset period defining signal / RAR rises to the H level (see the first embodiment). Selector 352 activates tristate inverter buffer TV2, activates tristate inverter buffer TV1 to an output high impedance state, selects read operation instruction signal φread given from the command decoder, and outputs global read trigger signal φrt. The selector 354 is
Similarly, externally applied bank address bit / BA
Is given to the AND circuit 356. Selector 362
Selects bank address bit / BA applied via inverter 360b and applies it to AND circuit 364. Therefore, in the normal operation cycle, the data read operation is performed on the addressed bank in accordance with the bank address provided simultaneously with the read command. In addition, during the auto refresh operation, no internal clock is generated, and the column circuit does not operate.

In the structure shown in FIG. 22A, when the operation of the output circuit is stopped, as in the third embodiment, the same structure as in the third embodiment is used for each bank. be able to.

As described above, according to the eighth embodiment of the present invention, in a synchronous semiconductor memory device having a bank configuration,
Since the internal clock is generated during the reset period and the read control circuits are operated alternately, initialization of these read control circuits and initialization of the data read path are performed without increasing current consumption compared to the case where the read control circuits are operated simultaneously. Settings can be made reliably.

[Ninth Embodiment] FIG. 23A shows a structure of a main part of a synchronous semiconductor memory device according to a ninth embodiment of the present invention. In FIG. 23A, bank A
And a structure for a portion for writing data to bank B are shown. In FIG. 23A, the synchronous semiconductor memory device has an auto-refresh operation instruction signal φ
Selector 370 which receives delayed auto-refresh operation instruction signal φard and write operation instruction signal φwrite from delay circuit 350 which delays ar by a predetermined time, and selects and outputs one of these signals in accordance with reset period defining signals RAR and / RAR. And the least significant address bit from refresh address counter 306, that is, refresh bank address bit / RFBA and externally applied bank address bit / BA, and one of these address bits is selected according to reset period defining signals RAR and / RAR. Selector 372 for output
And an AND circuit 374 receiving an output signal from selector 372 and a global write trigger signal φwt provided from selector 370, and performs a control necessary for a data write operation to bank A according to a write trigger signal φwta output from AND circuit 374. A bank A write control circuit 376 is included. This bank A circuit control circuit 376 operates in synchronization with internal clock signal φCLKA. This bank A write control circuit 376 is included in the bank A control circuit.

This synchronous semiconductor memory device further includes an inverter 3 receiving refresh bank address bit / RFBA from refresh address counter 306.
78a and a bank address bit /
An inverter 378b receiving BA, and an inverter 378
a selector 380 receiving output signals of signals a and 378b and selecting and outputting one of these signals in accordance with reset period defining signals RAR and / RAR;
An AND circuit 382 receiving the global write trigger signal φwt output from the selector 380 and the output signal of the selector 380;
A bank B write control circuit 384 for performing control necessary for a data write operation to bank B according to a write trigger signal φwb from ND circuit 382 is included. Bank B write control circuit 384 is included in the bank B control circuit and operates in synchronization with internal clock signal φCLKB. Each of bank A write control circuit 376 and bank B write control circuit 380 includes a burst length counter and a CAS latency counter.

Selectors 370, 372 and 380 have the same configuration, and in FIG.
0 is representatively shown. Selector 370 is activated when reset period defining signals RAR and / RAR are activated, tristate inverter buffer TV3 for inverting and transmitting delayed auto refresh operation instruction signal φard output from delay circuit 350, and reset period Tri-state inverter buffer TV4, which is set to an operative state when prescribed signals RAR and / RAR are inactivated and inverts and transmits write operation instruction signal φwrite applied from the command decoder, and output signals of tri-state inverter buffers TV3 and TV4 Receiving inverter IV1. Global write trigger signal φwt is output from inverter IV1.

Refresh control circuit 320 and refresh address counter 306 are the same as those described in the above embodiment. Next, FIG.
The operation of the circuit illustrated in FIG. 23A is described with reference to a timing chart illustrated in FIG.

The power is turned on in clock cycle 0 of external clock signal extCLK, and the voltage level of reset period defining signal RAR rises to H level. The inversion reset period defining signal / RAR maintains the L level.

In clock cycle 2, an auto-refresh command is applied for initialization, and auto-refresh operation instructing signal φar is activated at H level for a predetermined period. The refresh control circuit 320 is activated according to the activation of the auto-refresh operation instruction signal φar, the count value of the refresh address counter 306 is reset to the initial value, and the refresh bank address bit / RFBA is set to the H level (“1”). You. Next, delay response refresh operation instructing signal φard from delay circuit 350 is activated in clock cycle 3. In selector 370, since reset period defining signal RAR is at the H level, tristate inverter buffer TV3 is in an active state, and delayed auto refresh operation instructing signal φard is output.
Activates the global write trigger signal φwt
Is generated from the selector 370.

Selectors 372 and 380 each select a refresh bank address bit.
Now, the refresh bank address bit / RFBA is H
Level, the AND circuit 374 is enabled, A
The ND circuit 382 is in a disabled state. Therefore, a write trigger signal φwta is generated from AND circuit 374 in accordance with global write trigger signal φwt, and applied to bank A write control circuit 376. The bank A write control circuit 376 outputs the write trigger signal φw
, the internal clock signal φCLKA
In synchronization with the data writing. Thereby, initialization of bank A write control circuit 376 and initialization of the data write circuit system of bank A are performed.

In clock cycle 6, an auto-refresh command is applied again, and auto-refresh operation instructing signal φar is at H level for a predetermined period. In accordance with the generation of auto-refresh operation instruction signal φar, the address value of refresh address counter 306 is updated by 1, and bank address bit / RFBA changes to L level. In clock cycle 7, delay circuit 35
0, delayed auto refresh operation instructing signal φard
Is activated to an H level, selector 370 is accordingly operated.
Generates a global write trigger signal φwt (output in an active state).

Now, refresh bank address bit /
Since RFBA is at L level, the output signal of selector 372 is at L level and the output signal of selector 380 is at H level. Therefore, write trigger signal φwtb from AND circuit 382 is activated for a prescribed period according to global write trigger signal φwt, and bank B write control circuit 384 is activated. Bank B write control circuit 384 performs a control operation required for data writing in synchronization with internal clock signal φCLKB. Thereby, initialization of bank B write control circuit 384 and initialization of the data write path of bank B are performed.

In clock cycle 10, an auto refresh command is applied, and an auto refresh operation instructing signal φar is generated. The refresh control circuit 320 updates the value of the refresh address bit / RFBA from the refresh address counter 306 according to the auto-refresh operation instruction signal φar. Thereby, the refresh address bit / RFB
A rises from the L level to the H level, and accordingly, AND circuit 374 is enabled and AND circuit 382 is disabled. Therefore, when delayed auto-refresh operation instruction signal φard is generated from delay circuit 350 in clock cycle 11 in accordance with auto-refresh operation instruction signal φar, write trigger signal φwta is activated according to global write trigger signal φwt, and bank A write control circuit 37
6 is activated. Again, this bank A write control circuit 37
6 and the data write path of bank A are initialized.

Thereafter, while the auto-refresh command is applied and initialization is performed a required number of times, each time the auto-refresh command is applied, bank A write control circuit 376 and bank B write control circuit 384 are alternately activated. And the data write paths of the corresponding banks are initialized.

When the initialization operation by the auto-refresh command is completed, a mode register set command is applied in clock cycle 14, and necessary data is set in the mode register. According to this mode register set command, reset period defining signal RA
R falls to the L level, and the inverted reset period defining signal /
RAR rises to H level. Thereby, the selector 3
70 is set to select write operation instruction signal φwrite, selector 372 is set to select external bank address bit / BA, and selector 380 also sets external bank address bit / BA. It is set to the state to select. Therefore, in a subsequent operation cycle, bank A write control circuit 376 and bank B write control circuit 384 are activated according to an external write command and a bank address bit.

As described above, according to the ninth embodiment of the present invention, the write control circuit is alternately activated every time an auto-refresh command is given in the initialization sequence. Thus, the portions related to data writing of banks A and B can be reliably initialized.

[Tenth Embodiment] FIG. 24 schematically shows a structure of a main portion of a synchronous semiconductor memory device according to a tenth embodiment of the present invention. The configuration according to the tenth embodiment shown in FIG. 24 corresponds to the configuration shown in FIGS.
Embodiment 8 and Embodiment 9 shown in FIG.
Are combined. Therefore, corresponding parts are denoted by the same reference numerals.

In FIG. 24, refresh address counter 306 has a refresh address bit / RFA
0 // RFAn is output. The refresh address bit / RFA0 is the least significant bit.

This synchronous semiconductor memory device has an OR circuit 400 receiving inverted reset period defining signal / RAR and refresh address bit / RAF1 of refresh address counter 306, an output signal of OR circuit 400 and a global read trigger from selector 352. Signal φrt
AND circuit 402 receiving refresh address bit / RFA1, and an output signal of inverter 403 and inverted reset period defining signal / RA
An OR circuit 404 receiving R and an AND circuit 405 receiving an output signal of the OR circuit 404 and a global write trigger signal φwt supplied via a selector 370 are included.

The selectors 352 and 370 are the same as those in FIG.
2 (A) and the configuration shown in FIG.
According to reset period defining signals RAR and / RAR,
Delayed auto refresh operation instruction signal φard, read operation instruction signal φread, or write operation instruction signal φw
write selectively.

Read trigger signal φrtd from AND circuit 402 is applied to one input of each of AND circuits 356 and 364. The AND circuit 356 receives the output signal of the selector 354 at the other input, and
Receives the output signal of the selector 362 at the other input. Bank read trigger signal φrtda output from AND circuit 356 is applied to bank A read control circuit 358. Bank read trigger signal φrtdb output from AND circuit 364 is applied to bank B read control circuit 360. The bank A read control circuit 358 and the bank B read control circuit 366 have the same configuration as that shown in FIG. Therefore, this bank A read control circuit 3
58 and the bank B read control circuit 366,
Includes burst length counter and latency counter.
Bank A read control circuit 358 and bank B read control circuit 366 may be configured to control the operation of the output circuit and stop the operation of the output circuit during the reset period, respectively. May be configured to operate.

Selector 354 receives least significant refresh address bit / RFA0 and external bank address bit / BA. This least significant refresh address bit / RFA0 corresponds to the refresh bank address bit / RFBA in the eighth and ninth embodiments. Selector 354 selects and outputs refresh address bit / RFA0 when reset period defining signals RAR and / RAR are activated.

Selector 362 receives refresh address bit / RFA0 and bank address bit / BA via inverters 360a and 360b, respectively. During the reset period (when reset period defining signals RAR and / RAR are active), selector 362
The refresh address bit provided from inverter 360a is selected and output. The selector 372 is
Refresh address bit / RFA0 and bank address bit / BA are received. During the reset period, the selector 372 controls the refresh address bit / RFA0
Select and output. The selector 380 is connected to the inverter 3
Refresh address bit / RFA0 and bank address bit /
Receive BA. During the reset period, the selector 380 selects and outputs the output signal of the inverter 378a.

In the configuration shown in FIG. 24, selector 354 and selector 372 may be shared by one selector instead of being provided separately, and selectors 362 and 380 are also configured by one selector. (One selector is commonly used for bank A and bank B).

Refresh address bits / RFA0 to / RFAn from refresh address counter 306
Are supplied to the row selection circuit via the multiplexer during the auto refresh operation. Next, the operation of the circuit shown in FIG. 24 will be described with reference to the timing chart shown in FIG.

In clock cycle 0 of external clock signal extCLK, power is turned on. By this power-on, the voltage level of reset period defining signal RAR rises and is set to H level. The inversion reset period defining signal / RAR maintains the L level. In this state, selectors 352 and 370 are set to a state of selecting delayed auto-refresh operation instruction signal φard from delay circuit 350. Selectors 354, 362, 3
72 and 380 are set to select the applied refresh address bit, respectively.

In clock cycle 2, an auto refresh command is applied, and auto refresh operation instructing signal φar is at H level for a predetermined period. In accordance with the auto-refresh operation instruction signal φar, the refresh control circuit 320
06 refresh address is set to an initial value. Thereby, refresh address bits / RFA1 and / RFA0 are each set to H level.

In clock cycle 3, delay circuit 3
50, the delayed auto-refresh operation instruction signal φar
d rises to H level, and global read trigger signal φrt and global write trigger signal φwt rise to H level via selectors 352 and 370 accordingly. Refresh address bit / RFA1 is at H level, so that the output signal of OR circuit 400 is at H level.
The output signal of the OR circuit 404 is at L level.
Therefore, AND circuit 402 generates read trigger signal φrtd according to global read trigger signal φrt. AND circuit 405 is in a disabled state, and write trigger signal φwtd maintains an inactive state. Further, refresh address bit / RFA0 is at H level, AND circuit 356 is enabled,
AND circuit 364 is disabled, read trigger signal φrtda for bank A is activated according to read trigger signal φrtd, and bank A read control circuit 358 is activated. Thereby, the initialization of the read control circuit of bank A and the initialization of the data read path of bank A are performed.

In clock cycle 6, an auto refresh command is applied, the count value of refresh address counter 306 is updated by 1, and refresh address bit / RFA0 falls from H level to L level. On the other hand, refresh address bit / RFA1
Maintain the H level. Therefore, in this state, according to delayed auto-refresh operation instruction signal φard activated in clock cycle 3,
AND circuit 402 generates a read trigger signal φrtd, and then AND circuit 364 generates a read trigger signal φrdtb for bank B to apply to bank B read control circuit 366, and bank B read control circuit 366 is activated.

When an auto refresh command is applied in clock cycle 10, the count value of refresh address counter 306 is incremented by one under the control of refresh control circuit 320. Therefore, refresh address bit / RFA1 falls from H level to L level, while refresh address bit / RFA1 falls.
RFA0 rises from the L level to the H level. In this state, the output signal of OR circuit 400 is at L level,
The output signal of the R circuit 404 becomes H level, the AND circuit 404 is enabled, and the AND circuit 402 is disabled. Therefore, global write trigger signal φw is in accordance with delayed auto-refresh operation instruction signal φard activated in clock cycle 11.
is driven to the active state, and the write trigger signal φwtd
Is generated. Read trigger signal φrtd maintains the inactive state.

Since refresh address bit / RFA0 is at the H level, AND circuit 374 is enabled and AND circuit 382 is disabled. Therefore, write trigger signal φwtda for bank A is activated according to write trigger signal φwtd, and bank A write control circuit 376 operates.

In clock cycle 14, when an auto refresh command is applied, refresh control circuit 320 increments the count value of refresh address counter 306 by one according to auto refresh operation instruction signal φar. Therefore, refresh address bit / RFA0 falls from H level to L level, while refresh address bit / RFA1 maintains L level. Therefore, this time, the AND circuit 3
82 is enabled and the AND circuit 374 is disabled. Therefore, delayed auto refresh operation instructing signal φar generated in clock cycle 3
d, a global write trigger signal φwt is generated, and then a write trigger signal φwtd is generated.
A write trigger signal φwtdb for bank B is activated, and bank B write control circuit 384 is activated to perform control necessary for a write operation. Thereby, bank B
Initialization of write control circuit 384 and data write circuit of bank B are performed.

When an auto refresh command is applied again in clock cycle 18, the count value of refresh address counter 306 is incremented by one according to auto refresh operation instruction signal φar. By the increment of the count value, the refresh address bit /
RFA0 and / RFA1 rise to H level, and are in the same state as in clock cycle 2. Therefore,
In clock cycle 19, even if delayed auto-refresh operation instructing signal φard from delay circuit 350 is activated and global read trigger signal φrt and global write trigger signal φwt are generated, AND
Circuit 405 is disabled, and read trigger signal φrtd is activated. Refresh address bit / RFA0 is at H level, and read trigger signal φrtda for bank A is again generated from AND circuit 356, and bank A refresh control circuit 358 is activated. Thereafter, this operation is repeated every time the auto refresh command is given.

In clock cycle 22, a mode register set command is applied, and reset period defining signal RAR falls to L level, while inverted reset period defining signal / RAR rises to H level. This allows
Selectors 352 and 370 are set to select read operation instruction signal φread and write operation instruction signal φwrite, respectively. Selectors 354, 362, 3
72 and 380 are set to select externally applied bank address bits, respectively. Therefore, in a subsequent operation cycle, activation / inactivation of the read control circuit and the write control circuit is performed in accordance with an external command and a bank address bit.

In the above description, each control circuit is activated in the order of the read operation for bank A, the read operation for bank B, the write operation for bank A, and the write operation for bank B. However, this order is arbitrary, and the refresh address bit / R
By switching the connection between FA0 and / RFA1,
The read control circuit and the write control circuit for each of bank A and bank B can be activated in an arbitrary sequence. These read control circuit and write control circuit need only operate in the initialization sequence, and their activation order is arbitrary.

A structure in which the read control circuit and the write control circuit are simultaneously activated when one bank is designated may be used.

As described above, the tenth embodiment of the present invention is described.
According to the above, each time the auto refresh command is given in the initialization sequence, the bank A and the
Are performed in a predetermined sequence, so that a circuit portion related to data reading and a circuit portion related to data writing can be reliably set to an initial state in an initialization sequence. .

[Other Configurations] Embodiments 7 to 10
In the description, the number of banks is set to two.
However, the number of banks is arbitrary, and when a plurality of bank address bits are used, the read / write operation is activated in a predetermined sequence for three or more banks by using a bank decoder. can do.

In the above description, a synchronous DRAM has been described as an example of a synchronous semiconductor memory device. Any synchronous semiconductor memory device capable of performing a refresh mode operation in which a refresh address is internally generated in accordance with an external refresh instruction and performing data input / output in synchronization with an external clock signal may be used. The invention is applicable.

[0219]

As described above, according to the present invention, in the initialization operation after the power is turned on, the internal clock is generated during the normal operation cycle, the generation of which is stopped in the standby state. Therefore, at the time of the initialization operation, the circuit portion operating according to the internal clock can be reliably operated and set to the initial state.

Further, in the initialization operation, when the refresh operation mode is used, the circuit part whose operation is prohibited in the normal cycle is also configured to operate in the initial sequence. It can be initialized to a predetermined state.

That is, according to the invention of claim 1,
While the refresh period defining signal is activated in response to the activation of the power-on detection signal and inactivated in response to the operation mode instruction signal, the internal clock applied to the internal circuit is supplied to the external clock. Since it is configured to be generated in synchronization with the signal, the circuit that receives this internal clock signal can be clocked during the initialization operation after power-on, and the circuit part that receives this clock is reliably initialized. Can be performed.

According to the second aspect of the present invention, the read circuit for reading the data of the selected memory cell and the read control circuit for controlling the operation of the read circuit can be reliably set to the initial state after the power is turned on. it can.

According to the third aspect of the present invention, the internal circuit further includes an output circuit for outputting data to the outside and output control means for controlling the operation of the output circuit.
During the initialization operation, these output circuits and output control circuits can be reliably initialized.

According to the invention of claim 4, the internal circuit comprises a write circuit for writing data to a selected memory cell, and write control means for controlling the operation of the write circuit. At the time of the initialization operation after the power is turned on, the circuit portions related to the data writing can be reliably set to the initial state.

According to the invention of claim 5, the internal circuit further includes a write circuit for writing data to the selected memory cell, and a control circuit for controlling the operation of the write circuit. During the initialization operation, the circuit portion related to data reading and the circuit portion related to data writing can be reliably set to the initial state.

According to the invention of claim 6, the data write circuit and the data read circuit are alternately activated in a predetermined sequence during the initialization operation. Compared with this, the circuit portion related to data writing and the circuit portion related to data reading can be reliably initialized without increasing current consumption.

According to the invention of claim 7, the read circuit and the read control circuit provided for each of the plurality of banks are sequentially activated in a predetermined sequence. Also, it is possible to reliably set a circuit portion related to data reading to an initial state after power is turned on.

According to the invention of claim 8, since the data reading means and the writing means provided for each of the plurality of banks are sequentially activated in a predetermined sequence,
Even in a synchronous semiconductor memory device having a bank configuration, a circuit portion related to data writing can be reliably set to an initial state after power-on.

According to the ninth aspect of the present invention, the read circuit and the write circuit provided for each of the plurality of banks and the read control circuit and the write control circuit are initialized in a predetermined sequence at the time of initialization after power-on. Since they are sequentially activated, even in a synchronous semiconductor memory device having a bank configuration,
It is possible to surely initialize the circuit portion related to data reading and data writing.

According to the tenth aspect, an internal clock is generated by activation of an activation signal for driving an array to a selected state in a normal operation cycle, and an access instruction for instructing data writing / reading is applied. Thereafter, when this access instruction is given, the period of the product of the number of data continuously accessed and the number of cycles of the external clock signal, and the number of clock cycles from when the access instruction is given until valid data is output to the outside After the lapse of the sum of the latencies, the internal clock is generated only during the period required for the circuit using this internal clock signal to operate because the array activating signal is inactive when the array activating signal is inactive.
Current consumption during normal operation can be reduced.

[Brief description of the drawings]

FIG. 1 shows a structure of a main part of a synchronous semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing an operation of the reset period defining signal generation circuit shown in FIG.

FIG. 3 is a timing chart showing an operation of an internal clock signal generator shown in FIG. 1;

4A is a diagram showing a configuration of a power-on detection circuit shown in FIG. 1, and FIG. 4B is a diagram showing an operation waveform thereof.

FIG. 5 is a diagram schematically showing a configuration of a modification of the first embodiment of the present invention.

6 is a waveform chart showing an operation of the circuit shown in FIG.

FIG. 7 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing the operation of the circuit shown in FIG. 7;

FIG. 9 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a third embodiment of the present invention.

10 is a diagram schematically showing an example of a configuration of a read control circuit and an output control circuit shown in FIG. 9;

FIG. 11 is a timing chart showing the operation of the circuits shown in FIGS. 9 and 10;

FIG. 12 schematically shows a configuration of a modification of the third embodiment of the present invention.

FIG. 13 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 14 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 15 is a timing chart showing an operation of the circuit shown in FIG. 14;

FIG. 16 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 17 is a timing chart showing the operation of the circuit shown in FIG. 16;

FIG. 18 schematically shows a structure of a synchronous semiconductor memory device used in the seventh and subsequent embodiments of the present invention.

FIG. 19 schematically shows an entire structure of a synchronous semiconductor memory device according to the present invention.

20 is a diagram schematically showing a configuration of an input stage of a bank control circuit in the synchronous semiconductor memory device shown in FIG. 19;

FIG. 21 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 22A schematically shows a structure of a main part of a synchronous semiconductor memory device according to an eighth embodiment of the present invention,
FIG. 2B is a timing chart showing the operation of the circuit shown in FIG.

FIG. 23A is a diagram schematically showing a configuration of a main part of a synchronous semiconductor memory device according to a ninth embodiment of the present invention, and FIG. 23B is a timing chart showing the operation of the circuit shown in FIG. It is a chart figure.

FIG. 24 schematically shows a structure of a main part of a synchronous semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 25 is a timing chart showing the operation of the circuit shown in FIG. 24;

FIG. 26 is a diagram schematically showing an overall configuration of a conventional synchronous semiconductor memory device.

FIG. 27 is a timing chart showing an operation of the synchronous semiconductor memory device shown in FIG. 26;

FIG. 28 is a drawing schematically showing an example of the configuration of a row-related control circuit and a refresh control circuit of a conventional synchronous semiconductor memory device.

FIG. 29 is a timing chart showing the operation of the circuit shown in FIG. 28;

30 is a diagram schematically showing a configuration of a column related control circuit shown in FIG. 26;

FIG. 31 is a timing chart showing the operation of the circuit shown in FIG. 30;

FIG. 32 schematically shows a structure of a conventional internal clock generation circuit.

FIG. 33 is a timing chart showing the operation of the circuit shown in FIG. 32;

FIG. 34 is a diagram schematically showing a configuration of a mode register control unit of a conventional synchronous semiconductor memory device.

FIG. 35 is a diagram showing an initialization sequence of a conventional synchronous semiconductor memory device.

[Explanation of symbols]

100 power supply node, 102 power-on detection circuit, 10
4 Reset period definition signal generation circuit, 130 internal clock generation circuit, 140 internal clock generation circuit, 170
Read trigger signal generating circuit, 180 read / output control circuit, 180a read control circuit, 180b output control circuit, 181 burst length defining circuit, 181a burst length counter, 182 shifter, 190 write trigger signal generating circuit, 200 write / input control Circuit, B @ A bank A, B @ B bank B, 303a, 303b column selection circuit, 304a, 304b write / read circuit, 305
I / O circuit, 306 refresh address counter,
314 command decoder, 315a bank A control circuit, 315b bank B control circuit, 322 mode register, 325 reset period defining signal generation circuit, 376
Bank A write control circuit, 384 Bank B write control circuit, 1 memory array, 3 column selection circuit, 4 write / read circuit, 5 input / output circuit, 14 command decoder, 1
6 row control circuit, 18 column control circuit, 20 refresh control circuit.

Claims (10)

[Claims] A synchronous circuit having a plurality of memory cells and inputting / outputting data to / from a selected memory cell of the plurality of memory cells in synchronization with an externally applied clock signal having a predetermined time width. A power-on detection circuit coupled to a power supply node to which an external power supply voltage is supplied, detecting power-on of the external power supply voltage according to a voltage level of the power supply node, and generating a power-on detection signal. Means, activated in response to activation of the power-on detection signal;
Reset period defining means for generating a reset period defining signal inactivated in response to a predetermined operation mode instruction signal; an internal circuit operating in synchronization with an internal clock signal when activated; Internal clock generating means for synchronously generating the internal clock signal, wherein the internal clock generating means generates the internal clock signal when the reset period defining signal is activated, and the internal circuit is inactive. A synchronous semiconductor memory device including means for stopping generation of the internal clock signal when the reset period defining signal is inactivated. 2. An internal circuit comprising: a read circuit for reading data of a selected memory cell of the plurality of memory cells when activated; a refresh instruction for instructing refresh of data of the plurality of memory cells; and the resetting 2. The synchronous semiconductor memory device according to claim 1, further comprising: read control means for activating said read circuit in response to an active state of a period defining signal. 3. An internal circuit, comprising: an output circuit for outputting data from the readout circuit to the outside of the device when activated; 3. The synchronous semiconductor memory device according to claim 2, further comprising output control means for activating the output circuit. 4. A write circuit for writing data to a selected memory cell of the plurality of memory cells when activated, a refresh instruction for instructing a refresh of data of the plurality of memory cells. 2. The synchronous semiconductor memory device according to claim 1, further comprising: write control means for activating said write circuit in response to an active state of said reset period defining signal. 5. The internal circuit further comprises: a write circuit for writing data to a selected one of the plurality of memory cells when activated, an active state of the refresh instruction and the reset period defining signal. 4. The synchronous semiconductor memory device according to claim 2, further comprising: write control means for activating said write circuit in response to the above. 6. A write circuit for writing data to a selected one of the plurality of memory cells when activated, the internal circuit comprising: a write circuit for writing data to the selected one of the plurality of memory cells when activated; A read circuit for reading the data of the memory cell, and a write instruction for refreshing the data of the plurality of memory cells and an active state of the reset period defining signal. 2. The synchronous semiconductor memory device according to claim 1, further comprising a write / read control means for activating the circuits alternately in a predetermined sequence. 7. The plurality of memory cells are divided into a plurality of memory banks that are activated and deactivated independently of each other, and the internal circuit is provided corresponding to each of the plurality of memory banks. A plurality of read circuits for reading data from a selected memory cell in a corresponding memory bank, responding to a refresh instruction for instructing data refresh of the plurality of memory cells, and an active state of the reset period defining signal. 2. The synchronous semiconductor memory device according to claim 1, further comprising read control means for sequentially activating read circuits of said plurality of memory banks in a predetermined sequence. 8. The plurality of memory cells are divided into a plurality of memory banks driven to an active state and an inactive means independently of each other, and the internal circuit is provided corresponding to each of the plurality of memory banks. A plurality of write circuits for writing data to a selected memory cell of a memory bank corresponding to an activated state, a refresh instruction for instructing data refresh of the plurality of memory cells, and an active state of the reset period defining signal 2. The synchronous semiconductor memory device according to claim 1, further comprising: write control means for sequentially activating write circuits of said plurality of memory banks in a predetermined sequence in response to the above. 9. The plurality of memory cells are divided into a plurality of memory banks driven to an active state and an inactive state independently of each other, and the internal circuit is provided corresponding to each of the plurality of memory banks. A plurality of read circuits for reading data of a memory cell selected in the memory bank corresponding to the activation, and a plurality of read circuits provided corresponding to each of the plurality of memory banks, the memory selected in the memory bank corresponding to the activation A plurality of write circuits for writing data to cells; and a plurality of read circuits provided corresponding to each of the plurality of memory banks, for reading data from a selected memory cell of the corresponding memory bank when activated A plurality of memory banks in response to a refresh instruction for instructing data refresh of the plurality of memory cells and an active state of the reset period defining signal. Including a read / write control means for sequentially activating the write circuit and read circuit in a predetermined sequence, a synchronous semiconductor memory device according to claim 1, wherein. 10. The internal clock generating means, when the reset period defining signal is inactivated, activates an internal activating signal for defining a period during which a selected one of the plurality of memory cells is in a selected state. When an access instruction instructing data writing / reading is applied in response to the internal activation signal, when the internal activation signal is inactivated, the burst length indicating the number of data to be continuously read and the external A period given by the product of the cycle of the clock signal, and inactivation after a period of the sum of the latencies indicating the required number of clock cycles from the application of the access instruction to the output of valid data to the outside. The synchronous semiconductor memory device according to claim 1, wherein: