JPH10240676A - Data transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of a CPU, to reduce the burden of software and to reduce hardware by providing a pointing register only for peripheral function, which stores the content of the operation result of a peripheral function part in a memory and designates a storage destination address. SOLUTION: A data transfer circuit 10 is provided with a latch circuit 11 latching signals EA-EC showing the operation termination of the respective peripheral function parts, an operation result register 12 storing the operation result of the peripheral function parts and the private pointing register 13 constituted of private registers PRA-PRC showing destinations (addresses) at the time of storing the content of the operation result register 12 in a RAM. A selector 14 selects the private pointing register 13 corresponding to the peripheral function part latched in accordance with the generated operation termination signals EA-EC. A selector 15 selects the operation result register 12 corresponding to the peripheral function part latched in accordance with the generated operation termination signals EA-EC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer circuit, and more particularly, to a central processing unit (CPU) and its peripheral I / O.
The present invention relates to a data transfer circuit applicable to a microcomputer system or a microprocessor system including a memory for storing functions and data.

[0002]

2. Description of the Related Art A microcomputer incorporates various peripheral I / Os as interfaces for connecting peripheral devices for data input / output. The microcomputer transfers various data between the CPU, its peripheral I / O function, and the memory by using a data transfer circuit.

Conventional data transfer circuits of this type include:
For example, there is one disclosed in JP-A-3-21687. As shown in FIG. 5, the data transfer circuit 100
Central processing unit (CPU) 101, interrupt control unit 10
2, a program memory 103, a data memory 105 including a stack area 104, a peripheral section 106, a data bus 1
07 etc.

[0004] First, when a certain process is completed in the peripheral unit 106, the peripheral unit 106 outputs an interrupt signal to the interrupt control unit 102. The interrupt control unit 102
If the interrupt request signal is permitted, the CPU 101 outputs an interrupt request signal to the CPU 101. When the CPU 101 receives the interrupt request signal, the CPU 101 suspends the execution of the program, and stores the current program address, operation register,
Saves various registers such as control registers and status registers, and executes the interrupt processing program.

[0005]

However, in such a conventional data transfer circuit 100, the peripheral portion 1
When the operation result of step 06 is transferred by interrupt processing, it is necessary to save and restore a program address indicating the current execution state of the main program and various registers before and after execution of the interrupt processing program. In addition, since the main program is stopped during the execution of the interrupt processing, if the transfer of the operation result of the peripheral part frequently occurs along with the increase of the peripheral part, the CPU efficiency decreases.
In particular, when processing a large amount of data continuously in the peripheral area,
In order to save the preprocessing result, it is necessary to cope with the problem by increasing the execution of the interrupt processing program and providing a plurality of save registers, which causes a problem that the load on software and hardware increases.

The present invention has been made in view of the above-mentioned problems of the prior art, and a first object of the present invention is to improve CPU efficiency and reduce software load. It is another object of the present invention to provide a new and improved data transfer circuit capable of reducing hardware.

A second object of the present invention is to improve the CPU efficiency by processing the data transfer on hardware, thereby reducing the frequency of interruption of the execution of the main program due to interruption or the like. A new and improved data transfer circuit is provided.

Further, a third object of the present invention is to provide a new and improved access control program which can access a memory of a peripheral device on hardware, thereby omitting an access control program and reducing a load on software. A data transfer circuit is provided.

A fourth object of the present invention is to save hardware resources by enabling processing with a minimum number of registers even when a large amount of data is frequently exchanged between a peripheral device and a memory. And a new and improved data transfer circuit.

A fifth object of the present invention is to further improve the CPU efficiency by enabling one continuous operation between the peripheral device and the memory by one interrupt processing.
It is also possible to process large amounts of data efficiently.
A new and improved data transfer circuit is provided.

[0011]

According to a first aspect of the present invention, there is provided a memory for storing data and a memory for storing the data according to a first aspect of the present invention. A data transfer circuit for executing data transfer with a peripheral function unit for processing a peripheral function of a processor to be accessed, dedicated to a peripheral function for designating a storage destination address for storing the contents of operation results of the peripheral function unit in a memory A data transfer circuit including a pointing register is provided.

Further, the data transfer circuit may include an operation result register for temporarily storing an operation result of the peripheral function unit.

The operation result register may be configured such that data is written to an address of the memory specified by the peripheral function dedicated pointing register in response to an operation end signal of the peripheral function unit. Is also good.

The pointing register dedicated to the peripheral function and the operation result register may be provided by the number corresponding to at least the peripheral function unit, for example, as in the invention according to claim 4.

Further, the data transfer circuit includes a pointing device for exclusive use of a peripheral function and a selector for selecting an operation result register corresponding to a peripheral function section for performing data transfer to a memory. You may.

Further, in the data transfer circuit, for example, the peripheral function dedicated end pointing for designating the end address of the storage destination address for storing the contents of the operation result of the peripheral function unit in the memory as in the invention according to claim 6 A register may be provided.

According to a second aspect of the present invention, as in the seventh aspect of the present invention, a peripheral function unit for processing a peripheral function of a memory for storing data and a processor for accessing the memory. A data transfer circuit for performing data transfer between the data transfer circuit and a peripheral function dedicated pointing register for designating a head address of output data stored in a memory. You.

Further, the data transfer circuit may be provided with an output register for temporarily holding output data designated and read out by the peripheral function dedicated pointing register as in the invention of claim 8. Good.

Further, the output register may be provided with a buffer register for temporarily storing output data to be stored next time, for example, as in the ninth aspect of the present invention.

Further, the output register may be, for example,
As in the invention described in No. 0, data may be read from an address of a memory specified by a peripheral function dedicated pointing register in response to an operation end signal of the peripheral function unit.

In the buffer register, data may be read from an address of a memory specified by the peripheral function dedicated pointing register in response to an operation end signal of the peripheral function unit. .

Further, the pointing register and the output register dedicated to the peripheral function may be provided by the number corresponding to at least the peripheral function section.

Further, the data transfer circuit is provided with a selector for selecting a pointing register dedicated to a peripheral function and an output register corresponding to a peripheral function unit for transferring data to a memory, as in the invention according to a thirteenth aspect. Is also good.

Further, the data transfer circuit may be provided with a peripheral function dedicated end pointing register for designating an end address of the peripheral function dedicated pointing register.

Further, the data transfer circuit may be provided with a comparator for comparing the output of the peripheral function dedicated pointing register with the output of the peripheral function dedicated end pointing register. When the output of the peripheral function dedicated pointing register and the output of the peripheral function dedicated end register match by the comparator, an interrupt request signal may be output to the processor.

The pointing register dedicated to the peripheral function may be a counter circuit, for example, as in the invention of claim 16, and incremented or decremented each time the operation of the pointing register dedicated to the peripheral function is completed. Good.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a data transfer circuit according to the present invention will be described in detail with reference to the accompanying drawings.

The data transfer circuit 10 (30, 30
40) is a ROM for storing data as shown in FIG.
1 and a RAM 2 such as a RAM 2, a processor 4 such as a CPU for performing an access operation to the memory 3, and peripheral function units 5A, 5B and 5 for processing peripheral functions of the processor 4.
, And are disposed between the peripheral function units 5A, 5B, 5C,... And the memory 3 to efficiently process data transfer.

FIG. 2 is a configuration diagram of the data transfer circuit according to the first embodiment of the present invention. The data transfer circuit 10 shown in FIG. 2 is an example applied to a device assuming that there are three peripheral function units (A, B, C).

In FIG. 2, a data transfer circuit 10 includes a latch circuit 11 for latching signals EA, EB, and EC indicating the end of operation of each peripheral function unit, and an operation result register 12 for storing an operation result of each peripheral function unit. And operation result register 1
2 is provided with a dedicated pointing register 13 consisting of dedicated registers PRA, PRB, and PRC indicating the storage destination (address) when storing the contents of the RAM in the RAM. Further, the selector 14 selects the dedicated pointing register 13 corresponding to the peripheral function unit latched according to the generated operation end signals EA, EB, EC.
5 is an operation result register 1 corresponding to the peripheral function unit latched in response to the generated operation end signals EA, EB, EC.
2 is selected. The output signal of the latch circuit 11 is output to the selector 19 via the OR gate 16. The selector 17 selects a RAM address bus or an output signal of the selector 14 by a RAM access request signal, and the selector 18 selects a data bus or an output signal of the selector 15 by a RAM access request signal. , Selector 19, RAM write signal or OR gate 16 according to RAM access request signal.
Is selected. The output of the selector 17 is connected to the address terminal (A) of the RAM 20, the output of the selector 18 is connected to the data input terminal (O), and the output of the selector 19 is connected to the write signal terminal WR. It is connected.

The dedicated pointing register 13 is
This is a pointing register dedicated to peripheral functions and is composed of a counter circuit.

The operation of the data transfer circuit 10 configured as described above will be described below.

Now, consider a case where the peripheral function A operates continuously.

When the peripheral function A completes the first operation,
The operation result is stored in the operation result register RA, the operation end signal EA is output, and the second operation is started. When the signal EA indicating the end of the operation of the peripheral function is held in the latch circuit 11, the dedicated pointing register PRA and the operation result register RA of the peripheral function A are selected by the selectors 14 and 15, respectively, and the OR gate 16 is set. In this dedicated pointing register PRA, the starting address when the contents of the operation result register RA of the peripheral function A are stored in the RAM 20 is set in advance.

If there is no request for RAM access from the main program, the selectors 17, 18, and 19 select the dedicated pointing register PRA for the address of the RAM 20 and the operation result register RA for the write data, respectively. Is RAM2
Written to 0.

When the writing is completed, the latch circuit 11 is reset, the dedicated pointing register PRA is incremented, and waits for the next operation.

The above-described operation is to transfer the contents of the operation result register 12 to the RAM 20, and is not to transfer by software by an interrupt operation, but to perform all by hardware. As described above, according to the data transfer circuit 10 according to the first embodiment, since all RAM accesses are performed by hardware, a microcontroller having a peripheral function that frequently updates an operation result or a very large number of peripheral functions is used. When applied to a computer and a microprocessor, the following effects can be obtained.

That is, the main program can be executed without being interrupted by an interrupt or the like.
PU efficiency is improved.

The operation result of the peripheral device is simply stored in a RAM.
This eliminates the need for a program to be transferred to the PC, thus reducing the load on the software.

In general, when the operation result of a peripheral device is frequently updated, it is necessary to have a large number of operation result registers accordingly. Can be reduced.

Further, the operation result of the peripheral device is simply expressed as RA
The transfer to M can be realized without executing the interrupt operation, so that it is not necessary to save the current program address and various registers in the stack area as in the conventional case.
Highly important processing can be performed at high speed and with priority.

FIG. 3 is a configuration diagram of a data transfer circuit according to the second embodiment of the present invention. The data transfer circuit shown in FIG. 3 is an example applied to a device assuming that there are three peripheral function units (A, B, C). In the description of the data transfer circuit according to the present embodiment, the same components as those of the data transfer circuit shown in FIG. 1 will be denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 3, this data transfer circuit 30
Is an output register 31 composed of output registers ORA, ORB, and ORC for storing output data to a peripheral function unit (not shown), and a buffer register B for storing the next output data.
A buffer register 33 including RA, BRB, and BRC is provided. The latch circuit 11 latches signals EA, EB, and EC indicating the end of the operation of the peripheral function unit.
The AND gate 32 loads the output from the buffer register 33 into the output register 31 according to the output of the latch circuit 11. The selector 34 selects the buffer register 33 based on the output of the latch circuit 11. In addition, the dedicated pointing register 13
Indicates the head (address) of the ROM / RAM 38 in which the next output data is stored in the case of the present embodiment, and the selector 14 supplies the generated operation end signals EA, EB, and EC to the output end signals EA, EB, and EC. The corresponding dedicated pointing register 13 is selected. Then, the selector 35
Is ROM / R by the ROM / RAM access request signal
The selector 36 selects the AM address bus or the output of the selector 14. The selector 36 selects the output data of the ROM / RAM to the data bus or the output to the selector 34 according to the ROM / RAM access request signal. The selector 37 receives a ROM / RAM read request signal or a latch circuit 11 according to a ROM / RAM access request signal.
Selects the output signal of the OR gate 16 to which the output signal of (1) is input. The output of the selector 35 is connected to the address terminal (A) of the ROM / RAM 38, the input of the selector 36 is connected to the data output terminal (O), and its output enable (OE: Output Ena) is provided.
ble) Terminals OE are connected to the outputs of the selectors 37, respectively. Output enable (OE: Output)
Enable) terminal * OE.

The dedicated pointing register 13 is
In the present embodiment, the R that stores the next next output data
A peripheral function dedicated pointing register that specifies the head (address) of the OM / RAM 38, and is configured by a counter circuit.

The operation of the data transfer circuit 30 configured as described above will be described below.

Now, consider a case where the peripheral function A continuously outputs data.

When the peripheral function A outputs the data of the output register ORA in the first data output operation, it outputs an operation end signal EA.

When the signal EA indicating the end of the operation of the peripheral function is held in the latch circuit 11, the dedicated pointing register PRA of the peripheral function A is selected by the selector 14, and the OR gate 16 is set. The contents are loaded into the output register ORA through the AND gate 32.

At this time, the buffer register BRA stores the output data of the second time, and the dedicated pointing register PRA sets in advance the head address of the ROM / RAM 38 storing the output data of the third time and thereafter. deep.

Here, the ROM / R is read from the main program.
If there is no request for AM access, data having the dedicated pointing register PRA as an address is stored in the ROM / RAM.
The data is output from the selector 38, passes through the selector 36, and is written to the corresponding buffer register 33 (here, BRA).

When the writing is completed, the latch circuit 11 is reset, the dedicated pointing register PRA is incremented, and waits for the next operation.

The above-described operation is to transfer the contents of the ROM / RAM 38 to the output register 31, and is not to transfer by software by an interrupt operation, but to perform all by hardware. As described above, in the data transfer circuit 30 according to the second embodiment, since all the RAM accesses are performed by hardware, a microcontroller having a peripheral function for continuously outputting a large amount of data or a very large number of peripheral functions is provided. When applied to a computer and a microprocessor, the following effects can be obtained.

That is, since the main program can be executed without interruption by interruption or the like,
U efficiency is improved.

When transferring a large amount of data, it is not necessary to set output data every time one data is transferred, so that the load on software can be reduced.

Further, when transferring a large amount of data, it is not necessary to have many buffer registers, so that hardware resources can be reduced.

FIG. 4 is a configuration diagram showing a part of a data transfer circuit according to a third embodiment of the present invention. This embodiment is an example in which the present invention is applied to a device assuming a case where there are three peripheral function units (A, B, and C). FIG. 4 shows a configuration in which the dedicated pointing register shown in FIGS. A function-specific end pointing register and a matching circuit are added.

Referring to FIG.
Is a dedicated pointing register (PRA) that specifies the storage destination (address) when storing the contents of the operation result register 12 in the RAM 20 or specifies the head (address) of the ROM / RAM 38 that stores successive output data. ,
PRB, PRC) 41-43, ROM or RAM
Peripheral function dedicated end pointing registers (EPRA, EPRB, EPR) for storing the access end address
C) 44 to 46 and a dedicated pointing register (PR
A, PRB, PRC) 41 to 43 and peripheral function dedicated end pointing registers (EPRA, EPRB, EPR)
C) Comparing with 44 to 46, and matching circuits (COMP) 47 to 49 (comparing means) for outputting an interrupt request signal when there is a match.

The operation of the peripheral function dedicated register 40 of the data transfer circuit configured as described above will be described below.

Now, consider a case where the peripheral function A operates continuously.

The output of the dedicated pointing register (PRA) 41 of the peripheral function A and the output of the peripheral function dedicated pointing register (EPRA) 44 for storing the end address of the ROM or RAM access correspond to the matching circuit (C
OMP) 47. Here, the dedicated pointing register (PRA) 41 has a counter circuit configuration and is incremented each time the operation is completed.

When the dedicated pointing register (PRA) 41 is incremented by the continuous operation and matches the output of the peripheral function dedicated end pointing register (EPRA) 44, the matching circuit (COMP) 47 outputs an interrupt request signal to the processor.

As described above, the data transfer circuit according to the third embodiment includes a dedicated pointing register (P
RA, PRB, PRC) 41 to 43 have peripheral function dedicated end pointing registers (EPRA, EPRB, EP).
RC) 44-46 and match circuit (COMP) 47-49
, The required RO for peripheral functions
Access beyond the memory area of M or RAM can be prevented.

Further, in the present embodiment, an interrupt is not generated every time the operation of the peripheral function is completed, but is generated at the end of one continuous operation. Updating of output data according to the second embodiment can be performed by one interrupt process for one continuous operation. Therefore, the CPU efficiency is high and a large amount of data can be handled as one or a plurality of bundles.

Although the preferred embodiment of the data transfer circuit according to the present invention has been described with reference to the accompanying drawings, the present invention is not limited to this example. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong.

For example, in the data transfer circuit according to each of the above-described embodiments, the peripheral function dedicated pointing register is incremented after the end of the operation. This is the case when the peripheral function dedicated pointing register has an up counter circuit configuration. Yes, it may be constituted by a down counter circuit. In this case, the peripheral function dedicated pointing register is decremented after the operation of the peripheral function ends.

In each of the above embodiments, a DRAM, for example, can be used as the memory. However, any memory that performs data access can be used, and an EEPROM, a flash memory, or the like can be used for storing programs. It is. Further, any processor that can execute the program may be used.

Further, it goes without saying that the number of registers, selectors and gate circuits constituting the data transfer circuit, the type of connection, and the like are not limited to the above-described embodiment.

[0068]

As described above, in the data transfer circuit according to the present invention, the peripheral function dedicated pointing register for specifying the storage destination address for storing the contents of the operation result of the peripheral function unit in the memory, and the peripheral function dedicated pointing Since the configuration is provided with the peripheral function exclusive pointing register that specifies the end address of the register, the CPU efficiency can be improved, the load on software can be reduced, and the hardware can be reduced. In addition, even when the operation result of the peripheral device is simply transferred to the RAM, the operation result can be realized without executing the interrupt operation.
There is no need to save the current program address and various registers in the stack area, and high-priority processing can be performed at high speed and with priority.

In the data transfer circuit according to the present invention,
A peripheral function dedicated pointing register that specifies the start address of the memory where the next output data is stored, and a peripheral function dedicated end pointing register that specifies the end address of the peripheral function dedicated pointing register. When transferring data, it is not necessary to set output data every time one data is transferred, so that the load on software can be reduced. Also, since there is no need to have many buffer registers, hardware can be reduced.

Further, the data transfer circuit according to the present invention includes comparing means for comparing the output of the peripheral function dedicated pointing register and the output of the peripheral function exclusive end register, and the comparing means uses the output of the peripheral function dedicated pointing register and the peripheral function exclusive end. When the output of the pointing register matches, an interrupt request signal is output to the processor.
It can be performed by one interrupt processing for one continuous operation.
The PU efficiency can be further increased, and a larger amount of data can be handled as one or more bundles.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a schematic configuration of a data transfer circuit according to the present invention.

FIG. 2 is a schematic circuit diagram illustrating a configuration of a data transfer circuit according to a first embodiment to which the present invention is applied;

FIG. 3 is a schematic circuit diagram illustrating a configuration of a data transfer circuit according to a second embodiment to which the present invention is applied;

FIG. 4 is a schematic block diagram illustrating a configuration of a dedicated pointing register of a data transfer circuit according to a third embodiment to which the present invention is applied.

FIG. 5 is a schematic block diagram showing a configuration of a conventional data transfer circuit.

[Explanation of symbols]

10, 30 Data transfer circuit 11, 16 Latch circuit 12 Operation result register 13, 40, 41, 42, 43 Dedicated pointing register 14, 15, 17, 18, 34, 35, 36, 37
Selector 20 RAM (memory) 31 Output register 32 AND gate 33 Buffer register 38 ROM / ROM (memory) 44, 45, 46 Peripheral function dedicated end pointing register 47, 48, 49 Matching circuit (comparing means)

Claims (16)

[Claims] 1. A data transfer circuit for executing data transfer between a memory for storing data and a peripheral function unit for processing a peripheral function of a processor accessing the memory, wherein the operation of the peripheral function unit is performed. A data transfer circuit comprising a pointing register dedicated to a peripheral function for designating a storage destination address for storing the contents of a result in the memory. 2. The data transfer circuit according to claim 1, further comprising an operation result register for temporarily holding an operation result of said peripheral function unit. 3. The operation result register according to claim 2, wherein the operation result register writes data to an address of the memory specified by the peripheral function dedicated pointing register in response to an operation end signal of the peripheral function unit. Data transfer circuit. 4. The data transfer circuit according to claim 2, wherein the peripheral function dedicated pointing register and the operation result registers are provided in at least as many numbers as the number of the peripheral function units. 5. The semiconductor device according to claim 2, further comprising a selector for selecting the pointing register dedicated to the peripheral function and the operation result register corresponding to the peripheral function unit that transfers data to the memory. Or the data transfer circuit according to 4. 6. A peripheral function dedicated end pointing register for designating an end address of a storage destination address for storing contents of an operation result of the peripheral function unit in the memory. 6. The data transfer circuit according to any one of 2, 3, 4, and 5. 7. A data transfer circuit for executing data transfer between a memory for storing data and a peripheral function unit for processing a peripheral function of a processor accessing the memory, wherein the data transfer circuit stores data in the memory. A data transfer circuit, comprising: a pointing register dedicated to a peripheral function that specifies a start address of output data. 8. The data transfer circuit according to claim 7, further comprising an output register for temporarily holding the output data designated and read by the peripheral function dedicated pointing register. . 9. The data transfer circuit according to claim 8, wherein said output register includes a buffer register for temporarily holding output data to be held next time. 10. The output register according to claim 8, wherein the output register reads data from an address of the memory specified by the peripheral function dedicated pointing register in response to an operation end signal of the peripheral function unit. Data transfer circuit. 11. The buffer register according to claim 9, wherein the buffer register reads data from an address of the memory designated by the peripheral function dedicated pointing register in response to an operation end signal of the peripheral function unit. Data transfer circuit. 12. The peripheral function dedicated pointing register and the output registers are provided at least as many as the number corresponding to the peripheral function unit. Data transfer circuit. 13. The device according to claim 8, further comprising a selector for selecting the pointing register dedicated to the peripheral function and the output register corresponding to the peripheral function unit that transfers data to the memory. 10,11
13. The data transfer circuit according to any one of claims 12 14. A peripheral function dedicated pointing register for designating an end address of the peripheral function dedicated pointing register.
14. The data transfer circuit according to claim 8, 9, 10, 11, 12, or 13. 15. A comparator for comparing the output of the peripheral function exclusive pointing register with the output of the peripheral function exclusive end pointing register, wherein the comparator outputs the output of the peripheral function exclusive pointing register and the output of the peripheral function exclusive end pointing register. 15. The data transfer circuit according to claim 6, wherein an interrupt request signal is output to the processor when the values match. 16. The peripheral function dedicated pointing register is a counter circuit, and is incremented or decremented each time the operation of the peripheral function dedicated pointing register is completed. 4,5,6,7,8,9,10,11,1
16. The data transfer circuit according to any one of 2, 13, 14, and 15.