JPH10240566A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the position of a cable fault in its early stage and to improve the availability by the reduction of a fault analysis man-hour and a time and the reduction of MTTR(mean time to repair) by providing a means which records the passage confirmation of data on a network for communication between processors so as to specify a fault position in the network. SOLUTION: A terminal 108 for maintenance which is informed of abnormality of the inter-PE network from an arbitrary PE 101 during normal operation indicates a one-to-one communication with its PE to respective PE's through Etherenet 110. Each PE sends a packet to the PE. The maintenance terminal 108 after receiving a report on packet transmission completion from each PE checks whether or not there is a processor from which no packet arrives or a PE having received a packet with a wrong address. If there is sch a processor or PE, faulty communication path specifying operation is carried out. When an faulty communication path can be specified, the maintenance terminal 108 performs a faulty place specifying process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system for performing parallel processing among a plurality of processors.

[0002]

2. Description of the Related Art In a conventional network for communication between processors, as described in Japanese Patent Application Laid-Open No. 5-81224, there are many discussions relating to failure detection and processing after failure detection. There is no means relating to this, and means for tracing the record of the machine check latch and specifying the fault location is used as in a general computer system. For this reason, failures in communication networks between a large number of processors, in particular, failure locations of cables and connection points between processors often depend on human beings.
Availability has been reduced due to an increase in time and an increase in MTTR (Mean Time To Repair).

Further, in a system in which networks between processors are multiplexed, when a failure occurs in one network, the fault location of the network is identified and repaired at an early stage while the system as a whole is in operation to reduce system performance. In the prior art, it is difficult to specify a failure position when a cable or the like on a network fails, and thus it is difficult to specify a failure position during operation of the system.

[0004]

SUMMARY OF THE INVENTION It is a first object of the present invention to detect a failure in a network between processors, particularly a failure in a cable connecting between processors, at an early stage.
An object of the present invention is to improve the availability by reducing the number of failure analysis steps / time and the MTTR.

A second object of the present invention is to specify a failure position without bringing down the entire system in the event of a failure of a cable or the like.

[0006]

SUMMARY OF THE INVENTION The object of the present invention is to provide a means for specifying a communication path for specifying a failure position by transmitting / receiving data to / from the own processor, a means for transmitting data for passage confirmation to the path, and a means for confirming passage. Means is provided for recording the passage only when the data for use passes.

By the above means, when a failure occurs, each processor is instructed to communicate to its own processor, an approximate failure path is estimated from the position of the unreceivable processor or the erroneously received processor. , Data for passing confirmation can be sent out, and the passing confirmation latch can be traced to specify the fault position.

According to the above means, the number of man-hours for failure analysis can be significantly reduced, and the MTTR can be reduced, and the availability can be improved. Further, in a multiple processor system having a duplicated network, a failure position can be specified without bringing down the system, and a period during which system performance is reduced can be reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
Each processor (PE in the figure) 101 is connected through a network, and can communicate with an arbitrary PE including its own PE.

The network 107 is of a crossbar type, and comprises a three-dimensional Z, Y, X crossbar switch (XB). A plurality of identical crossbar switches Z-XB (102), Y-XB (103), X-
XB (104). Eight communication paths 105 are input to each switch, and the eight communication paths 105 are output to the next switch. Each switch is provided with one passage confirmation latch 106 corresponding to each input / output.

The switching system of this network is a packet switching system, and the data for passage confirmation is also a packet. Hereinafter, the passage confirmation data is referred to as a trace packet.

The PE 101 and the network 107 are connected to a maintenance terminal via an Ethernet 110 and a scan signal 112, respectively. Scan-only signal 11
Reference numeral 1 denotes a control signal, a data signal, and an address signal.

FIG. 2 is a diagram schematically showing a failure analysis procedure. In steps 201 to 204, a fault occurrence path is narrowed down by performing one-to-one communication between the same PEs, and a fault position specifying process is performed in 205 (details are shown in FIG. 3). The control of the failure analysis is performed from the maintenance terminal, and the maintenance terminal uses the Ethernet 110 and the scan signal 111 in FIG.
The failure analysis data is collected from the network switch 101 and the network switches 102 to 104. The failure analysis can be started automatically after the maintenance terminal receives the abnormality report, or can be manually instructed.

FIG. 3 is a diagram showing an outline of a fault location specifying process corresponding to 205 in FIG. The left side of the dotted line shows the processing in the maintenance terminal 108, and the right side shows the processing in the PE 101. The operation of the maintenance terminal 108 is performed by the switches 102 to 10.
4 includes analysis operations such as scan control, instruction to send a trace packet to the PE, specification of a communication path, passage confirmation latch trace, and display of a fault location.

FIG. 4 is a configuration diagram of a packet. PE1
When the maintenance terminal 108 instructs the transmission of the failure position trace packet from the maintenance terminal 108, the third bit of the second word in FIG. 4 is set to "1" to set a flag (J flag) indicating that the packet is a trace packet. Out the packet.

Although not shown in FIG.
104 receives the packet, checks whether the J flag is set, and sets the passage confirmation latch on the input side. The setting of the passage confirmation latch is realized by connecting the 3 bits (J flag 403) of the second word of the packet stored in the reception buffer to the Data terminal of the passage confirmation latch and setting the packet reception event as a clock ON condition. it can. When the trace packet is sent from the switch to the next-stage switch or PE 101, the trace packet is set in the pass confirmation latch on the data output side of the J flag 403 of the transmission buffer.

As a method of setting the passage confirmation latch, there is a method of checking and setting data of a packet by a control program in a switch. In addition to the above-described method, a method using a Set / Reset terminal may be used in hardware. Even if the data is not stored in the transmission / reception buffer, it can be used for setting the passage confirmation latch.

In FIG. 1, a failure analysis operation when the communication path 105 marked with X is broken will be described. First, the maintenance terminal that has received an abnormality report of the network between PEs from any PE 101 during the normal operation, based on FIG.
To the own PE via the Ethernet 110. Each PE sends a packet to its own PE. After receiving the report of the completion of the packet transmission from each PE, the maintenance terminal checks the processor that has not arrived the packet and the presence or absence of the PE that has received the packet with the destination error (202 to 20).
3). If there is a processor for which a packet has not arrived and a PE has received a packet with a destination error, the fault communication path specifying operation of 204 is performed. Although not described here, the communication path through which the packet is transmitted is determined by a certain algorithm and recorded in the routing table. This route is also described in one or two words in the packet as shown in FIG. In the case where there is no processor for which a packet has not arrived and there is no PE which has received a packet with a destination error, that is, when the one-to-one communication has been normally completed, the present invention will not be described. Perform failure analysis by another means.

When the faulty communication path can be specified by 204, the maintenance terminal executes the fault location specifying process of 205. This will be described in detail with reference to FIG. First, all the passage confirmation latches 106 are reset through the scan dedicated signal 111 (301), and the Ethernet 110 instructs the PE on the faulty communication path to transmit a trace packet (302). The PE receiving the instruction sends a trace packet to the corresponding faulty communication path (30).
3). After receiving the trace packet transmission completion report from the PE, the maintenance terminal 108 confirms that the PE has not received the packet, searches the passage confirmation latch on the trace path through the scan dedicated signal 111, and turns on the light. A latch that has not been detected is detected (304 to 305). In the case of the disconnection of FIG. 1, the input side passage confirmation latch of the crossbar switch 104 (X-XB) is not lit, and the output side passage confirmation latch of the source side crossbar switch 103 (Y-XB1) is lit. I have. Therefore, X-XB104 and Y-
It turns out that there is a disconnection between XB103.

As a result, the error location is displayed on the display of the maintenance terminal (305), and the cable is replaced.

[0022]

According to the above-described embodiment, since the fault location can be specified without manually checking the cable for disconnection, the number of man-hours for network fault analysis can be largely eliminated, and the MTTR of the system can be shortened. Even in a multiplexed inter-processor network, it is possible to detect the position of a disconnected cable remotely from a maintenance terminal, so that failure analysis can be performed without physically interfering with a normally operating network, and the system performance degradation period can be reduced. Can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram showing a tracing method at the time of cutting a cable according to an embodiment of the present invention.

FIG. 2 shows an outline of a failure analysis procedure.

FIG. 3 shows a fault location identification procedure.

FIG. 4 shows a packet format of the present embodiment.

[Explanation of symbols]

101: Processor (PE), 102 to 104: Crossbar switch, 105: Communication path, 1
06: passage confirmation latch, 107: network between PEs,
108: maintenance terminal, 109: scan control circuit,
110: Ethernet; 111: Scan-only signal; 201-204: Failure path identification processing by inter-processor communication; 205: Failure point identification processing; 301-303
… Trouble packet transmission processing for fault location identification, 304…
Passage confirmation latch trace processing, 305: Fault location display processing, 401: Packet ID, 402: Routing information field, 403: Trace packet flag.

Claims (2)

[Claims] 1. A computer system in which a plurality of processors perform processing in parallel, characterized in that the computer system includes means for recording a data passage confirmation on a network for identifying a fault location of a plurality of inter-processor communication networks. Computer system. 2. The computer system according to claim 1, further comprising means for designating, on the data to be transmitted to the network, data for passing confirmation, said passing confirmation only when said designated data passes. A computer system characterized by recording on a recording means.