JPH10240558A - Control method for data processor, data processor and electronic beam plotting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of easily analyzing a fault at the time of fault generation by absolute minimum hardwares and simple processings by providing a through mode function. SOLUTION: In these data processors 11-14 provided with two or more cascade-connected arithmetic processing units 27-30 for processing data by a pipeline arithmetic system, the respective arithmetic processing units are provided with a through mode setting means for outputting arithmetic object data as output data as they are from the respective arithmetic processing units without executing an arithmetic processing to the arithmetic object data for which the arithmetic processing is executed inside the respective arithmetic processing units.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a technique effective when applied to an electron beam (EB) drawing apparatus.

[0002]

2. Description of the Related Art For example, a data processing apparatus mainly having a multi-stage pipeline configuration is used for graphic decomposition processing of an electron beam (EB) drawing apparatus. Electron beam (EB) executed by this multi-stage pipeline data processing device
In the graphic decomposition pipeline processing of the drawing apparatus, since the decomposition processing is performed in the pipeline, the amount of data to be processed increases each time the number of pipeline stages is increased.

On the other hand, in the data processing apparatus having the multi-stage pipeline structure, there is a case where some trouble occurs and the data processing is stopped. In a data processing device having a multi-stage pipeline configuration used for a graphic decomposition pipeline process of an electron beam (EB) drawing device, if any fault occurs, the occurrence of the fault can be detected.
B) In the graphic decomposition pipeline processing of the drawing apparatus, the amount of data to be processed increases each time the number of stages of the pipeline is increased, so it was difficult to confirm the failure data itself.

Therefore, conventionally, in the failure analysis of the graphic decomposition pipeline processing in the electron beam (EB) drawing apparatus, (a) the cause of the failure is estimated by simulation or the like based on the input data of the pipeline and the intermediate results. Method (b) A method is adopted in which data processing is executed again from the time when a failure occurs, and the cause of the failure is estimated based on the processing result.

[0005] Incidentally, regarding these techniques, for example,
Published by the Industrial Research Council, "Electronic Materials", 1992 separate volume (p.
109-114).

[0006]

However, in the above method (a), in order to obtain input data at the time of occurrence of a fault or an intermediate result of processing, the processing is performed at the input stage or output stage of each pipeline. It is necessary to provide a memory for storing the results, and to read data stored in this memory. For this reason, when the number of pipeline stages increases, the amount of memory increases, and the scale of hardware increases, which is not practical.

Further, in the graphic decomposition pipeline processing in the electron beam (EB) drawing apparatus, if data processing is executed again from the point of occurrence of a failure, the failure data affects subsequent pipeline processing, and the number of failures increases. I do. For this reason, in the method (b), the original fault data is not easily transmitted in the pipeline and is not stored in the memory.

As described above, in the failure analysis of a data processing device having a multi-stage pipeline configuration used for a graphic decomposition pipeline process of an electron beam (EB) drawing device, as the number of pipeline stages increases, the amount of memory increases. There has been a problem that the size of the hardware increases and the scale of hardware increases, which is not realistic, or that the original failure data is not easily transmitted in the pipeline and stored in the memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a data processing apparatus having a pipeline structure by providing a through mode function to minimize the need. It is an object of the present invention to provide a technology that can easily perform a failure analysis at the time of occurrence of a failure with the above hardware and simple processing.

[0010] Another object of the present invention is to provide a technique capable of easily performing a failure analysis at the time of occurrence of a failure in a graphic decomposition pipeline process in an electron beam (EB) drawing apparatus.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a control method of a data processing device having two or more operation processing units connected in cascade and processing data by a pipeline operation method, when a failure occurs in the data processing device, each of the operation processing The arithmetic processing data is output from each arithmetic processing unit as output data without performing the arithmetic processing on the arithmetic processing data to be subjected to the arithmetic processing in the unit.

[0014] When a data error is detected in the operation target data to be subjected to the operation processing in any one of the operation processing units, the operation target data is left as it is without performing the operation processing on the operation target data. The data is output from each of the arithmetic processing units as output data.

[0015] A failure flag is set for the operation target data in which the data error has been detected.

The data processing device is connected to a higher-level device, and does not perform the arithmetic process on the data to be calculated based on an instruction from the higher-level device, and uses the data to be processed as output data as it is, without processing the data to be processed. Output from the unit.

In a data processing apparatus having two or more operation processing units connected in cascade and processing data by a pipeline operation method, each of the operation processing units includes:
A through-mode setting unit for outputting the operation target data as it is as output data from each of the operation processing units without performing the operation processing on the operation target data to be subjected to the operation processing in each of the operation processing units. .

Each of the arithmetic processing units includes selector means for directly outputting, as output data, input data input to each of the arithmetic processing units or arithmetic data subjected to arithmetic processing in each of the arithmetic processing units, The through mode setting means controls the selector means to cause the arithmetic processing units to output the arithmetic target data as output data without performing arithmetic processing on the arithmetic target data.

Each of the arithmetic processing units has an error detecting means for detecting a data error of the data to be operated, and when an error detecting means of any of the arithmetic processing units detects a data error of the data to be operated, The through mode setting means, based on the error signal output from the error detection means of any one of the arithmetic processing units, performs the arithmetic processing on the arithmetic processing data, and outputs the arithmetic processing data as it is to the output data. Is output from each of the arithmetic processing units.

Each of the arithmetic processing units includes a flag setting means for setting a failure flag on the data to be calculated in which a data error has been detected by the error detecting means.

The data processing apparatus includes a pipe control unit, and the through mode setting means performs the operation without performing the operation processing on the operation target data based on the through mode instruction from the pipe control unit. The target data is output directly from each of the arithmetic processing units as output data.

The data processing device is connected to a host device, and the pipe control section issues a through mode instruction to the through mode setting means based on a through mode command from the host device.

The higher-level device issues a through mode command to the pipe control unit in response to an error signal output from the error detection means of any of the arithmetic processing units.

An analysis memory connected to an output stage of the data processing device, wherein the arithmetic processing is not performed in each of the arithmetic processing units, but is directly output from each of the arithmetic processing units as output data. The target data is stored in the analysis memory.

The analysis memory can be read from a host device.

A plurality of data processing devices are cascaded.

The electron beam lithography system includes the data processing device and executes a graphic decomposition pipeline process.

According to the above means, when a failure occurs in the data processing device having a pipeline configuration, for example, when a data error is detected in the operation target data to be operated in any of the operation processing units, The operation target data is output directly from each operation processing unit as output data without being subjected to the operation processing to the operation target data, and is stored in the analysis memory. Data can be read, and failure analysis at the time of failure occurrence can be easily performed based on the failure data.

According to the above-described means, the failure flag is set in the failure data, so that the failure data can be easily read.

Thus, in the electron beam drawing apparatus, it is possible to easily perform a failure analysis when a failure occurs in the graphic decomposition pipeline processing.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 is a block diagram showing an example of an electron beam (EB) drawing apparatus for executing a graphic decomposition pipeline process using a multi-stage pipeline data processing apparatus according to an embodiment of the present invention. is there.

The electron beam (EB) drawing apparatus shown in FIG. 1 includes a computer control unit 100, a drawing control unit 200, and a drawing unit main body 300. Computer control unit 100
Has a data conversion computer 110 for converting input CAD data into pattern data, a pattern control computer 120 for transferring the pattern data, and controlling the drawing control unit 200 and the drawing unit main body 300. The drawing unit main body 300 includes an electron optical column 310, a stage / loader / sample chamber 320, and a gantry 33 having an exhaust system.
0.

FIG. 2 is a block diagram showing a schematic configuration of the drawing control section 200 shown in FIG.

As shown in the figure, the drawing control unit 200
Digital control system 210 and analog signal processing system 220
And a mechanism control system 230. The digital control system 210 includes an interface circuit 211, a buffer memory 212, a restoration processing unit 213, a disassembly / correction unit 214, a following absolute calibration unit 215, and a drawing procedure control unit 2
16. The analog signal processing system 220
Is composed of a transfer / deflection system 221, a lens system 222, and a signal processing system 223. Further, the mechanism control system 230
Includes a stage control system 231, a loader control system 232,
And an exhaust system 233.

The pattern data transferred from the drawing control computer 120 is input to the buffer memory 212 via the interface circuit 211 of the digital control system 210, and is developed by the restoration processing unit 213 in graphic units. The graphic data developed by the restoration processing unit 213 is decomposed into shot data by the decomposition and alignment correction unit 214.

The disassembly / correction correction unit 214 includes a data processing device mainly having a multi-stage pipeline configuration, and decomposes graphic data into shot data by pipeline processing.

FIG. 3 is a block diagram showing a schematic configuration of a data processing device having a multi-stage pipeline configuration according to an embodiment of the present invention.

The data processing apparatus of the present embodiment performs the entire pipeline processing by four processing pipes (11 to 14).
Run with Each of the processing pipes (11 to 14) includes a pipe control unit (21 to 24).
Analysis memories (16 to 19) are provided at output stages of 1 to 14).
Is provided.

The operation of each processing pipe (11 to 14) is controlled by each pipe control unit (21 to 24), and the control of the entire processing pipe is controlled by the entire pipe operation control unit 20.

The input data 10 to the present pipeline is first input to the processing pipe 11. The data processed by the processing pipe 11 becomes input data to the processing pipe 12 and the analysis memory 16 which are the next processing. In this way, the data processed by the processing pipe is sequentially output as the output data 15 to the analysis memory 19 and the outside of the pipeline. The data stored in the analysis memories (16 to 19) can be read from the higher-level drawing control computer 120.

FIG. 4 is a schematic diagram for explaining a graphic decomposition pipeline process by the data processing device having a multi-stage pipeline configuration according to the present embodiment.

The basic graphic data input from the restoration processing unit 213 to the processing pipe (short-side decomposition pipe) 11 is shown in FIG.
As shown in (a), this is trapezoidal figure data representing a trapezoidal figure. In the processing pipe 11, this trapezoidal figure data is decomposed in the short side direction. That is, in the processing pipe 11, FIG.
As shown in FIG. 4B, the trapezoidal figure shown in FIG. 4A is divided in the short side direction. In FIG. 4B, the restoration processing unit 2
An example is shown in which trapezoidal figure data input from FIG.

In the next processing pipe (oblique decomposition pipe) 12, as shown in FIG. 4C, the graphic data processed by the processing pipe 11 is decomposed into a hypotenuse part and other parts. Therefore, in the example shown in FIG. 4C, 15 pieces of graphic data are output from the processing pipe 12.

Next processing pipe (shot 1 decomposition pipe)
In step 13, as shown in FIG. 4D, the graphic data of the oblique side processed by the processing pipe 12 is divided into shot units. In FIG. 4D, the graphic data of the hypotenuse is
An example is shown in which the shot is divided into three shot units in the short side direction.
Accordingly, 35 pieces of graphic data are output from the processing pipe 13.

In the last processing pipe (shot 2 decomposition pipe) 14, as shown in FIG.
The graphic data other than the oblique side processed in step 2 is divided into shot units. FIG. 4E shows an example in which the graphic data other than the oblique side portion is divided into a total of 45 shot units in the long side direction. Therefore, the processing pipe 14
Will output 75 pieces of graphic data.

As described above, in the graphic decomposition pipeline processing of the electron beam (EB) drawing apparatus executed by the data processing apparatus of the present embodiment, the amount of data to be processed increases each time the number of pipeline stages is increased.

FIG. 5 shows the processing pipes (11 to 1) shown in FIG.
It is a block diagram which shows the internal schematic structure of 4).

As shown in FIG.
Inside 14), the arithmetic processing units (27 to 30)
It has a pipeline configuration connected in multiple stages,
The input data 26 to the processing pipes (11 to 14) is decomposed by the arithmetic processing units (27 to 30) and output to the next processing pipe as processing pipe output data 31. Note that the number of stages of the pipeline of each arithmetic processing unit (27 to 30) is appropriately changed according to the disassembly processing of each processing pipe (11 to 14).

As shown in FIG. 5, the pipe control units (21 to 24) of the processing pipes (11 to 14) include an in-processing pipe operation control unit 32 and a processing pipe mode control unit 3.
3 and an error detecting unit 34 in the processing pipe.

The operations such as the start and end of the operation of each of the arithmetic processing units (27 to 30) are individually controlled by the operation control unit 32 in the processing pipe. The processing pipe mode control unit 33 instructs each of the arithmetic processing units (27 to 30) to issue a normal mode (graphical decomposition pipeline processing) in a normal state, or
A through mode instruction at the time of occurrence of a failure is issued to set the operation mode of each of the arithmetic processing units (27 to 30). The normal mode is a setting at an initial time (immediately after power-on, at a reset) or a normal operation, and executes a normal graphic decomposition pipeline process.

For example, a hardware failure or
When any failure occurs in the pipelined data processing device due to an error in the input data or the like, the error detection unit 34 in the processing pipe detects the failure data, and outputs the data through the operation control unit 32 in the processing pipe. The pipeline processing of each arithmetic processing unit (27 to 30) is forcibly stopped. In addition, the error detection unit 34 in the processing pipe
An error signal is output to the error detection unit 34 in the processing pipe in the pipe control unit of another processing pipe, whereby the pipeline processing of the data processing device is stopped.

Further, the error detection unit 34 in the processing pipe
Also outputs an error signal to the upper-layer drawing procedure controller 216, thereby stopping the operation of the entire drawing controller 200.

Thereafter, the drawing control computer 1 on the upper side
The processing pipe mode control unit 33
Issues a through mode instruction to each of the arithmetic processing units (27 to 30), thereby changing the operation mode of each of the arithmetic processing units (27 to 30) to the through mode. The operation of 30) is a through mode in which nothing is performed (normal graphic decomposition pipeline processing is not performed), and thereafter, fault data can be transmitted as it is in the pipeline.

FIG. 6 is a block diagram showing a schematic internal configuration of each of the arithmetic processing units (27 to 30) shown in FIG.

In normal operation, each operation processing unit (2
Input data 26 to 7) to 30) are latched by an input latch circuit 37 and input to a calculator 41 via a selector 39. Similarly, the calculation parameter 38 selected by the selector 40 is also input to the calculator 41 and the decomposition calculation is executed. The operation result is fed back to the latch circuit 36 and becomes the next operation target data.

The selector 53 replaces a part of the operation target data input to the arithmetic unit 41 with the operation parameter 38 input to the arithmetic unit 41,
Output data 4 from each arithmetic processing unit (27 to 30)
3 is generated and sent to the next arithmetic processing unit.

Here, the operation parameters 38 are stored in a register, and these operation parameters 38 can be changed by the drawing control computer 120 on the upper side.

FIG. 7 is a schematic diagram for explaining an example of the decomposition operation method of the arithmetic unit 41 and the generation method of the output data 43 shown in FIG.

In the figure, a trapezoidal figure 60 indicates a trapezoidal figure represented by basic figure (trapezoidal figure) data input from the restoration processing unit 213. This trapezoidal figure data includes at least the coordinates (X0, Y) of the origin (A) of the trapezoidal figure.
0), bottom width (W) and height (H). When the trapezoidal figure data is to be decomposed in the short side direction by the operation parameter 38 of the height (h0), the height (H) of the trapezoidal figure data is calculated by the selector 53 to calculate the height (h0). The output data 43 is generated by replacing the output data 43 with the use parameters 38. Here, trapezoidal figure 6
1 indicates a trapezoidal figure represented by the output data 43.

The coordinates (X1, Y1) of the origin (B), the width (W1) and the height (h1) of the trapezoidal figure after removing the output data 43 from the trapezoidal figure data by the arithmetic unit 41. ) Is calculated. This is the data subjected to the arithmetic processing by the arithmetic unit 41 (the remaining data after the decomposition). Here, the trapezoidal figure 62 indicates a trapezoidal figure represented by the data subjected to the arithmetic processing by the arithmetic unit 41.

By such repetition, the input data 2
In 6, the arithmetic processing is sequentially executed in the arithmetic processing unit, and transmitted as output data 43 to the next arithmetic processing unit.

Here, the decomposition method and the presence / absence of decomposition are determined by the decomposition method control / decomposition determination unit 42 by the selector (3).
9, 40, 53) by controlling the selection logic.

The setting of the through mode at the time of occurrence of a failure is also realized by controlling the selector selection logic of the disassembly method control / disassembly determination unit 42 so as not to be unconditionally disassembled regardless of input data.

FIG. 8 is a block diagram showing a schematic internal configuration of the disassembly method control / disassembly determination unit 42 shown in FIG. FIG. 8 shows only the configurations of the disassembly determination unit and the mode control unit.

Data to be subjected to arithmetic processing, that is, input data 26 or data subjected to arithmetic processing, is input to the decomposition determination section 71, and the decomposition determination section 71 determines whether or not there is decomposition. Based on the instruction from the decomposition determination unit 71, the decomposition method control unit 72 determines the decomposition operation method,
A selector control signal is sent to the selectors (39, 40, 53) to control the selection logic of the selectors (39, 40, 53).

When a data error (error) is detected by the decomposition determining unit 71 or the arithmetic unit 41, the error determining unit 73
Are the pipe control units (21 to 21) of the processing pipes (11 to 14).
An error output signal is sent to the error detector 34 in the processing pipe in 24), thereby stopping the pipeline processing.

For example, if the data latched by the input latch circuit 37 is faulty data (data with a data error), a data error is detected by the decomposition method control / decomposition determination unit 42 or the arithmetic unit 41, and thereby the pipeline is detected. The operation stops. At this point, the fault data is still latched in the input latch circuit 37. After confirming that the pipeline processing has stopped due to an error, the drawing control computer 120 on the upper side instructs the processing pipe mode control unit 33 to set the operation mode of each arithmetic processing unit (27 to 30) to the through mode. Issue the instruction to change, and restart the pipeline processing.

Further, the processing pipe mode control unit 33 issues a through mode instruction to the disassembly method control / disassembly determination unit 42, whereby the disassembly method control / disassembly determination unit 42
Are controlled by the mode control unit 74 in each arithmetic processing unit (27
-30) are set to the through mode. For example, in the example shown in FIG.
5, the output from the mode control unit 74 is changed from "0" to "1", and the normal mode is changed to the through mode.

As a result, the disassembly method control section 72 controls the selection logic of the selectors (39, 40, 53), and holds the selection logic of the selector 39 as the data selected from the input latch circuit 37. When the pipeline processing is restarted, the fault data passes through the selector (39, 53) and is output data 4
It becomes 3 and is transmitted to the next arithmetic processing unit. Since the next processing unit is also in the through mode similarly, the fault data is transmitted as it is in the pipeline,
Finally, it is output to the analysis memory (16 to 19).
After confirming the completion of the restart of the pipeline, the upper-level drawing control computer 120 can recognize the failure data by reading out the analysis memories (16 to 19).

In FIG. 8, using a switch 75,
The output from the mode control unit 74 is set to “0” or “1”.
However, the present invention is not limited to this, and a register may be used.

FIG. 9 is a diagram showing an example of a data structure according to the present embodiment.

The data configuration shown in FIG. 9 is obtained by adding a failure flag 44 to the most significant bit of data transmitted in the pipeline. This fault flag is set to "0" at the time of initial operation and normal operation, and the corresponding fault flag is set to "1" only when a fault occurs.

Here, when a data error is detected by the arithmetic unit 41 or the decomposition method control / decomposition judgment unit 42 shown in FIG. 6, the decomposition method control / decomposition judgment unit 42 The upper bit (fault flag 44) is set to "1".

As described above, the failure flag 44 is added to all the data transmitted in the pipeline and the data configuration of the analysis memories (16 to 19) is made the same, so that the analysis memories (16 to It is possible to easily find the fault data 45 from the data stored in 19).

FIG. 10 is a diagram showing an operation flowchart of each of the arithmetic processing units (27 to 30) of the present embodiment.

As shown in FIG. 10, when the pipeline processing is started (Step 80), it is determined whether the operation mode is the normal mode or the through mode (Step 81). When the operation mode is the normal mode, after the arrival of input data (step 82), the disassembly determination / decomposition processing is executed (steps 83 and 85), and the data is transferred to the next arithmetic processing unit or processing pipe. (Step 87).

In the normal mode, when a data error is detected in the disassembly determination or the disassembly processing (steps 84 and 86), a failure flag is set in the failure data (step 88), and the pipeline processing is stopped (step 89). ).

If the operation mode is the through mode, the data stored in the input latch circuit 37 or the latch circuit 36 in the arithmetic processing unit is transferred to the next arithmetic processing unit or processing pipe (step 87).

In the above embodiment, the case where the present invention is applied to a data processing device having a pipeline configuration has been described. However, the present invention is not limited to this, and data processing other than a data processing device having a pipeline configuration may be performed. It goes without saying that the present invention can be applied to an apparatus.

As described above, the present invention has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the embodiments of the present invention, and various modifications may be made without departing from the gist of the present invention. It goes without saying that you get it.

[0083]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, when a failure occurs in a data processing device having a pipeline structure, for example, a data error (error) ) Is detected, the operation target data can be directly output as output data from each operation processing unit without performing the operation processing on the operation target data. It is possible to prevent a serious obstacle from being caused.

(2) According to the present invention, the fault data can be stored in the analysis memory, so that the higher-level drawing control computer reads the fault data stored in the analysis memory and reads the fault data. , It is possible to easily perform a failure analysis at the time of failure occurrence.

(3) According to the present invention, a failure analysis at the time of occurrence of a failure can be easily performed with a minimum necessary hardware and simple processing.

(4) According to the present invention, since a fault flag is set for fault data, fault data can be easily read.

(5) According to the present invention, it is possible to easily perform a failure analysis at the time of occurrence of a failure in the graphic decomposition pipeline processing in the electron beam drawing apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an electron beam (EB) drawing apparatus that executes a graphic decomposition pipeline process using a data processing apparatus having a multi-stage pipeline configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a drawing control unit 200 shown in FIG.

FIG. 3 is a block diagram illustrating a schematic configuration of a data processing device having a multi-stage pipeline configuration according to an embodiment of the present invention;

FIG. 4 is a schematic diagram for explaining graphic decomposition pipeline processing by the data processing device having a multi-stage pipeline configuration of the present embodiment.

FIG. 5 is a block diagram showing an internal schematic configuration of a processing pipe (11 to 14) shown in FIG. 3;

6 is an arithmetic processing unit (27 to 30) shown in FIG. 5;
FIG. 2 is a block diagram showing a schematic internal configuration of the device.

FIG. 7 is a schematic diagram for explaining a decomposition operation method of the operation unit 41 and a generation method of output data 43 shown in FIG. 6;

8 is a block diagram showing an internal schematic configuration of a disassembly method control / disassembly determination unit 42 shown in FIG.

FIG. 9 is a diagram illustrating an example of a data configuration according to the present embodiment.

FIG. 10 is a block diagram showing the arithmetic processing units (27 to 27) of the present embodiment;
It is a figure which shows the operation | movement flowchart of 30).

[Explanation of symbols]

11-14: processing pipe, 16-19: memory for analysis,
20: Pipe whole operation control unit, 21 to 24: Pipe control unit, 27 to 30: Arithmetic processing unit, 32: Processing pipe internal operation control unit, 33: Processing pipe mode control unit, 34 ...
.., An error detector in the processing pipe, 36, 37, 51, 52,.
Latch circuit, 38... Calculation parameters, 39, 40, 5
3 selector, 41 arithmetic unit, 42 decomposition method control / decomposition determination unit, 71 decomposition determination unit, 72 decomposition method control unit,
73: Error determination unit, 74: Mode control unit, 75: Switch, 100: Computer control unit, 110: Data conversion computer, 120: Drawing control computer, 20
0: drawing control unit, 210: digital control system, 211: interface circuit, 212: buffer memory, 213 ...
Restoration processing unit, 214: Resolution adjustment correction unit, 215: Tracking absolute calibration unit, 216: Drawing procedure control unit, 220: Analog signal processing system, 221: Transfer / deflection system, 222: Lens system, 223: Signal processing system, 230: mechanism control system, 231
... Stage control system, 232 ... Loader control system, 233 ... Exhaust system, 300 ... Drawing unit main body, 310 ... Electronic optical column,
320: stage / loader / sample chamber; 330: mount.

Claims (18)

[Claims] 1. A method of controlling a data processing device comprising two or more operation processing units connected in cascade and processing data by a pipeline operation method, wherein when a failure occurs in the data processing device, The data processing apparatus according to any one of claims 1 to 3, wherein the operation target data to be subjected to the operation processing in the operation processing unit is not subjected to the operation processing, and the operation target data is directly output as output data from each of the operation processing units. Control method. 2. When a data error is detected in operation target data to be subjected to operation processing in any one of the operation processing units, the operation target data is processed without performing the operation processing on the operation target data. 2. The control method for a data processing device according to claim 1, wherein the data is directly output as output data from each of the arithmetic processing units. 3. The control method for a data processing device according to claim 2, wherein a failure flag is set in the operation target data in which the data error has been detected. 4. The data processing device is connected to a higher-level device, and based on a command from the higher-level device, performs no arithmetic processing on the calculation target data, and uses the calculation target data as output data as it is as the output data. 4. The control method for a data processing device according to claim 1, wherein the data is output from an arithmetic processing unit. 5. An analysis memory connected to an output stage of the data processing device, wherein an arithmetic process is not performed in each of the arithmetic processing units and output as it is from the arithmetic processing unit as output data. 5. The control method for a data processing device according to claim 1, wherein data to be calculated is stored in the analysis memory. 6. The method according to claim 5, wherein the analysis memory is readable from a host device. 7. The control method for a data processing device according to claim 1, wherein a plurality of said data processing devices are cascaded. 8. A data processing device comprising two or more operation processing units connected in cascade and processing data by a pipeline operation method, wherein each of the operation processing units is operated in each of the operation processing units. A through-mode setting unit that outputs the operation target data as output data from each of the operation processing units without performing the operation processing on the operation target data on which the processing is performed. 9. Each of the arithmetic processing units includes selector means for directly outputting, as output data, input data input to each of the arithmetic processing units or arithmetic data subjected to arithmetic processing in each of the arithmetic processing units. The through mode setting means controls the selector means to output the calculation target data as output data from the respective processing units without performing the calculation processing on the calculation target data. The data processing device according to claim 8, wherein 10. Each of the operation processing units includes an error detection unit that detects a data error of the operation target data, and the error detection unit of any one of the operation processing units detects a data error of the operation target data. When you do
Based on the error signal output from the error detection unit of any of the arithmetic processing units, the through mode setting unit performs the arithmetic processing on the arithmetic target data without using the arithmetic target data as output data. The data processing device according to claim 8, wherein the data is output from each of the arithmetic processing units. 11. The apparatus according to claim 10, wherein each of the arithmetic processing units includes a flag setting unit that sets a failure flag for the operation target data in which a data error has been detected by the error detection unit. Data processing equipment. 12. The data processing device includes a pipe control unit, wherein the through mode setting unit performs no arithmetic processing on the operation target data based on a through mode instruction from the pipe control unit. The data processing apparatus according to claim 8, wherein the data to be operated is output directly from each of the operation processing units as output data. 13. The data processing apparatus is connected to a host device, and the pipe control unit issues a through mode instruction to the through mode setting means based on a through mode command from the host device. 13. The data processing device according to claim 12, wherein 14. The apparatus according to claim 1, wherein the host device receives an error signal output from an error detection unit of any one of the arithmetic processing units, and issues a through mode command to the pipe control unit. The data processing device according to claim 13. 15. An analysis memory connected to an output stage of the data processing device, wherein the analysis processing is not performed in each of the arithmetic processing units, and the data is directly output from each of the arithmetic processing units as output data. The data processing apparatus according to claim 8, wherein the calculation target data is stored in the analysis memory. 16. The data processing device according to claim 15, wherein said analysis memory is readable from a host device. 17. The data processing device according to claim 8, wherein a plurality of said data processing devices are connected in cascade.
7. The data processing device according to any one of 6. 18. An electron beam lithography apparatus comprising the data processing apparatus according to claim 8.