JPH1023744A - Power converter and its controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a circuit constituting section, by minimizing the unbalance between electric currents made to flow to a plurality of power semiconductor chips when a power converter is formed by connecting the semiconductor chips in parallel with each other. SOLUTION: Voltage drive elements 50a-50c are operated as one power element by connecting the elements 50a-50c in parallel with each other. When a signal is applied to the gates of the elements 50a-50c, the voltage of the signal is divided through resistors 64 and 65, inputted to the buffers 70a-70c of digital ICs, and turned on/off at a threshold voltage. All of the output signals of the buffers 70a-70c are inputted to an OR gate 71 and, at the same time, to exclusive OR gates 72a-72c. The output of each OR gate is ORed by means of an OR gate 73 and the output of the gate 73 turns on/off a switch element 67 through buffers 74a-74c and a resistor 68. When the element 67 is turned on, the slowest signal is supplied at the time of turning on elements and elements which are quickly turned on are suppressed by the output of the OR gate 73. Therefore, the turn-on time and turning-off time of the elements can become uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter constructed by connecting a plurality of power semiconductor elements (hereinafter referred to as "voltage driving elements") in parallel and a control device therefor.

[0002]

2. Description of the Related Art FETs and IGBTs, which are voltage driving elements,
The IEGT (Injecti0n Enhanced GateTransist0r) and the like are relatively easy to connect in parallel and change the magnitude and rate of change of the voltage-driven signal to turn on the power element,
In recent years, from the viewpoint of controllability and convenience such that the off time and the on / off speed can be relatively easily changed, a converter having a large capacity by connecting a number of such elements in parallel has been attempted in recent years.

Further, the individual voltage driving elements described above are mainly configured in a multi-chip system in which chips are connected in a package in a multi-parallel manner. By the way, when the individual elements are connected in multi-parallel to operate as one large-capacity power converter, or in the case of individual elements in which chips are connected in multi-parallel like a multi-chip, a common problem is the individual element. In a parallel connection, there is an imbalance between currents between elements, and in a multi-chip, there is an imbalance of current between the chips and a current concentration on a specific element caused by the unbalanced current.

The current concentration on this particular element or chip is
In the worst case, the device may be damaged, and the converter itself may be destroyed by the short-circuit current in the converter connected by Gretz.

The current imbalance of each element in multi-parallel connection of elements or parallel connection of chips is caused by the saturation voltage ΔVCE (sat) of each element or chip, and the change in saturation voltage at the junction temperature due to a rapid temperature rise. The threshold voltage ΔVth, the difference in inductance and resistance of the connection conductor from the gate drive circuit to the gate signal input terminal of the element,
It occurs due to the surrounding environment of the connection conductor, that is, the strength of the electromagnetic field. In addition, current imbalance occurs in each element from the power supply source of the smoothing capacitor to the power semiconductor element due to structural factors such as inductance and resistance of the connection conductor of the main circuit.

Here, multi-parallel connection of individual elements and multi-
The current imbalance at the time of multi-parallel connection of chips will be described. 13 to 16 show examples of multi-parallel connection with individual voltage driving elements of the module package, respectively. FIG. 13 shows a Gretz-connected inverter circuit,
FIG. 14 is a circuit configuration diagram when four elements of one phase in FIG. 13 are arranged in parallel, FIG. 15 is a structural diagram of the circuit configuration in FIG. 14, and FIG. 16 is an equivalent circuit diagram in the structure in FIG.

In FIG. 13, reference numeral 1 denotes a DC power supply, and a positive power supply conductor 3
However, the negative electrode power supply conductor 4 is connected to the negative electrode end side. 2 is a smoothing capacitor connected between the positive power supply conductor 3 and the negative power supply conductor 4. 5 is a positive arm. 6 is a negative arm. These positive arm 5 and negative arm 6 are Each of the three phases is connected in series between the power supply conductor 3 and the negative power supply conductor 4 corresponding to each phase. 7 is a positive arm 5 and a negative arm 6 of each phase.
Are the loads respectively connected between the series connections.

The circuit configuration of each phase arm is shown in FIGS.
As shown in FIG. 6, four voltage driving elements 8 connected in parallel are connected in parallel, and the anode electrode side is connected to an anode common conductor 9.
The cathode electrode side is commonly connected to the cathode common conductor 10, the gate electrode is connected to the gate drive signal supply common conductor 12 via the gate resistor 11, and the cathode electrode side of each voltage drive element 8 is connected to the gate drive signal. It is configured to be connected to the return common conductor 13 respectively.

The common gate drive signal supply conductor 12 and the common gate drive signal return conductor 13 are connected to a twisted pair gate drive signal supply conductor 14, respectively. Here, in the structural diagram shown in FIG. 15, reference numeral 15 denotes a heat sink, and in the equivalent circuit shown in FIG.
16, 18, 21 and 22 are stray inductances existing in the conductors 10 to 13, and 17, 19, 21 and 23 are conductors 1
This is the conductor resistance existing in 0 to 13.

FIG. 17 is a structural diagram in which the circuit configuration of FIG. 14 is reduced in inductance. The same parts as those of FIG. 15 are denoted by the same reference numerals, and different points will be described here.
In FIG. 17, reference numeral 24 denotes a plate-shaped positive power supply conductor provided above, 25 denotes a strip-shaped negative power supply conductor provided below, and 26 denotes these positive power supply conductors 24 and negative power supply conductors. 25 (dielectric) provided between
The positive power supply conductor 24 is fixed to the heat sink 15 by a positive fixing screw 27, and the negative power supply conductor 25 is fixed to the heat sink 15 by a negative fixing screw 28 inserted through a screw insertion hole of the positive power supply conductor 24.

FIG. 18 is an equivalent circuit diagram of the structure of FIG.
The same parts as those in FIG. 16 are denoted by the same reference numerals, and different points will be described here. In FIG. 18, 29, 31
Is the stray inductance present in the negative power supply conductor 25 and the dielectric 26; 30, 32 are the resistances present in the negative power supply conductor 25 and the dielectric 26; 33 is the negative power supply conductor 25
Is the stray capacitance existing between the dielectric and the dielectric 26.

At present, as described above, in the circuit configuration section in which the voltage driving elements are connected in multi-parallel, as means for eliminating the current imbalance of each element, the saturation voltage of the elements is made uniform and the main circuit is reduced in inductance. The structure shown in FIG. 15 is changed from the structure shown in FIG. 15 to the structure shown in FIG. 17. However, if a laminated structure in which an insulator is interposed between conductors as shown in FIG. Then, a stray capacitance 33 is formed between the conductor and the insulator.

Therefore, the inductance of the conductor generates a surge overvoltage and changes the cathode potential.
Influencing the control, the stray capacitance 33 has the effect of canceling the surge overvoltage and keeping the gate-cathode voltage of each element constant, and the inductance of the conductor also reduces the installation interval and conductor width of each power supply common conductor. The selection can reduce the size, and has an effect of suppressing the current imbalance of each voltage driving element to some extent.

However, even if the impedance of the main circuit conductor is reduced as shown in FIG. 17, there is a limit to the low impedance, and there is naturally a limit to the improvement of the current imbalance by this method. In other words, it is actually extremely difficult to balance the current of the element only by devising the structure of the main circuit conductor and the saturation voltage of the element.

In order to reduce the impedance, there is a configuration in which semiconductor chips are bonded in a module package and connected in multiple parallel as shown in FIG. This concept is almost the same as the multi-parallel connection of the individual voltage driving elements.

In FIG. 19, reference numeral 34 denotes a base plate; 35, a ceramic substrate provided on the base plate 34;
Is an anode (collector) electrode provided on the ceramic substrate 35, 37 is a cathode (emitter) electrode, 38 is a gate electrode, 39 is a voltage-driven semiconductor chip, 40 is a freewheel diode chip, and 41 and 42 are between electrodes. And aluminum wires connecting the chips.

In FIG. 19, the chips on the ceramic substrate 35 are drawn independently, but the anode electrode 36 and the cathode electrode 37 are connected to respective electrode terminals of the package by conductors. The gate electrodes 38 are also connected to each other, and are connected to the gate electrode of the package by a twisted pair of conductors.

In this structure, the arrangement of the chips is configured on the back,
The gate electrode 38 is located at the farthest end, and the gate electrode 38
The width of the electrode is large, the capacitance between this electrode and the base plate 34 is large, and each chip includes a delay element due to the speed condition of the gate signal, etc., so that the transmission of the gate signal is not uniform, The current of each chip may be unbalanced depending on the switching speed of the gate signal and the like.

[0019]

As described above, in a voltage driving element that is connected in multiple parallels to form a large power converter, and in a voltage driving element that is connected in parallel by a multi-chip,
Even if the saturation voltage VCE (sat) and the threshold voltage Vth, which are the element characteristics, are made uniform and the inductance of the connection conductor is reduced, it is difficult to make the current flowing through each element uniform.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a plurality of voltage driving elements connected in parallel to operate as a single power element or a plurality of voltage-driven multi-chips. And a drive circuit for a voltage-driven power converter capable of improving the reliability of the circuit component by minimizing the unbalance of the current flowing through each element or each chip of the circuit component formed by connecting the components in parallel. The purpose is to:

[0021]

In order to achieve the above object, the present invention provides a drive circuit for a voltage-driven power converter that operates as one power element by the following means. The invention according to claim 1, wherein in the power converter configured by connecting a plurality of power semiconductor chips in parallel, the power semiconductor chips are arranged in multiple concentric circles, The gate input resistance of the inside arrangement and the outside arrangement is set larger on the outside than on the inside.

Therefore, in the power converter according to the first aspect of the present invention, the phenomenon in which the element is generally destroyed by the deviation current in which the current is concentrated on the outer peripheral side is suppressed, and the flow of the current is suppressed in the outer peripheral chip. By doing so, it is possible to prevent the power semiconductor chip from being broken due to current concentration.

According to a second aspect of the present invention, there is provided a power converter comprising a plurality of voltage-driven power semiconductor chips connected in parallel, wherein the voltage-driven power semiconductor chips are multiplexed concentrically. The gate input resistance of the inside arrangement and the outside arrangement of the voltage-driven power semiconductor chip is set to be larger on the outside than on the inside, and a gate input terminal corresponding to each of the voltage-driven semiconductor chips. A gate drive circuit for providing a gate signal is provided in the center of the package in the form of an IC, and the gate of the gate drive circuit in the center is connected to each voltage-driven power semiconductor chip through a gate signal supply conductor of a uniform length. Give a signal.

Therefore, in the power converter according to the second aspect of the present invention, the deviation current and the current balance of each voltage-driven power semiconductor chip can be improved. The invention corresponding to claim 3 is a power converter control device for controlling a power converter configured by connecting a plurality of voltage-driven power semiconductor elements in parallel, wherein each of said voltage-driven power semiconductor elements A gate signal detecting means for detecting a gate signal inputted to the gate signal detecting means, and a gate signal of a voltage-driven power semiconductor element which turns on the latest when the detection signal is a turn-on signal based on the detection signal of the gate signal detecting means. In the case of a turn-off signal, the turn-off timing of the other voltage-driven power semiconductor element is set to the gate signal of the voltage-driven power semiconductor element that turns off the earliest. Signal processing means for simultaneously processing each of the voltage-driven power semiconductor elements by performing signal processing so as to match each other.

According to a fourth aspect of the present invention, there is provided a power converter control device for controlling a power converter configured by connecting a plurality of voltage-driven power semiconductor elements in parallel. A comparator that detects a gate input voltage input to a gate input terminal of the drive-type power semiconductor element based on a threshold value set in advance near a gate input terminal voltage, and detection of an input voltage of each gate detected by the comparator A signal is input, and the signal is processed so as to match the gate signal at the gate input terminal that turns on the slowest at the time of the turn-on signal and the gate signal that turns off the fastest at the time of the turn-off signal. Signal processing means for simultaneously controlling the semiconductor elements.

According to a fifth aspect of the present invention, in the power converter control device according to the third or fourth aspect, the voltage-driven power semiconductor element is an anode electrode,
A cathode electrode and one or more gate electrodes, a cathode ballast resistor or a low resistor of polycrystalline silicon is inserted on the cathode electrode side to apply a current feedback to a gate terminal, thereby saturating the voltage-driven power semiconductor device. Reduce the current imbalance caused by the voltage difference.

Therefore, in the control device of the power converter according to the third to fifth aspects of the present invention, the gate signal at the gate input terminal of each voltage-driven power semiconductor device is expressed by:
When the element is turned on, the gate input voltage is set to match the signal that turns on the slowest, and when the element is turned off, the gate input voltage is set to match the signal that turns off the fastest. By simultaneously controlling the drive-type power elements and eliminating switching delays,
The current flowing through each voltage-driven power semiconductor element can be balanced.

Further, in the invention corresponding to claim 5, the parameters of the saturation voltage Vce (sat) of the voltage-driven power semiconductor device can be made uniform, and the current imbalance caused by the difference between the saturation voltages can be suppressed. it can.

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising a plurality of anode electrodes, a first cathode electrode for main use, a second cathode electrode for sense use, and one or more voltage-driven gate electrodes. In a power converter control device for controlling a power converter configured by connecting voltage-driven power semiconductor elements in parallel, a gate input terminal is provided corresponding to each of the voltage-driven power semiconductor elements. A gate drive circuit that supplies a gate signal to the first and second current-carrying power semiconductor elements of the respective voltage-driven power semiconductor elements. Means for detecting the difference between the flowing currents and feeding back to the neutral point of the power supply of the corresponding gate drive circuit.

Therefore, in the control device of the power converter according to the present invention, the difference of the current flowing through the second cathode is fed back to the neutral point of the power supply of the gate drive circuit by the feedback means. By changing the neutral point potential so that the currents flowing through the respective voltage-driven power semiconductor elements become equal, the currents flowing through the respective voltage-driven power semiconductor elements can be balanced.

According to a seventh aspect of the present invention, there is provided a power converter control device for controlling a power converter configured by connecting a plurality of voltage-driven semiconductor chips in parallel to a module package. A gate drive circuit for providing a gate signal to a gate input terminal corresponding to each of the voltage-driven semiconductor chips is provided in the package in the form of an IC, and a uniform gate drive circuit chip is provided for each voltage-driven semiconductor chip. Bonding with a length of aluminum wire gives an even signal to the gate of each voltage driven semiconductor chip.

Therefore, in the control device for a power converter according to the present invention, an aluminum wire having a uniform length is bonded to each voltage-driven semiconductor chip, and the semiconductor chip of each voltage-driven element is bonded. The gate end of the device can be made a terminal having a very small area to eliminate a delay element of a stray capacitance generated between the terminal and the base, and to balance the current flowing through each pellet even at high speed switching.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit connection diagram showing a first embodiment of a power converter and a control device thereof according to the present invention. In FIG. 1, reference numerals 50a to 50c denote voltage driving elements including an anode electrode (collector electrode), a cathode electrode (emitter electrode), and one or more voltage-driven gate electrodes.
Each of these voltage driving elements 50a to 50c is connected in parallel to form a converter that operates as one power element.

The anode electrodes (collector electrodes) of the voltage driving elements 50a to 50c are connected to an anode common conductor 51, the cathode electrodes (emitter electrodes) are connected to a cathode common conductor 52, and the gate electrodes are connected to a gate resistor. 63, a gate drive signal supply common conductor 6
1 is connected to one output terminal of the gate drive circuit GC.

The gate electrodes of the voltage drive elements 50a to 50c are connected to a gate drive signal supply common conductor 62 via a series circuit of resistors 64 and 65, respectively. The other output terminal of the GC is connected via a twisted pair conductor 60.

A switching element 67 is connected between the gate electrode of each of the voltage driving elements 50a to 50c and the gate driving signal supply common conductor 62 via a resistor 66. The driving terminal of the switching element 67 is a resistor 69. Are respectively connected to the gate drive signal supply common conductor 62.

The gate drive circuit GC includes an amplifier circuit 55 for amplifying a control signal transmitted via a photocoupler or an optical cable 54, an NPN transistor 56 and a PNP transistor operated by the control signal amplified by the amplifier circuit 55. Transistor 57, NPN transistor 5
6 and DC power supplies 58 and 59 having the polarity shown in the figure provided on the collector side of the PNP transistor 57, respectively.

Reference numeral 53 denotes a clamp type snubber circuit connected between the anode electrode and the cathode electrode of the voltage driving element 50a. On the other hand, reference numerals 70a to 70c denote buffers composed of digital ICs in which terminal voltages applied to the gate input terminals of the voltage driving elements 50a to 50c are divided by the resistors 64 and 65 and input.
c is the Vth (threshold voltage) of the digital IC
To turn on and off to detect the gate input voltage.

Reference numeral 71 denotes these buffers 70a to 70
OR gate to which an output signal of c is input, 72a to 72c
The output signals of the OR gate 71 are respectively input to one input terminal, and buffers 70a to 70c are connected to the other input terminals.
Exclusive OR gates 73 to which the output signals of each of these are input separately.
These are OR gates to which output signals of .about.72c are respectively input.

Further, 74a to 74c are OR gates 73.
The buffers 74a to 74c supply drive signals to the drive terminals of the switch element 67 via the resistors 68, respectively.

These buffers and logic circuits constitute signal processing means. Next, the operation of the power converter control device configured as described above will be described with reference to a time chart shown in FIG.

Now, when gate signals as shown in FIGS. 2A, 2B and 2C are applied to the gate terminals of the voltage driving elements 50a to 50c, each of the voltage driving elements 50a to 50c.
The terminal voltage of the gate input terminal 50c is divided by a voltage dividing circuit of resistors 64 and 65, and the voltage of the digital IC buffer 7 is
0a, 70b, and 70c.

The buffers 70a, 70b and 70c are turned on / off by Vth (threshold voltage) of the digital IC, and all the output signals are OR gates as shown in FIGS. 2 (d), (e) and (f). 2 and exclusive OR gates 72a to 72c of the output of the OR gate 71 and the output of the buffer shown in FIG.
(Nu) is output.

Exclusive OR gates 72a-72
The output signal of c is input to the OR gate 73, and the output signal is supplied to the switch element 67 via buffers 74a to 74c as shown in FIG.
Drive for ~ t6 (at turn-off).

Therefore, by driving the switching element 67,
At the time of turn-on, it is given by the signal that operates the slowest of the turn-on signals at the gate input terminal, and the element that turns on quickly is suppressed by the output signal of the OR gate 73.

At the time of turn-off, it is given by the earliest operation signal of the turn-off signal at the gate input terminal, and the element which turns off later is suppressed by the output signal of the OR gate 73.

As described above, in the first embodiment, as the gate signal applied to the gate input terminals of the voltage driving elements 50a to 50c, the signal which turns on the gate input voltage at the time of turn-on is the slowest in the buffer constituted by the digital IC. By turning on the signal that turns off the fastest at the time of turn-off, it is possible to balance the current flowing through each voltage drive element by simultaneously controlling the multiple parallel-connected voltage drive elements to eliminate switching delays. Therefore, breakdown of each voltage driving element can be prevented, and a highly reliable converter can be realized.

FIG. 3 is a circuit connection diagram showing a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Only different points will be described here.
In the second embodiment, as shown in FIG.
The analog comparators 75a to 75c are provided on the input sides of a to 70c.
5c, and the analog comparators 75a to 75c
The terminal voltage applied to the gate input terminals of the voltage driving elements 50a to 50c is divided by a voltage dividing circuit of resistors 64 and 65 and input to one of the input terminals, and the other input terminal is connected to the gate drive signal supply common conductor 62 by a resistor. 76a-76c, resistors 77a-77c are connected, and furthermore, resistors 78a-78c are connected to input / output terminals to connect these resistors 76a-76c.
The threshold of the voltage driving element can be adjusted by 76c, 77a to 77c, and 78a to 78c.

According to the power converter control device having such a configuration, the terminal voltage applied to the gate input terminal is divided by the voltage dividing circuit of the resistors 64 and 65 and input to the analog comparators 75a to 75c having hysteresis characteristics. And
And resistors 76a to 76c, 77a to 77c, 78a to 7
By adjusting the resistance value of 8c, the accuracy of the delay of the gate pulse signal can be improved.

The analog comparators 75a-75
The output signal processing, control, and effect of c are the same as those in the first embodiment, and a description thereof will not be repeated. FIG. 4 is a circuit connection diagram showing a third embodiment of the present invention. The same parts as those in FIG.
Here, only different points will be described.

In the third embodiment, as shown in FIG. 4, a cathode ballast resistor or a low resistor 79 of polycrystalline silicon is inserted on the emitter side of each of the voltage driving elements 50a to 50c.

With the power converter control device having such a configuration, the saturation voltage Δ of the voltage driving elements 50a to 50c can be obtained.
A current flowing through Vce (sat) through a low resistance is automatically fed back to the gate, so that current imbalance due to a difference in saturation voltage can be suppressed.

In FIG. 4, each voltage driving element 50a shown in FIG.
The case where the cathode ballast resistor or the low resistor 79 is inserted on the emitter side of each of the voltage driving elements 50a to 50c shown in FIG. Is also good.

As described in the first and second embodiments, by controlling the gate input terminal signal, the difference between the parameters of the voltage driving elements 50a to 50c, the gate signal transmission conductor, etc. The current imbalance of each voltage driving element caused by a signal delay due to the above can be reduced.

FIG. 5 is a circuit connection diagram showing a fourth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Only different points will be described. 4th
In the embodiment, as shown in FIG.
0a to 50c corresponding to the gate drive circuits 80a to 80c.
c, respectively, and each of these gate drive circuits 80a-8
A gate signal input to the gate electrode 0c through a photocoupler or optical cables 54a to 54c is given to the gate electrode.

The gate drive circuits 80a to 80c include DC power supplies 81a to 81c, a resistor 82, a knot gate 83,
AND gate 84, OR gate 85, resistors 86 to 89,
It has a simplified configuration consisting of MOSFETs 90 and 91, a diode 93 and a capacitor 94, and resistors 63 to 65 and 92.

The control device for the power converter having such a configuration eliminates the need for a twisted pair gate signal transmission conductor and a common conductor from a common gate drive circuit as shown in FIGS. 1, 3 and 4. Therefore, the imbalance of the current flowing through the voltage driving element caused by the signal delay or signal distortion due to the inductance and installation environment of these conductors, that is, the electromagnetic field can be reduced.

Also, as in the first and second embodiments, the gate terminal voltage of the voltage driving element is divided and taken out, and this is processed by a signal processing circuit to control the gate signal. In addition, the current balance of each drive voltage type element connected in parallel can be improved.

FIG. 6 is a circuit connection diagram showing a fifth embodiment of the present invention. In FIG. 6, reference numerals 96a to 96c denote an anode electrode (collector electrode), a first cathode for main use and a second cathode for sense use as cathode electrodes (emitter electrodes).
The voltage driving elements 96a to 96c are connected in parallel to form a converter that operates as one power element.

Gate driving circuits 80a to 80c similar to those shown in FIG. 5 are provided corresponding to the voltage driving elements 96a to 96c, respectively.
A gate signal inputted through a photocoupler or an optical cable 54a to 54c to the gate electrode is supplied to the gate electrode.

The anode electrodes (collector electrodes) of the voltage driving elements 96a to 96c are respectively connected to the anode common conductor 51, and the cathode electrodes are connected to the cathode common conductor 52 by currents flowing to the first cathode and the second cathode, respectively. Are connected in a direction in which the currents cancel each other between the second cathodes of adjacent elements.

In such a connection circuit, current transformers 98a to 98c are provided at the intersections of the second cathodes, and the differential currents detected by the current transformers 98a to 98c are used to transfer the differential currents from the capacitors 100a to 100c and the resistors 101a to 101c. 101c
, And this differentiated signal is supplied to the neutral points a and d of the driving power sources of the gate driving circuits 80a to 80c, respectively.
Connections are made to be input to b and c, respectively.

In the power converter control device having such a configuration, when a difference between the currents flowing through the second cathodes of the adjacent voltage source driving elements is detected by the current transformers 98a to 98c, the difference current becomes It is differentiated by the differentiating circuit and fed back to the neutral point of the driving power supply of the gate driving circuit. Since the driving power supply moves around the neutral point potential and changes the gate voltage, the driving power supply is adjusted to balance the current flowing through the element. That is, when a differential signal of the differential current is given to the neutral point of the power supply of the gate drive circuit, the gate signal voltage fluctuates, and a large element having a large imbalance current has a small positive gate voltage, and a small element has a large gate voltage. To make the unbalanced current uniform.

Further, in the above driving circuit, as in the first embodiment and the second embodiment, the gate terminal voltage of the voltage driving element is divided and taken out, and this is processed by the signal processing circuit to form the gate. By controlling the signals, it is possible to enhance the effect of suppressing the unbalance current of each of the driving voltage type elements connected in parallel.

FIG. 7 shows a chip position of a module structure of a power conversion element according to a sixth embodiment of the present invention.
FIG. 8 shows the circuit connection diagram. In the sixth embodiment, as shown in FIG. 7, the package has a modular structure, and a semiconductor chip is connected in multi-parallel to constitute a voltage driving element composed of a multi-chip functioning as one power element. is there.

In FIG. 7, reference numeral 34 denotes a base plate; 102, a ceramic substrate provided on the base plate 34;
4 is a cathode (emitter) electrode provided on the ceramic substrate 102, 39 is a voltage-driven semiconductor chip 3
9 and 40 are freewheel diode chips, 105 is an aluminum wire connecting each electrode and between chips and 10
6 is a gate drive circuit.

Here, the simplified gate drive circuit 106 shown in FIG. 5 is formed as a hybrid IC or IC, and is mounted at the center of the multi-chip, and an aluminum wire having a uniform length is provided at the gate of each voltage drive element chip. And the gate end of the chip of the voltage driving element is configured as a terminal having a small area.

In FIG. 8, reference numeral 111 denotes a positive side DC power supply, 112 denotes a negative side DC power supply, 113 and 114 denote gate drive signals, 115 denotes a photocoupler or optical cable for transmitting and receiving a gate drive signal as an optical signal, and 116 denotes a DC drive. A smoothing capacitor 117 for smoothing a power supply is a knot gate to which a gate drive signal obtained by converting a light receiving signal of a photocoupler or an optical cable 115 into an electric signal is input, 118, 11
9, 120, 121, 125, 127 are resistors, 122,
123 is a MOSFET controlled by the output signal of the knot gate 117, 124 is a diode, 126 is a capacitor, and 128 is a gate resistor.

If such a package is used as a power element having a modular structure, the relay terminals 103 and 104 of the gate drive signal between the multi-chip and the IC are spotted as shown in the figure, and the casting terminal and the base plate 34 are formed. The current imbalance between the pellets caused by the delay element of the stray capacitance generated between the pellets can be suppressed, and the current flowing through the pellets can be balanced even at high speed switching.

FIG. 9 is a circuit connection diagram showing a seventh embodiment of the present invention. In the seventh embodiment, as shown in FIG. 9, semiconductor chips 132 and 133 each having an anode electrode (collector electrode), a cathode electrode (emitter electrode), and one or more voltage-driven gate electrodes are connected in multiple parallel. The semiconductor chips 132 and 133 in the package are concentrically arranged in a multilayer structure as a power converter in which the semiconductor chips 132 and 133 are packaged and operated as one power element, and the package is voltage-driven by a pressure contact structure. The gate resistance 129 of the outer peripheral chip is set to be larger than that of the central part so that group control is possible.

Here, 130 is an anode electrode / clamping plate,
131 is a cathode electrode / clamping plate, and 134 is a freewheel diode chip. With the control device for the power converter having such a configuration, it is possible to prevent the semiconductor chip disposed outside from being easily broken by the deviation current, thereby improving the reliability of the semiconductor chip.

10 to 12 show an eighth embodiment of the present invention. FIG. 10 is a side sectional view of a press-contact type package, and FIG. 11 is an arrow along the line BB in FIG. FIG. 12 is a cross-sectional view, and FIG. 12 is a circuit connection diagram.

In the eighth embodiment, FIGS.
As shown in FIG. 2, in a pressure-contact type power converter composed of multi-chips in which semiconductor chips are connected in parallel in a pressure-contact type and function as one power element, a gate drive circuit 13 is provided.
8 is integrated into an IC to simplify it, and is provided at the center of each chip as a press-contact structure.

Here, in FIG. 10 to FIG.
5 is a container made of ceramic or porcelain, 136, 13
7 is a molybdenum plate, 138 is a gate drive circuit, 139,
140 is a molybdenum plate, and 142 and 143 are gate resistors.

According to the control device for a power converter having such a configuration, the gate drive circuit, which is simplified as in the sixth embodiment, is replaced with a hybrid IC or IC, and a uniform length is provided to the multi-chip gate. And the gate end of the semiconductor chip, which is each voltage drive element, is a terminal with a small area, eliminating the stray capacitance delay element between the terminal and the base. Can be balanced. Further, similarly to the seventh embodiment, the semiconductor chip in the package is formed in a concentric multilayer structure, and the driving of the gate is separated into a central portion and an outer peripheral portion. Since the group is controlled by setting it larger than the central part, the phenomenon of destruction of the element due to the deviation current where the current concentrates on the outer peripheral side is generally achieved by suppressing the current flow on the outer peripheral chip. In addition, destruction of the semiconductor chip due to current concentration can be prevented.

[0076]

As described above, according to the power converter and the control device thereof according to the present invention, the following effects can be obtained. (1) Since some variations in the turn-on and turn-off times are automatically corrected, it is not necessary to select the switching time of each voltage driving element.

In particular, since a low resistance is inserted on the cathode side of the voltage driving element as in the third embodiment, the saturation voltage V
There is no need to strictly sort ce (sat). (2) In a voltage drive element having a multi-chip multi-parallel connection and a package having a module structure and a pressure contact structure, a simplified gate drive circuit driven by a single power supply is provided in the module package as in the sixth embodiment. By incorporating the gate signal, the gate signal is connected by the shortest conductor to prevent an imbalance in current caused by the inductance of the gate signal supply conductor and the gate signal distortion caused by the installation environment of the supply conductor.

Further, as in the seventh and eighth embodiments, a multi-chip voltage driving element in which multiple semiconductor chips are arranged concentrically in a press-contact manner as in the seventh and eighth embodiments, wherein the chips are arranged inside and outside. By performing group control under different conditions, destruction can be prevented by a phenomenon in which the current of the element easily flows outward due to the deviation current.

[Brief description of the drawings]

FIG. 1 is a circuit connection diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment.

FIG. 3 is a circuit connection diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit connection diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit connection diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit connection diagram showing a fifth embodiment of the present invention.

FIG. 7 is a layout diagram of a chip having a module structure according to a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating the embodiment.

FIG. 9 is a circuit diagram of a voltage-driven power converter having a module structure according to a seventh embodiment of the present invention.

FIG. 10 is a side sectional view showing a press-contact type package according to an eighth embodiment of the present invention.

FIG. 11 is a sectional view taken along the line BB of FIG. 10;

FIG. 12 is a circuit diagram illustrating the embodiment.

FIG. 13 is a circuit diagram for explaining a configuration of a conventional power converter.

FIG. 14 is a circuit diagram showing a configuration example of a converter corresponding to one arm in the converter.

FIG. 15 is a structural diagram of a converter corresponding to one arm in the converter.

FIG. 16 is an explanatory view of the circuit component.

FIG. 17 is a structural diagram of a converter corresponding to one arm showing a different conventional configuration example.

FIG. 18 is an explanatory view of the circuit component.

FIG. 19 is a configuration diagram showing a converter corresponding to one arm connected in multiple parallel by bonding semiconductor chips in a conventional module package.

[Explanation of symbols]

50a, 50b, 50c Voltage drive element 51 Anode common conductor 52 Cathode common conductor 54 Photocoupler or optical cable 55 Amplifying circuit 56, 57 Transistor 58, 59 DC power supply 60 Twisted pair conductors 61, 62 ... gate drive signal supply common conductor 63 ... gate resistance 64, 65, 66, 68, 69 ... resistance 67 ... switches 70a, 70b, 70c, 74a, 74b, 74c ...
Buffers 71, 73 ... OR gates 72a, 72b, 72c ... Exclusive OR gates 75a, 75b, 75c ... Analog comparator 79 ... Cathode ballast resistance or low resistance of polycrystalline silicon 80a, 80b, 80c ... Gate drive circuit 81a 81b, 81c DC power supply 83 NOT gate 84 AND gate 85 OR gate 90, 91 MOSTFET 93 Diode 94 Capacitors 96a, 96b, 96c Double-cathode voltage driving element 98a , 98b, 98c ... current transformers 100a, 100b, 100c ... capacitors 101a, 101b, 101c ... resistor 102 ... ceramic substrate 103 ... gate electrode 104 ... cathode electrode 105 ... aluminum washer 106 ... gate drive Circuit 111 Positive DC supply power 112 Negative DC supply power 113, 114 Gate drive signal 115 Photocoupler or optical cable 116 Smoothing capacitor 117 Not gate 122, 123 MOSTFET 124 ... Diode 126... Capacitors 128 and 129... Gate resistance 130... Anode and clamping plate 132 and 133... Voltage-driven semiconductor chip 134... Freewheel diode chip 135... Ceramic or porcelain 136 and 137. Molybdenum plate 138 Gate drive circuit 139, 140 Molybdenum plate 141, 142 Gate resistance

Claims (7)

[Claims] 1. A power converter comprising a plurality of power semiconductor chips connected in parallel, wherein the power semiconductor chips are arranged in multiple concentric circles, and an inner arrangement of the power semiconductor chips is provided. A power converter characterized in that the outside gate input resistance is set to be larger on the outside than on the inside so that the element is not destroyed by current concentration due to the deviation current. 2. A power converter comprising a plurality of voltage-driven power semiconductor chips connected in parallel, wherein said voltage-driven power semiconductor chips are arranged in multiple concentric circles, Drive circuit for setting the gate input resistance of the inside and outside arrangements of the semiconductor chip for power supply to be larger on the outside than on the inside, and providing a gate signal to the gate input terminal corresponding to each of the voltage-driven semiconductor chips And the IC is mounted in the center of the package, and a gate signal is supplied from a gate drive circuit chip in the center to each voltage-driven power semiconductor chip through a gate signal supply conductor of a uniform length. A power converter characterized by the above-mentioned. 3. A power converter control device for controlling a power converter configured by connecting a plurality of voltage-driven power semiconductor devices in parallel, wherein the control device is supplied to each of the voltage-driven power semiconductor devices. A gate signal detecting means for detecting a gate signal; and a voltage driven type power semiconductor element which turns on the slowest when the detection signal is a turn-on signal based on the detection signal of the gate signal detecting means. A signal to match the turn-on timing of the power semiconductor element and, in the case of a turn-off signal, to match the turn-off timing of another voltage-driven power semiconductor element to the gate signal of the voltage-driven power semiconductor element that turns off the earliest. Signal processing means for processing and simultaneously controlling each of the voltage-driven power semiconductor elements. Controller of the force transducer. 4. A power converter control device for controlling a power converter configured by connecting a plurality of voltage-driven power semiconductor elements in parallel, wherein a gate input terminal of each of said voltage-driven power semiconductor elements. A comparator that detects a gate input voltage input to the gate based on a preset threshold value near the gate input terminal voltage, and a detection signal of the input voltage of each gate detected by the comparator. Signal processing means for simultaneously controlling each of the voltage-driven power semiconductor elements by performing signal processing so as to match the gate signal at the gate input terminal that turns on late and to match the gate signal that turns off the earliest at the time of the turn-off signal. A control device for a power converter, comprising: 5. The control device for a power converter according to claim 3, wherein the voltage-driven power semiconductor device has an anode electrode, a cathode electrode, and one or more gate electrodes, and the cathode electrode. A cathode ballast resistor or low resistance of polycrystalline silicon is inserted on the side and a current feedback is applied to the gate terminal to reduce the current imbalance caused by a difference in saturation voltage of the voltage-driven power semiconductor device. Power converter control device. 6. A plurality of voltage-driven power semiconductor devices each having an anode electrode, a first main cathode electrode, a second cathode electrode for sensing, and one or more voltage-driven gate electrodes are arranged in parallel. In a power converter control device that controls a power converter configured to be connected, a gate drive circuit that is provided corresponding to each of the voltage-driven power semiconductor elements and provides a gate signal to a gate input terminal; The current flowing through the first cathode electrode and the second cathode electrode of each of the voltage-driven power semiconductor devices has a similar relationship, and the difference between the currents flowing through the second cathode electrode of the adjacent device is detected to be applicable. Means for feeding back to the neutral point of the power supply of the gate drive circuit, wherein the feedback means feeds back the difference of the current flowing through the second cathode electrode to the neutral point of the power supply of the gate drive circuit. The power converter characterized in that the neutral point potential is varied so that the currents flowing through the respective voltage-driven power semiconductor elements are equal, and the currents flowing through the respective voltage-driven power semiconductor elements are balanced. Control device. 7. A power converter control device for controlling a power converter configured by connecting a plurality of voltage-driven semiconductor chips to a module package in parallel, wherein each of the voltage-driven semiconductor chips is included in the package. The IC is equipped with a gate drive circuit that applies a gate signal to the gate input terminal corresponding to each of the above. The chip of this gate drive circuit is bonded to each voltage drive type semiconductor chip with an aluminum wire of a uniform length, A control device for a power converter, characterized in that a uniform signal is applied to the gate of each voltage-driven semiconductor chip to balance the current flowing through each voltage-driven semiconductor chip.