JPH10234050A - Solid-state image pickup camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the solid-state image pickup camera employing three CCD system to correct automatically a deviation of picture elements of each color CCD in both horizontal and vertical directions. SOLUTION: A CCD drive circuit 2 that provides outputs of a plurality of horizontal transfer clocks 3a, 3b, 3c and vertical transfer clocks 4a, 4b, 4c to drive respectively a plurality of CCDs 1a, 1b, 1c is provided with a means to stop the outputs for a prescribed period. Then the transfer is stopped by a detection signal from a registration detection circuit 10 that detects a picture element deviation among a plurality of CCD outputs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-panel system used in video cameras, digital still cameras, etc.
The present invention relates to a solid-state imaging camera having a function of automatically adjusting a pixel shift due to alignment of each of Rch, Gch, and Bch CCDs, so-called registration shift.

[0002]

2. Description of the Related Art Conventionally, in a three-panel system used in a solid-state imaging camera such as a video camera and a digital still camera, a method for automatically adjusting a registration deviation is described in Japanese Patent Application Laid-Open No. 6-46435. It has been known. Hereinafter, a conventional example will be described with reference to the drawings.

FIG. 9 is an electrical block diagram showing a part of the configuration of a conventional solid-state imaging camera. The CCD 101R for R, the CCD 101G for B, and the CCD 101B for B, which are a plurality of solid-state imaging devices, and the CCD 101R for each color. , 101
R, G, and B sample and hold circuits 102, 103, and 104 that sample and hold the respective color image pickup signals from G and 101B, and output lines of the G sample and hold circuit 103 to perform spatial pixel shifting. And a CCD 10 for each color.
The timing signal generator 106 is a driving signal generator that outputs a timing signal that is a driving signal for driving each of the 1R, 101G, and 101B, and the timing signal output from the timing signal generator 106 is stopped for a predetermined period. , The respective color CCDs 101R, 1
01G and 101B, a drive control circuit 107 serving as a horizontal transfer stop means for stopping the horizontal transfer operation of each imaging charge for a predetermined period, and the CCD 101 for each color in accordance with a timing signal supplied from the timing signal generator 106.
CCD drive circuit 10 for driving R, 101G, 101B
8 and the sample hold circuits 102 and 10 for each color.
The gain-variable color amplifiers 116, 117, and 118 that amplify and output the respective color imaging signals via the respective color amplifiers 3 and 104 and the noise components from the respective color video signals output from the respective color amplifiers 116, 117, and 118. A low-pass filter (LPF) 119, 120, 121 for each color to be removed, a G delay circuit 122 capable of varying a delay amount for delaying the G image signal from the G low-pass filter 120, and a G delay circuit 122; Control circuit 123 for controlling the delay amount of
, LPF 119, G delay circuit 122, LPF 121
& Gain 125,12 connected to the output terminal of
6,127.

A gate signal CTLH1 for horizontal transfer control, which becomes high level for a predetermined time in the drive control circuit 107.
12 is supplied, the OR gate 109 and the AND gate 110 in the drive control circuit 107 cause the horizontal transfer pulse H to be supplied.
1 ′ and H2 ′ are stopped, and the CCD1 for each color of the horizontal transfer clock φH1 and φH2 from the CCD drive circuit 108 is stopped.
The supply to 01R, 101G, and 101B is stopped, and each color video signal from each color CCD 101R, 101G, and 101B is output as a video signal of a certain level, that is, a black level.

The CCDs 101R, 101G, 1 for the respective colors
When a black-level video signal is output from 01B, the sample hold circuits 102, 103, and 104 for each color, amplifiers 116, 117, 118, and LPFs 119, 120, and 12 are output.
1. Although not shown, the delay amount is supplied to a delay difference detection circuit for each color video signal via a clamp & gain 125, 126, 127 to detect a delay amount at a point where the color video signal changes to a black level. In this conventional example, an R CCD 101R,
The G CCD 10 responds to the video signal of the B CCD 101B.
Since the 1G video signal is output earlier, the delay difference detection circuit outputs a delay control signal 124 to the delay control circuit 123 so as to delay the G video signal, and is controlled by the delay control circuit 123. The G delay circuit 1
At 22, the G video signal is output after being delayed for a predetermined time.

[0006]

However, in a solid-state imaging camera using a three-plate system, a CCD 1 for each color is used.
Just as the horizontal pixel shift amount of 01R, 101G, and 101B is the cause of the deterioration of the horizontal resolution, the pixel shift in the vertical direction also affects the image quality as the deterioration of the vertical resolution. In the conventional solid-state imaging camera, as described above, only the adjustment of the pixel shift in the horizontal direction is performed, and the pixel shift in the vertical direction cannot be adjusted.

In addition, the conventional delay circuit has a problem that the delay range is reduced because a continuous delay is realized, and it is necessary to serially connect the delay circuit for a large pixel shift. there were.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a solid-state imaging camera capable of automatically correcting both horizontal and vertical pixel shifts.

[0009]

In order to solve the above-mentioned problems, a solid-state imaging camera according to the present invention comprises a CCD driving circuit for outputting a plurality of horizontal transfer clocks and a plurality of vertical transfer clocks for driving a plurality of CCDs, respectively. For a certain period, a means for stopping the output of the horizontal transfer clock and the vertical transfer clock is provided, and a detection signal according to a pixel shift from a registration detection circuit for detecting a pixel shift between the outputs of the plurality of CCDs is provided. The transfer of the horizontal transfer clock and the vertical transfer clock to the CCD drive circuit is stopped, and the shift can be automatically corrected for both horizontal and vertical pixel shifts.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a CC for outputting a plurality of horizontal transfer clocks and a plurality of vertical transfer clocks for driving a plurality of CCDs for imaging a subject.
D driving means, means for stopping the output of the horizontal transfer clock and vertical transfer clock for a predetermined period by the CCD driving means, analog signal processing means for performing analog signal processing on CCD output signals from the plurality of CCDs, A / D conversion means for receiving a signal from the analog signal processing means and outputting a plurality of digital video signals, and receiving the plurality of digital video signals from the A / D conversion means and receiving a pixel shift between the digital video signals And a means for outputting a stop signal for instructing the CCD driving means to stop transferring the horizontal transfer clock and the vertical transfer clock to the CCD driving means in accordance with the pixel shift by the registration detection means. It is a camera, receives digital video signals from each color CCD, and the registration detection means Detecting a delay difference of the CCD of the digital video signal of use. Based on the detected delay difference, for example, GR,
GB and calculate the delay amount of the digital video signal of each color so as to match the digital video signal that is the slowest.
CCD for each color to stop horizontal transfer clock to D drive means
, And a vertical transfer clock stop signal for each color CCD for stopping the vertical transfer clock. The CCD driving means outputs the horizontal transfer clock and vertical transfer clock for each color CCD during each stop signal period. Stop. The CCD output signal from the CCD stops during the horizontal transfer clock stop signal, and the vertical transfer in the CCD stops during the vertical transfer clock stop signal. An output signal is output. That is, the CCD output signals for each color can be output in a state where the pixels match.

According to a second aspect of the present invention, there is provided a CCD driving means for outputting a plurality of horizontal transfer clocks and a vertical transfer clock for respectively driving a plurality of CCDs for picking up an image of a subject, and a horizontal synchronization with the CCD driving means. A synchronizing signal generating means for outputting a signal HD and a vertical synchronizing signal VD;
Analog signal processing means for performing analog signal processing on a CCD output signal from a CD; and A for receiving a signal from the analog signal processing means and outputting a plurality of digital video signals
Receiving the plurality of digital video signals from the A / D conversion means and the A / D conversion means, detecting a change point exceeding a predetermined threshold value of a luminance level of the plurality of digital video signals,
A level detecting means for outputting a level signal of a pixel or a line before and after the change point each time the change point is detected, and receiving the level signal, calculating a level difference between the digital video signals, and calculating a correction value. A solid-state imaging camera having control means for outputting a correction value signal based on the correction value, and arithmetic means for multiplying the plurality of digital video signals by the correction value signal. When an image of a white square arranged at the center of the corner is picked up, the level detection circuit which has received the digital video signal from the CCD for each color exceeds a predetermined threshold from the black level of the digital video signal of each color CCD. The brightness level of the pixel is determined in the horizontal direction before and after the threshold from the white level or the white level to the black level beyond the predetermined threshold, and the brightness of the line is determined in the vertical direction. Level is detected and the control means, supplied for example to the microprocessor. The microprocessor calculates a luminance level difference for each color and calculates a correction value for each color digital video signal. The correction value signal is supplied from a microprocessor to an arithmetic circuit, and the correction value is calculated for the digital video signal, whereby the pixel shift of the digital video signal can be corrected.

According to a third aspect of the present invention, there are provided a plurality of CCDs for each color for capturing an image of a subject, a plurality of horizontal transfer clocks for driving each of the plurality of CCDs, and CCD driving means for outputting a vertical transfer clock. A means for delaying the output of the horizontal transfer clock and the vertical transfer clock by the CCD driving means for a predetermined period; a synchronizing signal generating means for outputting a horizontal synchronizing signal HD and a vertical synchronizing signal VD to the CCD driving means; Analog signal processing means for performing processing such as gain control and gamma correction on a CCD output signal from the CCD; and receiving signals from the analog signal processing means,
A / D conversion means for outputting a plurality of digital video signals,
Receiving a plurality of digital video signals from the A / D conversion means, detecting a change point exceeding a predetermined threshold value of the luminance level of the plurality of digital video signals, and detecting the change point before and after the change point. Level detecting means for outputting a level signal of a pixel or a line, and receiving the level signal, calculating a level difference between the digital video signals, calculating the correction value, and calculating the C value based on the correction value signal based on the correction value.
Means for outputting a stop signal for instructing the CD drive means to stop the horizontal transfer clock and the vertical transfer clock, means for outputting the correction value signal, and whether to output the stop signal or the correction value A solid-state imaging camera having control means having means for making a determination, and arithmetic means for multiplying the plurality of digital video signals by the correction value signal. In the case where an image of a white square is taken, the level detection circuit which receives the digital video signal from the CCD for each color exceeds a predetermined threshold from the black level of the digital video signal of the CCD for each color. The luminance level of the pixel is set in the horizontal direction before and after the threshold from the white level or the white level to the black level exceeding the predetermined threshold, and the luminance level in the vertical direction. Detection control means the brightness level of emissions,
For example, supply to a microprocessor. The microprocessor calculates a luminance level difference for each color, calculates a correction value for each color digital video signal, and requires correction in horizontal or vertical pixel units by a correction value signal based on the correction value, It is determined whether or not correction is required. In the former case, a stop signal is output to the CCD drive circuit and the horizontal and vertical transfer clocks are stopped by the CCD drive circuit during the stop signal period. Each CCD can adjust the pixel shift by stopping the CCD output signal during the stop period. On the other hand, in the latter case, the correction value signal is supplied from a microprocessor to an arithmetic circuit, and the correction value signal is calculated for the digital video signal, thereby making it possible to correct the pixel shift of the digital video signal.

An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is an electric block diagram showing a partial configuration of a solid-state imaging camera according to Embodiment 1 of the present invention. FIGS. 2 and 3 are electric block diagrams of FIG. 2 is a signal waveform diagram showing an outline of the operation of the registration detection circuit at the H rate and the V rate in FIG. 1. In FIG. 1, 1a is an RCCD, 1b is a GCCD, and 1c is a BCC.
D, 2 are the above RCCD 1a, GCCD 1b, BCCD1
c, 3a, 3b, and 3c are respectively φH1, φH2, φR output from the CCD drive circuit 2.
RCCD1a, GCCD1b, B
The horizontal transfer clocks 4a, 4b, 4c of the CCD 1c are respectively φV1, φV2, φ output from the CCD drive circuit 2.
RCCD1a, GC composed of four signals V3, φV4
Vertical transfer clock of CD1b, BCCD1c, 5a, 5
b, 5c are RCCD1a, GCCD1b, BCCD1c
Is a CCD output signal that is photoelectrically converted and output.
An analog signal processing circuit for performing analog signal processing such as gain-up or gamma correction on the output signals 5a, 5b, 5c;
a, 7b, and 7c are R, G, and B analog video signals output from the analog signal processing circuit 6, 8 is an A / D conversion circuit, and 9a, 9b, and 9c are R signals output from the A / D conversion circuit 8. , G, B digital video signals, 10 is a registration detection circuit to which the digital video signals 9a, 9b, 9c are input, and 11 is a horizontal transfer clock for each of R, G, B output from the registration detection circuit 10. A stop signal (collectively illustrated), 12 is a vertical transfer clock stop signal (collectively illustrated) for each of R, G, and B that is also output by the registration detection circuit 10.
3 is a synchronous signal generating circuit, 14 is the synchronous signal generating circuit 1
The horizontal synchronizing signals HD and 15 which are output from the synchronizing signal generating circuit 13 and input to the CCD driving circuit 2 are output from the synchronizing signal generating circuit 13. The vertical synchronization signal VD shown in FIG. Reference numerals 16a, 16b, and 16c denote video signals output from the registration detection circuit 10 from which corrected pixel deviation has been removed.

In FIG. 1, a CCD drive circuit 2 has horizontal transfer clocks 3a, 3b, 3c and vertical transfer clocks 4a, 4a,
When 4b and 4c are supplied to each color CCD in the same phase, RC
CCD output signals 5a, 5b, 5c are output from CD1a, GCCD1b, BCCD1c at the same timing,
In the analog signal processing circuit 6, the CCD output signals 5a, 5b,
Digital image signals 9a, 9b and 9c converted into digital signals by the A / D conversion circuit 8 enter the registration detection circuit 10 by performing gain-up and gamma correction to make the three signal levels 5c the same. Digital video signal 9a,
Assuming that 9b and 9c are horizontal signals shown in 9a, 9b and 9c of FIG. 2, the registration detection circuit 10 determines the difference between the change point of the digital video signals 9a, 9b and 9c from the black level to the white level and the white level. The difference between the transition points from the black level to the black level is detected. That is, as shown by GR in FIG. 2, between the R digital video signal 9a and the G digital video signal 9b, the G digital video signal 9b is delayed by the registration detection circuit 10 by i time. A G-R difference signal shown in FIG. 2 is generated, and between the B digital video signal 9c and the G digital video signal 9b, as shown in GB of FIG. A GB difference signal indicating that the signal 9b is output earlier is generated. When the registration detection circuit 10 determines that the B digital video signal 9c is output with the latest delay based on the GR difference signal and the GB difference signal, C
An R horizontal transfer clock stop signal 11 for stopping the output start position of the R CCD output signal 5a by i + j to the CD drive circuit 2 and a G horizontal transfer for stopping the output start position of the G CCD output signal 5b by j A clock stop signal 11 is supplied. The CCD drive circuit 2 stops outputting the horizontal transfer clock φHr3a of R for i + j, and after i + j,
By starting to supply the horizontal transfer clock φHr3a, R
Can be delayed by i + j. Similarly, the output of the horizontal transfer clock φHg3b of G is stopped by j, and the supply of the horizontal transfer clock φHg3b is started after j. Thus, the R and G CCD output signals 5a and 5
b is output so as to be in phase with the B CCD output signal 5c.

FIG. 3 shows digital video signals 9a, 9b and 9c viewed at a vertical rate. The registration detection circuit 10 detects a line difference that changes from a black level to a white level and from a white level to a black level. In GR, G is 1
It changes with a delay of H, and in GB, B changes with a delay of 1H. That is, the registration detection circuit 10 determines that R is 2
An R vertical transfer clock stop signal 12 for stopping the vertical transfer clock by H and a G vertical transfer clock stop signal 12 for G to stop the vertical transfer clock by 1H are generated. The CCD drive circuit 2 receives the vertical transfer clock stop signal 12 and outputs 2H vertical transfer clock φV to R.
After stopping r4a, the output of the vertical transfer clock φVr4a is started, and for G, the 1H vertical transfer clock φVg
4b, the output of the vertical transfer clock φVg4b is started, so that the R, G CCD output signals 5a, 5b
Is output so as to be in phase with the CCD output signal 5c of B which is output latest.

(Embodiment 2) FIG. 4 is an electric block diagram showing a partial configuration of a solid-state imaging camera according to Embodiment 2 of the present invention, and is a diagram showing an electric block diagram of Embodiment 1. The same reference numerals are given to the same parts as 1. In FIG. 4, reference numeral 17 denotes a horizontal transfer clock common to the RCCD 1a, GCCD 1b, and BCCD 1c comprising three signals of φH1, φH2, and φR, respectively, and 18 denotes φV1, φV2, and φV, respectively.
RCCD1a, GCC composed of four signals of φ3 and φV4
A vertical transfer clock common to D1b and BCCD1c, 19 is a CCD drive circuit for generating the horizontal transfer clock 17 and the vertical transfer clock 18, and 20 is an RCCD1a, GC
The CCD output signals 5a, 5b, 5c, which are photoelectrically converted and output by the CD 1b, BCCD 1c, are converted into analog signal processing circuits 6, A for performing analog signal processing such as gain increase and γ correction.
The level detection circuit to which the R, G, and B digital video signals 9a, 9b, and 9c output from the A / D conversion circuit 8 are input via the / D conversion circuit 8, and the level detection circuit 20 for 21a, 21b, and 21c. Digital video signals 9a and 9 to be output
b, a level signal indicating the luminance level of each signal of 9c;
Is a microprocessor to which the level signals 21a, 21b, and 21c are input; 23a, 23b, and 23c are digital video signals passed through the level detection circuits 20 for each color;
a, 24b, and 24c are correction value signals from the microprocessor 22, and 25a, 25b, and 25c are digital video signals 23a, 23b, and 23c and correction value signals 24a, 24b, and 24c.
Arithmetic circuit to which 24c is input, 26a, 26b, 26c
Are video signals corrected by the arithmetic circuits 25a, 25b, and 25c and from which pixel shifts have been removed.

In FIG. 4, the CCD drive circuit 19 supplies the horizontal transfer clock φH17 and the vertical transfer clock φV18 to the respective color CCDs 1a, 1b, 1c in the same phase in accordance with the horizontal synchronization signal HD14 and the vertical synchronization signal VD15. CC
D output signals 5a, 5b, 5c are RCCD1a, GCCD
1b and BCCD 1c are output at the same timing,
The gain is increased by the analog signal processing circuit 6 to make the three signal levels the same, and the digital image signals 9a, 9b, and 9c converted to digital by the A / D conversion circuit 8 enter the level detection circuit 20. When an image of a chart, for example, an image in which a white square is arranged at the center of the angle of view in black, is taken as an object, CCDs 1a, 1b, 1
c receiving the digital video signals 9a, 9b, 9c from the color CCDs 1a, 1b, 1c.
Of the digital video signals 9a, 9b, 9c from a black level to a white level beyond a predetermined threshold or from a white level to a black level beyond the predetermined threshold to a black level,
The luminance level of the pixel is detected in the horizontal direction, and the luminance level of the line is detected in the vertical direction.
1b and 21c are output. The microprocessor 22
A luminance level difference for each color is calculated, and a digital video signal 9 for each color is calculated.
The correction value for each of a, 9b, and 9c is calculated. The correction value signals 24a, 24b, and 24c are supplied from the microprocessor 22 to arithmetic circuits 25a, 25b, and 25c, and the digital video signals 23a, 23b, and 23c are calculated by using the correction value signals 24a, 24b, and 24c. It is possible to correct a pixel shift of a video signal.

FIG. 5 is a signal waveform diagram showing an outline of the operation of the level detection circuit 20 and the microprocessor 22 at the V rate, and shows the black to white levels of the R digital video signal 9a and the G digital video signal 9b. 7 is a V-rate waveform of a change to V. The level detection circuit 20 calculates the luminance level v1r when the digital video signal 9a of R detects a change point from the black level to the white level on the line L1.
Thereafter, lines L2, L3. . And the luminance levels v2r, v sequentially
3r. . The calculation is repeated until the white level peak v4r is reached on the line L4, and the detected luminance level signal 21a is
It is supplied to the H microprocessor 22 every time. On the other hand, when the change point from the black level to the white level is detected on the line L2, the G digital video signal 9b has the same luminance level v1g, v
2g. . The calculation is repeated until the white level peak v4g is reached on the line L5, and is supplied to the H microprocessor 22 as a luminance level signal 21b. When receiving the above-mentioned luminance level signals 21a and 21b, the microprocessor 22 calculates a correction value between a change position from the black level to the white level and a peak position. As an operation example, a correction value 0 is applied to the line L1 and a correction value v1g / is applied to the line L2 so that the R digital image signal 9a is combined with the G digital image signal 9b in which the white level is detected late. v2r, the correction value v2g / v3 for line L3
r, correction value v3g / v4r at line L4, line L5
Then, the peak of the white level is converted to both digital video signals 9a and 9b.
, The correction value is set to 1. The correction value signals 24a, 24b based on the correction values are calculated by the arithmetic circuits 25a, 25
The video signals 26a and 26b from which the pixel shift has been removed by the calculation and supplied to b are output. By performing the same calculation, the video signal 26c from which the pixel shift has been removed can also be output.

In the above description, when the change from the black level to the white level is made, the R digital video signal 9a output earlier is corrected so as to match the G digital video signal 9b output later. In the change to the level, the microprocessor 22 operates so that the G digital video signal 9b output late is corrected in reverse to the above, and matches the R digital video signal 9a.

FIG. 6 is a signal waveform diagram showing an outline of the operation of the level detection circuit 20 and the microprocessor 22 at the H rate, and shows a change from the black level to the white level of the R digital video signal 9a and the G digital video signal 9b. FIG. 7 is a signal waveform diagram for each pixel of a change from a white level to a black level. The level detection circuit 20 outputs the R digital video signal 9a.
Detects the change point from the black level to the white level at the pixel P1, calculates the luminance level v1r ′, and thereafter calculates the pixel P2
P3. . And luminance levels v2r ', v3r'. . The calculation is repeated until the white level peak v4r 'at the pixel P4, and the detected luminance level signal 21a is supplied to the pixel microprocessor 22. On the other hand, when the change point from the black level to the white level is detected by the pixel P1, the G digital video signal 9b has the same brightness levels v1g ′, v2g ′. .
The calculation is repeated until the white level peak v4g 'of the pixel is reached, and each pixel microprocessor 22 supplies it as a luminance level signal 21b. When receiving the above-mentioned luminance level signals 21a and 21b, the microprocessor 22 calculates a correction value between a change position from the black level to the white level and a peak position. As a calculation example, a digital video signal in which a white level is detected late, in this example, a G digital video signal 9b
The correction value v1g ′ / v1r ′ for the pixel P1, the correction value v2g ′ / v2r ′ for the pixel P2, and the correction value v3g ′ /
In v3r 'and the pixel P4, the peak of the white level is detected by the two digital video signals 9a and 9b, so that the correction value is 1, and the change from the white level to the black level is G in reverse to the above.
Is corrected for the digital video signal 9b, and the correction value v5r '/ v5g' for the pixel P5 and the correction value v6r 'for the pixel P6.
For the / v6g 'pixel P7, the correction value 0 is calculated. The correction value signals 24a and 24b based on the correction values are calculated by an arithmetic circuit 25.
The video signals 26a and 26b from which pixel shifts have been removed by the calculation and supplied to the signals a and 25b are output. By performing the same calculation, the video signal 26c from which the pixel shift has been removed can also be output.

(Embodiment 3) FIG. 7 is an electric block diagram showing a partial configuration of a solid-state imaging camera according to Embodiment 3 of the present invention, and is a diagram showing an electric block diagram of Embodiment 1. The same reference numerals are given to the same parts as 1. In FIG. 7, reference numeral 27 denotes R output from the microprocessor 22,
G and B horizontal transfer clock stop signals (collectively illustrated) and 28 are R, G, and B vertical transfer clock stop signals (collectively illustrated) output from the microprocessor 22.

In FIG. 7, as described in the second embodiment of the present invention, when a chart, for example, an object in which a black square is arranged at the center of the angle of view in black, is picked up as a subject, each color CCD 1 a , 1b, 1c, the level detection circuit 2 receiving the digital video signals 9a, 9b, 9c
0 is a threshold from the black level of the digital video signals 9a, 9b, 9c of each color CCD 1a, 1b, 1c beyond a predetermined threshold to a white level or from the white level to a black level beyond the predetermined threshold. The luminance level of the pixel before and after the value is detected in the horizontal direction, and the luminance level of the line is detected in the vertical direction, and level signals 21a, 21b, and 21c are output. The microprocessor 22 calculates a luminance level difference for each color and calculates a correction value for each color digital video signal 9a, 9b, 9c.

FIG. 8 is a signal waveform diagram showing an outline of the operation at the V rate in the level detection circuit 20 and the microprocessor 22, and shows the R digital video signal 9a and the G digital video signal 9b from black level to white. 7 shows waveforms at each 1H of a change to a level and a change from a white level to a black level. As shown in FIG. 8, the microprocessor 22 monitors a line of the digital video signals 9a and 9b at which a change from a black level to a white level is started based on the luminance level signals 21a and 21b from the level detection circuit 20, and When it is determined that the white level change start lines of the signals 9a and 9b are separated by 2H, the vertical transfer clock stop signal 28 is output to the CCD drive circuit 2 for 2H, and the line difference is reduced to reduce the line difference. To obtain the R digital video signal 9a after the 2H vertical transfer is stopped. This R digital video signal 9
After the level detection by the level detection circuit 20 and the correction value calculation by the microprocessor 22 are performed again with the digital video signal 9b of a and G, the correction value signals 24a and 24b are supplied to the arithmetic circuits 25a and 25b, and the arithmetic circuit The calculation is performed by 25a and 25b, and the video signals 26a and 26b from which the pixel shift has been removed are output from the calculation circuits 25a and 25b. By performing the same calculation, the video signal 26c from which the pixel shift has been removed can also be output.

[0024]

According to the solid-state imaging camera of the first aspect of the present invention, the CCD driving circuit stops the horizontal transfer clock and the vertical transfer clock for driving the CCD by the horizontal and vertical clock stop signals, so that the CCD of each color is stopped. By adjusting the pixel shift of the output signal, it is possible to correct horizontal and vertical pixel shifts with a simple circuit configuration, and it is not necessary to use a delay element to delay the CCD output signal, thus reducing the circuit scale. As a result, stable correction can be realized without being affected by variations in the temperature characteristics of the delay elements.

According to the solid-state imaging camera of the second aspect, the level detection circuit detects the level for each pixel in the horizontal direction and for each line in the vertical direction, and calculates the correction value for the level by the microprocessor. By multiplying the digital video signal by the correction value, the correction can correct a pixel shift of one pixel or less in the horizontal and vertical directions and one line or less.

According to the solid-state imaging camera of the third aspect, when one pixel or more and one line or more are processed, the horizontal and vertical transfer clocks are stopped in the same manner as in the first aspect, and the level is detected again. In addition, since the calculation using the correction value can be performed, it is possible to obtain an effect that both high-accuracy pixel shift correction and correction for a large pixel shift can be realized.

[Brief description of the drawings]

FIG. 1 is an electric block diagram showing a partial configuration of a solid-state imaging camera according to Embodiment 1 of the present invention;

FIG. 2 is a signal waveform diagram showing an outline of an operation at an H rate of a registration detection circuit in the electrical block diagram of FIG. 1;

FIG. 3 is a signal waveform diagram showing an outline of an operation at a V rate of a registration detection circuit in the electrical block diagram of FIG. 1;

FIG. 4 is an electric block diagram showing a partial configuration of a solid-state imaging camera according to Embodiment 2 of the present invention;

FIG. 5 is a signal waveform diagram showing an outline of the operation of the level detection circuit and the microprocessor at the V rate in the electric block diagram of FIG. 4;

FIG. 6 is a signal waveform diagram showing an outline of the operation of the level detection circuit and the microprocessor at the H rate in the electrical block diagram of FIG. 4;

FIG. 7 is an electric block diagram showing a partial configuration of a solid-state imaging camera according to Embodiment 3 of the present invention;

8 is a signal waveform diagram showing an outline of the operation of the level detection circuit and the microprocessor at the V rate in the electric block diagram of FIG. 7;

FIG. 9 is an electrical block diagram showing a partial configuration of a conventional solid-state imaging camera.

[Explanation of symbols]

1a RCCD 1b GCCD 1c BCCD 2,19,108 CCD drive circuit 3a, 3b, 3c Horizontal transfer clock 4a, 4b, 4c Vertical transfer clock 5a, 5b, 5c CCD output signal 6 Analog signal processing circuit 7a, 7b, 7c Analog video Signal 8 A / D conversion circuit 9a, 9b, 9c, 23a, 23b, 23c Digital video signal 10 Registration detection circuit 11, 27 Horizontal transfer clock stop signal 12, 28 Vertical transfer clock stop signal 13 Synchronization signal generation circuit 14 Horizontal synchronization Signal HD 15 Vertical synchronization signal VD 16 a, 16 b, 16 c, 26 a, 26 b, 26 c Video signal from which pixel shift has been removed 17 Common horizontal transfer clock 18 Common vertical transfer clock 20 Level detection circuit 21 a, 21 b, 21 c Level signal 22 Micropro Compensator 24a, 24b, 24c Correction value signal 25a, 25b, 25c Arithmetic circuit 101R CCD for R 101G CCD for G 101B CCD for B 102 Sample hold circuit for R 103 Sample hold circuit for G 104 Sample hold circuit for B 105 Delay circuit 106 Timing signal generator 107 Drive control circuit 109 OR gate 110 AND gate 123 Delay control circuit 125, 126, 127 Clamp & gain

Claims (3)

[Claims] 1. A CCD driving means for outputting a plurality of horizontal transfer clocks and a vertical transfer clock for driving a plurality of CCDs for capturing an image of a subject, respectively, and outputting the horizontal transfer clock and the vertical transfer clock for a predetermined period by the CCD drive means. An analog signal processing means for performing analog signal processing on CCD output signals from the plurality of CCDs;
A / D conversion means for receiving a signal from the analog signal processing means and outputting a plurality of digital video signals;
Receiving the plurality of digital video signals from the D conversion means,
Registration detection means for detecting a pixel shift between the digital video signals; and a stop signal for instructing the CCD driving means to stop transferring the horizontal transfer clock and the vertical transfer clock to the CCD drive means in accordance with the pixel shift. A solid-state imaging camera having output means. 2. A CCD driving means for outputting a plurality of horizontal transfer clocks and a vertical transfer clock for respectively driving a plurality of CCDs for imaging a subject, and outputting a horizontal synchronizing signal HD and a vertical synchronizing signal VD to said CCD driving means. Synchronizing signal generating means, analog signal processing means for performing analog signal processing on the CCD output signals from the plurality of CCDs, and A / D conversion for receiving a signal from the analog signal processing means and outputting a plurality of digital video signals Means for receiving the plurality of digital video signals from the A / D conversion means, detecting a change point exceeding a predetermined threshold of the luminance level of the plurality of digital video signals, and detecting the change point each time the change point is detected. Level detection means for outputting a level signal of a pixel or a line before and after a change point; and a level between the digital video signals, receiving the level signal. A solid-state imaging camera comprising: a control unit that calculates a difference to calculate a correction value and outputs a correction value signal based on the correction value; and a calculation unit that multiplies the plurality of digital video signals by the correction value signal. 3. A CCD driving means for outputting a plurality of horizontal transfer clocks and a vertical transfer clock for respectively driving a plurality of CCDs for imaging a subject, and outputting the horizontal transfer clock and the vertical transfer clock for a predetermined period by the CCD drive means. And a horizontal synchronization signal H to the CCD driving means.
D, a synchronizing signal generating means for outputting a vertical synchronizing signal VD;
Analog signal processing means for performing analog signal processing on the CCD output signals from the plurality of CCDs; A / D conversion means for receiving signals from the analog signal processing means and outputting a plurality of digital video signals; Receiving the plurality of digital video signals from the D converting means, detecting a change point exceeding a predetermined threshold value of the luminance level of the plurality of digital video signals, and detecting a pixel before and after the change point each time the change point is detected; A level detecting means for outputting a level signal of a line, a level difference between the digital video signals, calculating a correction value by receiving the level signal, calculating a correction value, and driving the CCD with a correction value signal based on the correction value. Means for outputting a stop signal for instructing the means to stop the horizontal transfer clock and the vertical transfer clock; means for outputting the correction value signal; A solid-state imaging camera having a control means and means for selecting whether said outputs a correction value signal or output item, and arithmetic means for multiplying said correction value signal to said plurality of digital video signals.