JPH10233097A - Semiconductor storage device and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly increase the speed of a reading operation in a stable manner by eliminating the necessity of forcible bit line initialization for each reading cycle. SOLUTION: When the potential Vb of a bit line is higher than that of a reference voltage Vbref by precharging, the output of the comparator C1 of a comparison circuit 12 is inverted from a low signal to a high signal, outputted to the bit line potential initialization control unit 13 of a rear stage and synchronized with a clock signal ϕ by this bit line potential initialization control unit 13 to produce a wait signal WAIT, and ROM makes a wait request to CPU. Then, during a reading operation, an initialization signal ϕ Dis is outputted from the bit line potential initialization control unit 3 to make a switching element 11 conductive and then the potential Vb of a bit line is initialized to a ground potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a high-speed read operation of a nonvolatile memory.

[0002]

2. Description of the Related Art According to studies made by the present inventor, E
PROM (Erasable and Programmable)
In a semiconductor integrated circuit device such as an abbreviated read only memory or a flash ROM, for example, a MOS transistor is provided in a read circuit,
By forcibly initializing the potential of the bit line in each read cycle, that is, setting the potential of the bit line to the ground potential, excessive precharge of the bit line is discharged to prevent defective reading of the memory.

An example of this type of semiconductor integrated circuit device is described in detail in August 30, 1990.
Published by Nikkan Kogyo Shimbun (published by Nikkan Kogyo Shimbun) and written by Yasuji Suzuki (Author), "Semiconductor MOS Memory and How to Use It", P82 to P84. .

[0004]

However, it has been found by the present inventors that the above-described bit line precharge discharging technique has the following problems.

In recent years, with the increase in the speed of products such as electronic devices, there has been a strong demand for faster access speeds of memories mounted on the electronic devices. In order to increase the access speed of the memory, the clock frequency is increased and the clock cycle time is shortened.

However, when increasing the clock frequency to increase the speed of the readout circuit, the ratio of the drive time of the MOS transistor for initializing the potential of the bit line to the unit readout time becomes relatively large. It is difficult to secure the precharge and the data determination time of the memory, and it is difficult to increase the reading speed.

If the driving time of the MOS transistor is designed to be short, the discharge control signal, which is a pulse for driving the MOS transistor, is destroyed due to variations in process, temperature, and the like, so that the bit line is initialized. May not be possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device and a semiconductor integrated circuit device which do not require forced bit line initialization every read cycle and can stably and greatly speed up a read operation. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor memory device of the present invention, when a potential of a bit line to which data of a memory cell is transferred becomes higher than a predetermined reference voltage during a precharge operation, a wait signal for issuing a wait request to a microprocessor is provided. Bit line initialization control means for forcibly initializing the output and the bit line is provided.

Further, in the semiconductor memory device according to the present invention, the bit line initialization control means includes a switching element for discharging a bit line based on a bit line initialization signal, and a reference for generating a reference voltage for bit line initialization. A voltage generator, a voltage detector that compares the reference voltage generated by the reference voltage generator with the voltage of the bit line during the precharge operation, and determines whether to initialize the bit line; An initialization control unit generates a wait signal for issuing a wait request to the microprocessor based on the determination result of the voltage detection unit and a bit line initialization signal for controlling the operation of the switching element.

Further, in the semiconductor memory device according to the present invention, the memory cells are composed of nonvolatile memory cells.

Further, according to the semiconductor integrated circuit device of the present invention, when a potential of a bit line to which data of a memory cell is transferred becomes higher than a predetermined reference voltage during a precharge operation, a wait signal for issuing a wait request to a microprocessor is provided. And a semiconductor memory device provided with bit line initialization control means for forcibly initializing the bit line, and electrically connected to the semiconductor memory device by an external bus, and output from the bit line initialization control means. And a microcomputer provided with a microprocessor which enters a wait state on the basis of the given wait signal.

Further, the semiconductor integrated circuit device according to the present invention
The bit line initialization control means includes a switching element that discharges a bit line based on a bit line initialization signal, a reference voltage generator that generates a reference voltage for bit line initialization, and a reference voltage generator that is generated by the reference voltage generator. A voltage detector that compares the reference voltage with the bit line voltage during the precharge operation, and determines whether or not to initialize the bit line; and a microprocessor based on the determination result of the voltage detector. An initialization control unit generates a wait signal for issuing a wait request and a bit line initialization signal for controlling the operation of the switching element.

Further, in the semiconductor integrated circuit device according to the present invention, the memory cells are composed of nonvolatile memory cells.

As described above, the bit line is initialized only when the potential of the bit line becomes higher than the predetermined reference voltage. Therefore, the initialization of the bit line in each read cycle becomes unnecessary, and In addition, the reading speed of the semiconductor integrated circuit device can be significantly increased.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an RO according to an embodiment of the present invention.
Block diagram of a main part of a semiconductor integrated circuit device provided with M;
FIG. 2 is a circuit diagram of a read circuit and a bit line initialization control circuit provided in the semiconductor integrated circuit device according to one embodiment of the present invention, and FIG. 3 is a circuit diagram of the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 4 is a timing chart illustrating a reference voltage in the read circuit according to the embodiment of the present invention.

In the present embodiment, a semiconductor integrated circuit device 1 which is a microcomputer manages and controls the operation of a peripheral circuit, which will be described later, and performs a CPU (microprocessor) which performs all arithmetic or logical operations applied to data. 2) are provided.

The semiconductor integrated circuit device 1 has a ROM
(Semiconductor storage device) 3, RAM, I / O (Input /
Output) or SCI (Scalable Cohe)
Peripheral circuits such as Rent Interface) are provided. Further, the CPU 2 and peripheral circuits such as the ROM 3 are electrically connected by an internal bus.

Next, the ROM 3 is provided with nonvolatile memory cells 4, which are the minimum unit of storage, and the memory cells 4 are regularly arranged in an array to form a memory mat 5.

The ROM 3 has a row decoder 6 for selecting a word line WL for selecting a memory cell 4 in a row (row) direction and a bit for selecting a memory cell 4 in a column (column) direction. A column decoder 7 for selecting the line BL is provided.

The address signal Address output from the CPU 2 is applied to the row decoder 6 and the column decoder 7.
Connected to be input to Then, the address signal Address is output from the row decoder 6 to the memory mat 5 as a module address signal MAddress.

Further, the ROM 3 is provided with a read circuit 8 for performing a read operation of the bit line BL. Also,
The read circuit 8 includes a precharge circuit 8a for precharging the bit line BL and a sense amplifier 8b for amplifying precharged data.

Next, the read signal RDN output from the CPU 2 is stored in the ROM 3 for the selected memory cell 4.
And a reference voltage generating circuit (reference voltage generating unit) 10 for generating a reference voltage Vbref.
f is output to a comparison circuit described later.

In the ROM 3, the potential of the bit line BL is reset to the ground potential, that is, for example, by resetting the potential of the bit line BL to the ground potential.
A switching element 11 which is a switch for initializing a bit line potential, which is composed of an OS transistor, is provided.

Further, the ROM 3 stores the potential of the bit line BL at the reference voltage Vb generated by the reference voltage generation circuit 10.
A comparison circuit (voltage detection unit) 12 that determines whether the voltage is higher than ref and a bit line potential initialization control unit (initialization control unit) 13 that controls the initialization operation of the bit line BL are provided.

The reference voltage generation circuit 10, switching element 11, comparison circuit 12, and bit line potential initialization control section 13 constitute a bit line initialization control circuit (bit line initialization control means) 14. .

The output of the bit line BL via the column decoder 7 is supplied to a precharge circuit 8a, a sense amplifier 8
b, are electrically connected to the switching element 11 and the comparison circuit 12.

Further, the data of the selected memory cell 4 is electrically connected so as to be output from the sense amplifier 8b to the CPU 2 via the data bus DB, which is one of the internal buses. The precharge control signal φEQU output from 9 is input to the read circuit 8, and the module control signal MRDN is connected to the read circuit 8 and the reference voltage generation circuit 10.

The comparison circuit 12 is electrically connected to the bit line potential initialization control unit 13, and the initialization signal φDis output from the bit line potential initialization control unit 13.
Is connected to the gate of the switching element 11.

Further, the wait signal WAIT output from the bit line potential initialization control unit 13 is
Is electrically connected so as to be input to the further,
The clock signal φ is input to the bit line potential initialization control unit 13.

Next, the circuit configuration of the read circuit 8, reference voltage generation circuit 10, switching element 11, comparison circuit 12, and bit line potential initialization control unit 13 will be described with reference to FIG.

First, the precharge circuit 8a of the read circuit 8 includes a transistor Q1 which is a P channel MOS and transistors Q2 to Q4 which are N channel MOSs, and a sense amplifier 8b includes transistors Q5 to Q7 which are P channel MOSs. , N-channel MOS transistors Q8 to Q11, an inverter Iv1, and a NAND circuit N1 as a NAND circuit.

The reference voltage generation circuit 10 includes a P-channel MOS transistor Q13, an N-channel MOS transistor Q14 to Q17, and a switching element 11.
It is configured by an N-channel MOS transistor Q18.

Further, the comparison circuit 12 includes a comparator C
1 and the bit line potential initialization control unit 13
Inverters Iv2 to Iv4, NO which is a NAND circuit
It is composed of R circuits NO1 to NO5.

The transistors Q1, Q2, Q5
The drains of Q7, Q13, Q14 are electrically connected to power supply voltage Vcc, and transistors Q3, Q4, Q8,
The sources of Q9, Q11, Q15 to Q18 and the gate of transistor Q6 are electrically connected to the ground potential.

The source of the transistor Q1 is connected to the gate of the transistor Q2 and the drains of the transistors Q3 and Q4, and the gates of the transistors Q1, Q4 and Q7 are electrically connected to the output of the NAND circuit N1. .

Further, the transistors Q5, Q9, Q1
1, Q13, Q15, and Q17 are provided with the module control signal MR output from the read control unit 9 (FIG. 1).
They are electrically connected so that DN is input.

The bit line BL via the column decoder 7 is connected to the sources of the transistors Q2 and Q10, the gates of the transistors Q3 and Q8, the transistors Q11 and Q18.
Is electrically connected to one input of the comparator C1.

Further, the source of the transistor Q5 is connected to the drains of the transistors Q8 and Q9 and the transistor Q5.
10 is electrically connected to the gate of transistor Q10.
Are electrically connected to the sources of the transistors Q6 and Q7 and the input of the inverter Iv1.

The output of the inverter Iv1 is used as an output signal Vout of the sense amplifier 8b by the CPU.
2 (FIG. 1).

The gate of the transistor Q14 is connected to the source of the transistor Q13, the transistors Q15 and Q1.
6 is electrically connected to the drain of transistor Q14.
Is electrically connected to the gate of the transistor Q16, the drain of the transistor Q17, and the other input of the comparator C1, and the voltage output from the source of the transistor Q14 is the reference voltage Vbref.

Next, the output of the comparator C1 is NOR
The signal is input to one input unit of the circuit NO1 and the inverter Iv
2, a clock signal φ is input to the other input portions of the NOR circuits NO2 and NO3. Here, the clock signal φ is used to generate a wait signal WAIT, an initialization signal φDis, and an inverted initialization signal described later.

The output of the NOR circuit NO2 is electrically connected to the other input of the NOR circuit NO1.
The output of the OR circuit NO1 is connected to the NOR circuits NO2 and NO3.
Is electrically connected to one of the input sections.

Further, the output of the NOR circuit NO3 is N
The other input of the OR circuit NO5 is electrically connected, and the one input is electrically connected to the output of the NOR circuit NO4 and the input of the inverter Iv3. Then, the output of the NOR circuit NO3 is output to the CPU 2 as the wait signal WAIT.

The output of the NOR circuit NO5 is
The other input of the R circuit NO4 is electrically connected, and one input is electrically connected to the output of the inverter Iv2.

Further, the output of the inverter Iv3 is electrically connected to the input of the inverter Iv4 and the other input of the NAND circuit N1, and the output of the inverter Iv4 is electrically connected to the gate of the transistor Q18. I have.

The signal output from the inverter Iv4 becomes the initialization signal φDis, and the signal output from the inverter Iv3 becomes the inverted initialization signal φDisn.

One input of NAND circuit N1 is electrically connected so as to receive a precharge control signal φEQU output from read control unit 9, and a signal output from NAND circuit N1. Are the inverted precharge control signal φEQUIN.

The precharge circuit 8a performs precharge when the potential of the precharge control signal φEQU becomes high, and stops operation when the potential of the precharge control signal φEU is low. The sense amplifier 8b controls the module When the potential of the signal MRDN becomes low, reading is performed,
The operation stops when the potential of the module control signal MRDN becomes high.

While the precharge is being performed, the transistor Q2 of the precharge circuit 8a and the transistor Q7 of the sense amplifier 8b allow a current to flow through the bit line BL. In order to prevent a through current from flowing between the transistor Q2 and the transistor Q7 and the transistor Q10, an inverted precharge control signal φ which is a signal obtained by performing a NAND operation of the inverted initialization signal φDisn and the precharge control signal φEQU.
The transistors Q2 and Q7 are driven by the EQUN.

Next, the operation of the present embodiment will be described with reference to FIG.
This will be described with reference to FIG.

First, in the timing chart of FIG. 3, from the upper stage to the lower stage, SR1 to SR6 indicate a read sequence of the ROM 3, and SC1 to SC7 therebelow indicate the sequence of the CPU 2.

Next, in the timing chart, the state of the clock signal φ, the change of the read signal RDN output from the CPU 2, the state of the address signal Address, the state of the module address signal MADRES, the change of the precharge control signal φEQU, A change in the charge control signal φEQUUN, a change in the initialization signal φDis, and a change in the inverted initialization signal φDisn are shown.

Further, in the timing chart of FIG. 3, the change of the output voltage V4 of the NOR circuit NO4, the change of the output voltage V5 of the NOR circuit NO5, and the wait signal WAIT
, Change in output voltage V2 of NOR circuit NO1, NO
Change in output voltage V3 of R circuit NO2, comparator C1
, The change in the potential Vb of the bit line BL, and the state of the reference voltage Vbref.

Here, the operation of the semiconductor integrated circuit device 1 is as follows. For example, the CPU 2 reads data from the ROM 3 five times in succession, and all the selected memories have the memory '0' having a high threshold voltage. It is assumed that the potential Vb of the bit line BL becomes higher than the potential of the reference voltage Vbref in the fourth read period SR4.

The reference voltage Vbref determined by the current capability ratio of the transistors Q13 and Q16 is set higher than the potential Vb of the bit line BL as shown in FIG. Note that the potential Vb of the bit line BL and the reference voltage Vbre
It is necessary to provide a margin for the potential difference from f so as not to malfunction due to the influence of noise or the like.

Further, the precharge circuit 8a controls the potential fluctuation of the reference voltage Vbref due to the power supply voltage, process, temperature, etc., to be the same as the fluctuation of the potential Vb of the bit line BL.
And the sense amplifier 8b preferably have the same circuit configuration.

Then, as shown in FIG. 3, when the potential Vb of the bit line BL becomes higher than the potential of the reference voltage Vbref due to the precharge (FIG. 3E), the output of the comparator C1 of the comparison circuit 12 changes to the Lo signal. To a Hi signal to detect that the potential Vb of the bit line BL has become higher than the potential of the reference voltage Vbref.

Then, the Hi signal (V6) output from the comparator C1 is output to the bit line potential initialization control unit 13 at the subsequent stage, and the bit line potential initialization control unit 13 synchronizes with the clock signal φ, In the read period SR4, the wait signal WAIT is generated. Therefore, by the wait signal WAIT, R
OM3 can issue a wait request to CPU2.

Thereafter, in the read period SR5 of the ROM 3, the initialization signal φDis is output from the bit line potential initialization control unit 13, and the transistor Q18 is turned on, that is, the transistor V18 is turned on, thereby setting the potential Vb of the bit line BL to ground. Initialize to potential.

In the read period SR4 of the ROM 3, the ROM 3 simultaneously outputs a wait request to the CPU 2 and outputs data of 'Address = 4'.
On the other hand, in the CPU period SC5, the CPU 2
Latches the output data of 'Address = 4' of the
'Address = 5' is output to M3.

However, due to the wait request of the wait signal WAIT output from the ROM 3, the CPU 2
In the PU period SC6, without latching erroneous data during the initialization of the bit line BL, 'A = 5' is performed in the read sequence SR6 of the ROM 3 so that the process of 'Address = 5', which is originally performed in the read sequence SR5, is performed.
Outputs dress = 5 ′.

Accordingly, the read sequence S
After the initialization in R5, the data output of 'Address = 6' is performed in the read period SR6.

Since the probability of initializing the bit line BL is low, the state of the initializing operation of the bit line BL is repeated, and the heading time does not totally increase.

In this embodiment, the bit line initialization control circuit 14 initializes the bit line BL only when the potential Vb of the bit line BL becomes higher than the reference voltage Vbref. The initialization operation for each bit line is not required, and the reading speed can be significantly increased.

When the bit line BL is initialized, the bit line initialization control circuit 14 sends a wait signal W to the CPU 2.
Since the AIT is output, it is possible to reliably prevent a data read defect due to the initialization operation of the bit line BL.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, a semiconductor integrated circuit device in which a microcomputer has a built-in ROM has been described. However, all nonvolatile semiconductor storage devices such as a flash memory and a mask ROM, and a DR
AM (Dynamic Random Access)
Even if the bit line initialization control circuit 14 is provided in a volatile semiconductor memory such as a memory, the bit line initialization operation for each read cycle becomes unnecessary, and the reading speed can be greatly increased.

[0072]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the bit line is initialized only when the potential of the bit line becomes higher than a predetermined reference voltage. Therefore, it is not necessary to initialize the bit line for each read cycle. Become.

(2) In the present invention, the reading speed of the semiconductor memory device and the semiconductor integrated circuit device can be greatly increased by the above (1).

[Brief description of the drawings]

FIG. 1 is a main block diagram of a semiconductor integrated circuit device provided with a ROM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a read circuit and a bit line initialization control circuit provided in the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a timing chart of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is an explanatory diagram of a reference voltage in the read circuit according to the embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor integrated circuit device 2 CPU (microprocessor) 3 ROM (semiconductor storage device) 4 memory cell 5 memory mat 6 row decoder 7 column decoder 8 readout circuit 8a precharge circuit 8b sense amplifier 9 readout control unit 10 reference voltage generation circuit ( Reference voltage generation unit) 11 Switching element 12 Comparison circuit (Voltage detection unit) 13 Bit line potential initialization control unit (Initialization control unit) 14 Bit line initialization control circuit (Bit line initialization control unit) DB Data bus WL Word Line BL Bit line Address Address signal MADDRESS Module address signal RDN Read signal Vout Output signal φEQU Precharge control signal φEEQU Inversion precharge control signal φDisn Inversion initialization signal φDis initialization signal φ Clock signal MRD Module control signal WAIT Wait signal Q1~Q11 transistor Q13~Q18 transistor Iv1~Iv4 inverter N1 NAND circuit C1 comparator NO1～NO5 NOR circuit Vbref reference voltage Vb potential V2 output voltage V3 output voltage V4 output voltage V5 output voltage V6 output voltage

Claims (6)

[Claims] When a potential of a bit line to which data of a memory cell is transferred becomes higher than a predetermined reference voltage during a precharge operation, a wait signal for issuing a wait request to a microprocessor is output and a force of the bit line is forced. A semiconductor memory device provided with bit line initialization control means for performing initialization. 2. The semiconductor memory device according to claim 1, wherein said bit line initialization control means generates a switching element for discharging a bit line based on a bit line initialization signal, and a reference voltage for bit line initialization. A reference voltage generator that performs a comparison between a reference voltage generated by the reference voltage generator and a voltage of the bit line during a precharge operation, and determines whether to initialize the bit line. A detection unit, and an initialization control unit that generates a wait signal for issuing a wait request to the microprocessor based on the determination result of the voltage detection unit and a bit line initialization signal for controlling the operation of the switching element. A semiconductor memory device characterized by the following. 3. The semiconductor memory device according to claim 1, wherein said memory cell is a nonvolatile memory cell. 4. When a potential of a bit line to which data of a memory cell is transferred becomes higher than a set voltage value during a precharge operation, a wait signal for issuing a wait request to a microprocessor is output and the bit line is forcibly turned off. A semiconductor memory device provided with bit line initialization control means for performing initialization, a wait state electrically connected to the semiconductor memory device via an external bus, and a wait state based on a wait signal output from the bit line initialization control means; And a microcomputer provided with the microprocessor. 5. The semiconductor integrated circuit device according to claim 4, wherein said bit line initialization control means includes a switching element for discharging a bit line based on a bit line initialization signal, and a reference voltage for bit line initialization. A reference voltage generator to be generated, and comparing the reference voltage generated by the reference voltage generator with the voltage of the bit line during a precharge operation to determine whether or not to initialize the bit line. A voltage detection unit; and an initialization control unit that generates a wait signal for issuing a wait request to the microprocessor and a bit line initialization signal for controlling the operation of the switching element based on a determination result of the voltage detection unit. A semiconductor integrated circuit device characterized by the above-mentioned. 6. The semiconductor integrated circuit device according to claim 4, wherein said memory cell is a non-volatile memory cell.