JPH10233089A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a plurality of power source lines and capable of controlling connection/disconnection for these lines. SOLUTION: This device includes power source lines 3, 5 and a power source switching circuit 7 and, according to a signal ϕ supplied to the power source switching circuit 7, the power source lines 3, 5 are connected/disconnected from each other. Here, the signal ϕis made active when a sense amplifier is inactive or in a test mode and, in this case, a power source is strengthened by connection between the power source lines 3, 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having two or more different power supply lines.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device, a transistor which operates at the time of data output is relatively large (gate width W = approximately 100 μm) and generates noise on a power supply line. If used, there has been a problem that a malfunction of peripheral circuits may occur. For this reason, as shown in FIG. 20, the power supply line connected to the output circuit 1 and the power supply line connected to the peripheral circuit 2 are often separated.

[0003]

However, recently, there has been an increasing demand for speeding up the data access time, in particular, the delay of the access time due to the voltage drop of the power supply line during the operation of the output circuit, and the relative power supply noise. In order to solve the problem of increase in power supply, the necessity of strengthening the power supply line has increased.

[0004] On the other hand, the number of power supply pins is determined by the specifications of the product, and the separation of power supply lines taking only the influence of noise into consideration leads to insufficient output.
The supply of voltage to the semiconductor memory device has a design problem.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device having a plurality of power supply lines and capable of controlling connection and disconnection (opening) of the power supply lines.

[0006]

According to a first aspect of the present invention, a semiconductor memory device includes: a bit line pair; a sense amplifier for amplifying a potential difference between the bit line pair; a plurality of power supply lines; Is provided with switching means for connecting at least two of the power supply lines and disconnecting all the power supply lines when the sense amplifier is in an active state.

According to a second aspect of the present invention, there is provided a semiconductor memory device, comprising: a first power supply line, a second power supply line, a first detection means for detecting a magnitude of a voltage of the first power supply line, and a second power supply line. A second detector for detecting the magnitude of the voltage of the power supply line; and a first detector for detecting a magnitude of the voltage of the first power supply line that is larger than a first predetermined value, and a second detection. When the means detects the magnitude of the voltage of the second power supply line larger than the second predetermined value,
A switching unit for disconnecting the first power supply line from the second power supply line;

According to a third aspect of the present invention, a first power supply line connected to the first internal circuit, a second power supply line connected to the second internal circuit, and a first power supply line are provided. Current consumption detecting means for detecting the magnitude of current consumption flowing through the first power supply line and the second power supply line when the current consumption exceeding a predetermined value is detected by the current consumption detection means. And switching means for disconnecting the first power supply line from the second power supply line when the magnitude of the current consumption detected by the current consumption detection means is equal to or smaller than a predetermined value.

According to a fourth aspect of the present invention, there is provided a semiconductor memory device including a plurality of power supply lines and a fuse for connecting at least two of the power supply lines.

A semiconductor memory device according to a fifth aspect includes a plurality of power supply lines and a plurality of power supply pads for connecting at least two of the power supply lines by wiring.

A semiconductor memory device according to a sixth aspect is a semiconductor memory device having a normal operation mode and a test mode, wherein a first power supply line, a second power supply line, and an external control signal are input. Test mode detection means for detecting the occurrence of a test mode based on timing, and switching means for connecting the first power supply line and the second power supply line in the test mode detected by the test mode detection means. .

A semiconductor memory device according to a seventh aspect is a semiconductor memory device having a normal operation mode and a test mode, wherein a first power supply line, a second power supply line, and an external control signal are inputted. A test mode detecting means for detecting the occurrence of a test mode by timing, an external input terminal, and the test mode detecting means detecting the occurrence of the test mode, and when a voltage exceeding a predetermined value is supplied to the external input terminal, Switching means for connecting the first power supply line and the second power supply line.

The semiconductor memory device according to claim 8, wherein the first power supply line, the second power supply line, the external input terminal, and the first input terminal, when a voltage exceeding a predetermined value is supplied to the external input terminal. Switching means for connecting the power supply line to the second power supply line.

According to a ninth aspect of the present invention, there is provided a semiconductor memory device having an internal circuit operated by an internal power supply voltage generated by an external power supply voltage, wherein the step-down means lowers the external power supply voltage and the step-down means. Switching means for supplying the output voltage to the internal circuit as an internal power supply voltage and, in a predetermined case, supplying the external power supply voltage as it is to the internal circuit as the internal power supply voltage.

A semiconductor memory device according to a tenth aspect is the semiconductor memory device according to the ninth aspect, further comprising: a plurality of external control signal input terminals; Is supplied at a predetermined timing, the external power supply voltage is supplied as it is to the internal circuit as the internal power supply voltage.

A semiconductor memory device according to an eleventh aspect of the present invention is the semiconductor memory device according to the ninth aspect, further comprising an external terminal, wherein the switching means operates according to a voltage supplied to the external terminal. Is supplied as it is to the internal circuit as the internal power supply voltage.

A semiconductor memory device according to a twelfth aspect is a semiconductor memory device having an internal circuit operated by an internal power supply voltage generated from an external power supply voltage, wherein the first internal power supply voltage is reduced by reducing the external power supply voltage. A first step-down means for generating a second internal power supply voltage by stepping down an external power supply voltage; a first internal power supply voltage;
Switching means for selectively supplying either the internal power supply voltage or the external power supply voltage to the internal circuit as the internal power supply voltage.

A semiconductor memory device according to a thirteenth aspect is the semiconductor memory device according to the twelfth aspect, further comprising a plurality of external terminals, and the switching means is configured to switch an internal terminal according to a voltage supplied to the external terminal. The voltage supplied to the internal circuit is switched as the power supply voltage.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 shows a configuration of a power supply line and a power supply switching circuit of a semiconductor memory device according to a first embodiment of the present invention.

As shown in FIG. 1, the semiconductor memory device according to the first embodiment includes a power supply line 3 for supplying a power supply voltage VCC1 to a first internal circuit (not shown) and a power supply voltage VCC2. A power supply line 5 for supplying power to a second internal circuit (not shown) and a power supply switching circuit 7 are provided.
The power supply switching circuit 7 is connected between the power supply line 3 and the power supply line 5 and has an N-channel MOS transistor NT1 supplied with a signal φ at its gate, an inverter 9 for inverting the signal φ, and a power supply line 3 And a power supply line 5, a P-channel MOS transistor PT1 having a gate supplied with an inverted signal of signal φ.

Here, when signal φ is at a high level, both N-channel MOS transistor NT1 and P-channel MOS transistor PT1 are turned on, so that power supply line 3 and power supply line 5 are connected. When signal φ is at a low level, both N-channel MOS transistor NT1 and P-channel MOS transistor PT1 are turned off.
The power supply line 3 and the power supply line 5 are cut off.

The power supply line 3 and the power supply line 5 supply the power supply voltages VCC1 and VCC2 to the internal circuits, respectively.
1 and VSS2 are also considered. The same can be said for all the following embodiments.

FIG. 2 is a diagram showing the configuration of the memory section and its peripheral circuits of the semiconductor memory device according to the first embodiment.
As shown in FIG. 2, the semiconductor memory device includes a memory section 13, a bit line pair BL and / BL, and a column selection line 1
8, a sense amplifier 15 for amplifying the potential difference between the pair of bit lines BL and / BL, a sense amplifier driving circuit 21 for driving the sense amplifier 15, and a bit line equalizing unit 11 for equalizing the potentials of the pair of bit lines BL and / BL. , I / O gate 17 for inputting / outputting data, and word lines WL0-WLn
And a row decoder 19 for selecting word lines WL0 to WLn.
And a reference voltage supply line 10 for supplying a reference voltage VBL such as 1/2 VCC and VCC, and a signal line 12 for supplying a signal BLEQ which becomes inactive after activation of the signal / RAS.

FIG. 3 is a diagram showing a configuration of a circuit for generating the signal φ. As shown in FIG.
An OR circuit 23 connected to the word lines WL0 to WLn,
A delay circuit 25 comprising an even number of inverter chains;
Inverters 27 and 31 and a NAND circuit 29 are provided.

Next, the operation of the semiconductor memory device according to the first embodiment will be described with reference to the timing chart of FIG.

As shown in FIG. 4A, the input signal ext. When / RAS is activated, signal BLEQ shown in FIG. 4B becomes inactive. Here, for example, the signal ext. Assuming that the row address taken when / RAS is activated selects the word line WL0, as shown in FIG.
The potential of L0 becomes high (H) level. Word line WL0
Are activated, as shown in FIGS. 4F and 4G, activated signals / SAN and SAP for sensing the potential difference between the pair of bit lines BL and / BL are applied to the sense amplifier. It is supplied from the drive circuit 21 to the sense amplifier 15.

When the word line WL0 is activated,
As shown in FIG. 3, a sense completion signal SC delayed by delay circuit 25 is generated, and a signal φ is generated by signal REF.
Is generated.

Here, the signal REF is a signal generated when data output such as CBR refresh and self refresh is not performed.

As described above, according to the semiconductor memory device of the first embodiment, when data output from a memory cell is sensed by sense amplifier 15, power supply line 3 and power supply line 5 are disconnected from each other, and While the sensing operation is ensured, the power supply line 3 and the power supply line 5 are connected after the completion of the sensing operation, so that the data output capability is improved.

[Second Embodiment] FIG. 5 is a diagram showing a configuration of a power supply line and a switching unit thereof in a semiconductor memory device according to a second embodiment of the present invention.

As shown in FIG. 5, the semiconductor memory device according to the second embodiment includes power supply lines 3 and 5 and power supply switching circuit 7 in the same manner as the semiconductor memory device according to the first embodiment. And voltage detecting units 33 and 39, and NOR
The circuit includes a circuit 45 and an inverter 47. Here, the voltage detection unit 33 includes a reference voltage Vref1 and a power supply voltage VCC1.
, And a voltage detection unit 39 includes a reference voltage Vref2 and a power supply voltage VCC2.
, And a comparator 41 for comparing.

Next, the operation of the semiconductor memory device will be described. When the power supply voltage VCC1 or the power supply voltage VCC2 is lower than the reference voltage Vref1 or the reference voltage Vref2, respectively, the signal LVCC input to the NOR circuit 45 is output.
1 or the signal LVCC2 goes high, so that the signal φ input to the power supply switching circuit 7 goes high. Therefore, N-channel MOS transistor NT1 and P-channel MOS transistor PT1 are both turned on, and power supply line 3 and power supply line 5 are connected. Thus, in this case, the power supply is strengthened.

On the other hand, when the power supply voltage VCC1 is changed to the reference voltage Vre
f1 and the power supply voltage VCC2 is equal to the reference voltage Vr.
If it is higher than ef2, 2
Since the two signals LVCC1 and LVCC2 are both at a low (L) level, the signal φ input to the power supply switching circuit 7 is at a low level. Therefore, both N-channel MOS transistor NT1 and P-channel MOS transistor PT1 are turned off, and power supply line 3 and power supply line 5 are disconnected.
Thus, in this case, generation of noise in the output circuit and the peripheral circuit is reduced.

[Third Embodiment] FIG. 6 is a diagram showing a configuration of a power supply line and a switching unit thereof in a semiconductor memory device according to a third embodiment of the present invention.

As shown in FIG. 6, the semiconductor memory device according to the third embodiment has power supply lines 3 and 5 and a power supply switching circuit 7 similar to the semiconductor memory device according to the above embodiment.
And However, the power supply line 3 has the resistance R is connected to the internal circuit (illustrated not), power supply line 5 has a resistance R _Q is connected to an output circuit (not shown), the current i flows.

Further, the semiconductor memory device according to the third embodiment, the resistor R respectively potentials potential V2 of the potential V1 and the point B of the point A in _Q V1 ', V2' cross-coupled to amplify the differential Amplifying circuit 49 such as a mold, potential V1 'and potential V
A level determining unit 51 is provided for determining whether the difference 2 'is greater than a predetermined value.

Next, the operation of the semiconductor memory device according to the third embodiment will be described. For example, when the current i is large, such as during a burst read in a synchronous semiconductor memory device,
The voltage drop across the resistor R _Q, potentials V1 and V2
The difference becomes large. Therefore, the potential V1 'and the potential V
2 'also increases. At this time, the potential V1 'and the potential V
When the difference of 2 ′ exceeds a predetermined value, level determining section 51 outputs signal φ having a high level. Therefore, both N-channel MOS transistor NT1 and P-channel MOS transistor PT1 are turned on, and power supply line 3 and power supply line 5 are connected.

As described above, when the consumed current i is large, the power supply current is dispersed, and disconnection due to electromigration can be prevented.

On the other hand, when the current i is small, the voltage drop across the resistor R _Q, the difference between the potentials V1 and V2 is reduced. Therefore, the difference between the potential V1 'and the potential V2' also becomes small. At this time, if the difference between potential V1 'and potential V2' is less than a predetermined value, level determining section 51 outputs signal φ having a low level. Therefore, N-channel MOS transistor NT1 and P-channel MOS transistor PT
1 are both turned off, and the power supply line 3 and the power supply line 5 are disconnected.

As described above, when the consumed current i is small, the noise of the output circuit and the internal circuit is reduced.

[Fourth Embodiment] FIG. 7 is a diagram showing a configuration of a power supply line and a switching portion thereof of a semiconductor memory device according to a fourth embodiment of the present invention.

As shown in FIG. 7, the semiconductor memory device according to the fourth embodiment includes power supply lines 3 and 5, and a fuse 53 connecting both power supply lines 3 and 5.

Generally, a semiconductor memory device is manufactured by a wafer process step and a subsequent assembly step. After the wafer process step, laser trimming for cutting a fuse is performed to replace an unnecessary portion with a redundant circuit.

Here, the power supply voltages VCC1, VC used
By cutting the fuse 53 in the laser trimming process according to the size of C2, the power lines 3 and 5 connected in advance can be cut off before the product is completed.

[Fifth Embodiment] FIG. 8 is a diagram showing a configuration of a power supply line and a switching section thereof in a semiconductor memory device according to a fifth embodiment of the present invention.

As shown in FIG. 8, the semiconductor memory device according to the fifth embodiment has power supply lines 3 and 5, a power supply pad 55 connected to power supply line 3, and a power supply line connected to power supply line 5. And a pad 56.

In the semiconductor memory device according to the present embodiment,
In the assembly process, the power supply pad 55 and the power supply pad 5
By connecting 6 with wires 57, the power supply can be strengthened before the product is completed.

[Sixth Embodiment] A semiconductor memory device according to a sixth embodiment of the present invention includes a power supply line 3 shown in FIG.
5 and a power supply switching circuit 7, which have a normal operation mode and a test mode, and further, as shown in FIG.
External signal input terminals 60, 62, 64, test mode detection circuit 59, NAND circuit 91, inverter 93
And a delay circuit 95.

Here, the test mode detection circuit 59 includes delay circuits 71, 73, 81, NOR circuits 63, 79,
NAND circuits 69, 77, 83, 85, 87, inverters 61, 65, 67, 75, 89, N-channel MO
And an S transistor NT30. Also, the delay circuit 7
Each of 1, 73, 81 and 95 includes an even number of inverters connected in series.

Next, the operation of the semiconductor memory device according to the sixth embodiment will be described with reference to FIG.

A signal IPOR which normally has a high level and becomes a low level only for a predetermined time after the power is turned on is shown in FIG.
As shown in FIG.
1, the signal IBBU which goes to a high level other than during the self-refresh is input to the delay circuit 71 when the signal IBBU is input to the NAND circuits 77 and 91 as the high level as shown in FIG. Write enable signal ext. / WE, a column address strobe signal ext. / CAS is Figure 10
Activated as shown in (c) and (b), respectively.
As shown in FIG. 10A, the row address strobe signal ext. / RAS is subsequently activated (such timing is referred to as “WC
As shown in FIG. 10F, the test mode detection circuit 59 outputs the high-level signal W
Outputs CBR.

The signal WCBR and the high-level signal IBBU are input to the NAND circuit 91.
As shown in (f) and (g), the signal φ is the signal WCB
R is at the high level during the high level.

As described above, WCB not used in normal operation
When the test mode is entered by inputting an external control signal at R timing, the power supply line 3 and the power supply line 5 are connected, and the power supply is strengthened.

[Seventh Embodiment] A semiconductor memory device according to a seventh embodiment of the present invention includes a power supply line 3 shown in FIG.
5 and a power supply switching circuit 7, and further has a normal operation mode and a test mode, and further includes a test mode detection circuit 59 shown in FIG.

As shown in FIG. 11, the semiconductor memory device according to the seventh embodiment has an address terminal 96,
It includes a detector 97, NAND circuits 105 and 109, inverters 107 and 111, P-channel MOS transistors PT2 and PT3, N-channel MOS transistors NT9 and NT10, and a delay circuit 113.

Here, detector 97 includes N-channel MOS transistors NT2 to NT8 connected in series, and switching units 99, 101 and 103. This switching unit 99,
Connection and disconnection of 101 and 103 are determined by a mask pattern in a one-layer aluminum wiring process or a two-layer aluminum wiring process. NAND circuit 109 includes P-channel MOS transistors PT4 and PT5 and N-channel MOS transistors NT11 and NT12. Delay circuit 113 includes an even number of inverters connected in series.

The detector 97 is an N-channel MOS transistor in a normal operating voltage range (-1.0 V to 7.0 V).
This is adjusted so that the transistor NT11 does not turn on.

Next, a seventh embodiment will be described with reference to FIG.
The operation of the semiconductor memory device according to the first embodiment will be described.

When signal IBBU having a high level shown in FIG. 12B is input to NAND circuit 105, signal WCBR having a high level is output from test mode detection circuit as shown in FIG. When input to NAND circuit 105, N-channel MOS transistor NT12 is turned on.

When a voltage of 9.0 V exceeding the normal operating voltage range is applied to the address terminal 96 as the address signal A1, an N-channel MO in the detector 97 is provided.
S transistors NT2 to NT8 are sequentially turned on, and N channel MOS transistor NT11 is turned on. Than this,
A low level signal is output from the NAND circuit 109, and the signal ISVDF goes high as shown in FIG. The signal ISVDF is supplied to the delay circuit 113
And a signal φ having a high level is generated as shown in FIG. The power supply line 3 and the power supply line 5 are connected by the signal φ having the high level, and the power supply is strengthened.

As described above, according to the semiconductor memory device of the seventh embodiment, an external control signal is input at a WCBR timing that is not used in a normal operation, and an address signal A1 is supplied from the outside, so that the power supply line 3, 5 can be connected, and the power supply can be strengthened without error in the test mode.

In the seventh embodiment, it can be similarly considered that the address terminal 96 is replaced with an unused terminal not used in the specification.

[Eighth Embodiment] A semiconductor memory device according to an eighth embodiment includes power supply lines 3 and 5 shown in FIG.
As shown in FIG. 13, the power supply switching circuit 7 is further provided with an empty terminal 115 not used in the specification, a detector 97 connected to the empty terminal, and a NAND circuit 11.
7 and an inverter 119.

Next, the operation of the semiconductor memory device according to the eighth embodiment will be described with reference to FIG.

When the high-level signal IBBU shown in FIG. 14B is input to the NAND circuit 117, the normally used voltage range (-1. 9.0 V exceeding 0 V to 7.0 V)
When the voltage NC is supplied, a low-level signal is output from the NAND circuit 117 and inverted by the inverter 119, so that a signal φ having a high level is generated as shown in FIG. You. Thereby, the power supply line 3 and the power supply line 5 are connected.

As described above, according to the semiconductor memory device of the eighth embodiment, the power supply line can be connected by supplying a predetermined voltage to the vacant terminal, and the vacant terminal can be effectively used.

[Ninth Embodiment] FIG. 15 is a circuit diagram showing a configuration of a power supply voltage supply section of a semiconductor memory device according to a ninth embodiment of the present invention.

As shown in FIG. 15, the ninth embodiment
The semiconductor memory device according to the external power supply voltage Ext. VCC
And an internal power supply voltage int. To an internal circuit (not shown). It includes an internal power supply voltage line 123 for supplying VCC, a step-down circuit 125, a step-down voltage determining unit 127, and a supply voltage switching circuit 129.

Here, step-down circuit 125 is an N-channel MOS transistor NT which is diode-connected and connected in series between external power supply voltage line 121 and a ground node.
13 to NT16, supply voltage switching circuit 129 includes an inverter 131 for inverting signal φ, and an N-channel MOS transistor NT1 connected between external power supply voltage line 121 and internal power supply voltage line 123 to receive signal φ at its gate.
7, a P-channel MOS transistor PT6 connected between external power supply voltage line 121 and internal power supply voltage line 123 and receiving at its gate an inverted signal of signal φ, and step-down voltage determining unit 1
P-channel MOS transistor PT7 connected between transistor 27 and internal power supply voltage line 123 to receive signal φ at its gate.
And an N-channel MOS transistor NT18 connected between down-converted voltage determining section 127 and internal power supply voltage line 123 and receiving an inverted signal of signal φ at its gate.

The connection of the step-down voltage determining unit 127 is determined by a mask pattern used in the single-layer aluminum wiring process and the double-layer aluminum wiring process.

It should be noted that signal φ is equal to that in the sixth to eighth embodiments.
This is generated by a circuit similar to any of the circuits described by.

Next, the operation of the semiconductor memory device according to the ninth embodiment will be described with reference to FIG. In the following, as an example, as shown in FIG. 16, the step-down voltage determining unit 127 connects the source of the N-channel MOS transistor NT13, the drain of the N-channel MOS transistor NT18, and the source of the P-channel MOS transistor PT7, Step-down circuit 125 to supply voltage switching circuit 1
29, the voltage VCC lower than the power supply voltage VCC by the threshold voltage Vth of the N-channel MOS transistor NT13.
−Vth is supplied.

First, when the signal φ supplied to the supply voltage switching circuit 129 is at the high level, the N-channel MO
S transistor NT17 and P channel MOS transistor PT6 are turned on, and external power supply voltage line 121 and internal power supply voltage line 123 are connected. Thus, as shown in FIG. 16B, the external power supply voltage Ext. VCC is the internal power supply voltage int. It is supplied to an internal circuit (not shown) as VCC.

Next, when signal φ supplied to supply voltage switching circuit 129 attains a low level as shown in FIG. 16A, P-channel MOS transistor PT7
And N channel MOS transistor NT18 are turned on, so that voltage down converter 125 and internal power supply voltage line 123 are connected. Thus, as shown in FIG. 16B, the internal power supply voltage int. A voltage VCC-Vth is supplied to an internal circuit (not shown) as VCC.

As described above, according to the semiconductor memory device of the ninth embodiment, in the test mode or when a voltage higher than the predetermined value is supplied from outside to the empty terminal, the external power supply voltage is directly used as the internal power supply voltage. In addition to supplying to the internal circuit, in normal operation, a voltage obtained by stepping down the external power supply voltage can be supplied to the internal circuit, so that a voltage of a different magnitude can be selectively supplied to the internal circuit as the internal power supply voltage. it can.

Further, spike noise generated in the semiconductor memory device can be reproduced by controlling the level of signal φ, and the spike noise can be evaluated.

[Embodiment 10] FIG. 17 shows a structure of a power supply voltage supply section of a semiconductor memory device according to an embodiment 10 of the present invention.

As shown in FIG. 17, the first embodiment
0, the external power supply voltage line 121, the internal power supply voltage line 123, the step-down circuit 125, the step-down voltage determining unit 133, and the supply voltage. A switching circuit 135.

Here, step-down circuit 125 includes N-channel MOS transistors NT13 to NT16 which are diode-connected and connected in series.
The connection 3 is determined by a mask pattern used in a one-layer aluminum wiring process or a two-layer aluminum wiring process.

The supply voltage switching circuit 135 is connected between the external power supply voltage line 121 and the internal power supply voltage line 123 and has an N-channel MOS transistor NT19 having a gate supplied with a signal φ, and an inverted signal φ. An inverter 137 to be connected, a P-channel MOS transistor PT9 connected between the source of the N-channel MOS transistor NT13 and the internal power supply voltage line 123 and having a gate supplied with the signal φ1, and an inverter 139 to invert the signal φ1;
The signal φ1 is connected between the source of the N-channel MOS transistor NT13 and the internal power supply voltage line 123 and has a gate connected thereto.
N-channel MOS transistor NT20 to which the inverted signal of the above is supplied, step-down voltage determining section 133 and internal power supply voltage line 1
23, a gate of which is supplied with a signal φ2, a P-channel MOS transistor PT10, an inverter 141 for inverting the signal φ2, and a step-down voltage determining unit 133.
And an internal power supply voltage line 123, and an N-channel MOS transistor NT21 whose gate is supplied with an inverted signal of signal φ2.

FIG. 18 is a circuit diagram showing a structure of a circuit for generating signals φ, φ1, φ2. As shown in FIG. 18, this circuit includes empty terminals 143 and 145, an exclusive OR circuit 147, a NOR circuit 159, NAND circuits 153 and 155, and inverters 149, 151 and 157.
And

Next, the operation of the semiconductor memory device according to the tenth embodiment will be described with reference to FIG.

In the following, however, as shown in FIG. 17, step-down voltage determining section 133 connects the source of N-channel MOS transistor NT13 to the drain of N-channel MOS transistor NT21 and the source of P-channel MOS transistor PT10. It is assumed that the signal IPOR input to the inverter 157 shown in FIG. 18 is at a high level as shown in FIG.

As shown in FIG.
3 to 145, when the voltages NC1 and NC2 are both at the low level or the high level.
From T3 to T4 to T5, the signals φ, φ1 and φ2 are all at the high level. In this case, the N-channel MO
S transistor NT19 and P channel MOS transistor PT8 are turned on, and external power supply voltage line 121 and internal power supply voltage line 123 are connected. Therefore, this period is shown in FIG.
(G), the external power supply voltage Ext. VCC
Is the internal power supply voltage int. It is supplied to an internal circuit (not shown) as VCC.

The voltage N supplied to the empty terminal 143
At times T1 to T2 when C1 is at a high level and the voltage NC2 supplied to the empty terminal 145 is at a low level, the signals φ and φ1 are at a low level, and the signal φ2 is at a high level. At this time, since N-channel MOS transistor NT20 and P-channel MOS transistor PT9 are turned on, as shown in FIG. 19 (g), external power supply voltage Ext. N-channel MOS transistor N from VCC
Text voltage Ext. VC
C-Vth is equal to the internal power supply voltage int. It is supplied to the internal circuit as VCC.

The voltage N supplied to the empty terminal 143
During times T3 to T4 when C1 is at low level and voltage NC2 supplied to empty terminal 145 is at high level, signals φ and φ2 are at low level and signal φ1 is at high level. At this time, since the N-channel MOS transistor NT21 and the P-channel MOS transistor PT10 are turned on, the external power supply voltage Ext. VCC lower than the voltage Ext. 2 by the threshold voltage 2Vth of the two N-channel MOS transistors NT13 and NT14. VCC-2Vth is the internal power supply voltage in
t. It is supplied to the internal circuit as VCC.

As described above, according to the semiconductor memory device of the tenth embodiment, by controlling the voltage supplied to the vacant terminal, three types of voltages having different magnitudes can be selectively used as the internal power supply voltage. Can be supplied to

Further, by controlling the magnitude of the voltage supplied to the vacant terminals, the spike noise generated in the semiconductor memory device can be reproduced more accurately, and the generated spike noise can be evaluated more accurately.

[0090]

According to the semiconductor memory device of the first aspect, the power supply line is disconnected when the sense amplifier is in the active state, and the power supply line is connected when the sense amplifier is in the inactive state. Can be realized, and the data output capability can be improved.

According to the semiconductor memory device of the second aspect,
When the power supply voltage level is low, the power supply line is connected, and when the power supply voltage level is high, the power supply line is disconnected, so that power supply noise can be avoided and the power supply can be strengthened.

According to the semiconductor memory device of the third aspect,
When the current consumption is high, connect the power supply line.When the current consumption is low, disconnect the power supply line.This can prevent disconnection by dispersing the power supply current, and can reduce noise to improve power supply reliability. it can.

According to the semiconductor memory device of the fourth aspect,
The power supply line can be disconnected before the product is completed.

According to the semiconductor memory device of the fifth aspect,
The power line can be connected before the product is completed.

According to the semiconductor memory device of the sixth aspect,
Power can be enhanced in test mode.

According to the semiconductor memory device of the seventh aspect,
In the test mode, the power supply can be strengthened without malfunction.

According to the semiconductor memory device of the eighth aspect,
By supplying a voltage exceeding a predetermined value to the external input terminal, the power supply can be strengthened, and the external input terminal can be used effectively.

According to the semiconductor memory device of the ninth aspect,
Voltages having different levels can be selectively supplied to an internal circuit as an internal power supply voltage, and noise can be evaluated.

According to the semiconductor memory device of the tenth aspect, voltages having different levels can be selectively supplied to the internal circuit as the internal power supply voltage according to the timing of the input external control signal, and the noise can be evaluated. Can be.

According to the semiconductor memory device of the eleventh aspect, voltages having different levels can be selectively supplied to the internal circuit as the internal power supply voltage according to the voltage supplied to the external terminal, and noise can be reduced. Can be evaluated.

According to the semiconductor memory device of the twelfth aspect, three types of voltages having different levels can be selectively supplied to the internal circuit as the internal power supply voltage, and the noise can be more accurately evaluated. it can.

According to the semiconductor memory device of the thirteenth aspect, three types of voltages having different levels can be selectively supplied to the internal circuit as the internal power supply voltage according to the voltage supplied to the external terminal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a power supply line and a power supply switching circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a memory unit and peripheral circuits of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a circuit for generating signal φ shown in FIG. 1;

FIG. 4 is a timing chart for explaining an operation of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 5 is a diagram showing a configuration of a power supply line and a switching unit thereof in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a power supply line and a switching unit thereof in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a power supply line and a switching unit thereof in a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a power supply line and a switching unit thereof in a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a circuit for generating a signal φ in a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the circuit shown in FIG. 9;

FIG. 11 is a diagram showing a configuration of a circuit for generating a signal φ in a semiconductor memory device according to a seventh embodiment of the present invention.

12 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 13 is a diagram showing a configuration of a circuit for generating a signal φ in a semiconductor memory device according to an eighth embodiment of the present invention.

14 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 15 is a circuit diagram showing a configuration of a power supply voltage supply unit of a semiconductor memory device according to a ninth embodiment of the present invention.

16 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 17 is a circuit diagram showing a configuration of a power supply voltage supply unit of a semiconductor memory device according to a tenth embodiment of the present invention.

18 is a circuit diagram showing a configuration of a circuit for generating signals φ, φ1, and φ2 in FIG.

FIG. 19 is a timing chart for explaining the operation of the circuits shown in FIGS. 17 and 18;

FIG. 20 is a diagram showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

3, 5 power supply line, 7 power supply switching circuit, 15 sense amplifier, 33, 39 voltage detector, 49 amplifying circuit, 51
Level determination unit, 53 fuse, 55, 56 power pad, 59 test mode detection circuit, 60, 62, 64
External signal input terminal, 96 address terminals, 115, 1
43, 145 unused terminal, 125 step-down circuit, 129,
135 supply voltage switching circuit, NT1 to NT21 N-channel MOS transistor, BL, / BL Bit line pair.

Claims (13)

[Claims] 1. A bit line pair, a sense amplifier for amplifying a potential difference between the bit line pair, a plurality of power lines, and at least two of the power lines when the sense amplifier is inactive. Switching means for disconnecting all the power supply lines when the sense amplifier is in an active state. 2. A first power supply line, a second power supply line, first detection means for detecting a magnitude of a voltage of the first power supply line, and a magnitude of a voltage of the second power supply line. Second detecting means for detecting the first and second values, and the first detecting means, which is larger than a first predetermined value by the first detecting means.
When the magnitude of the voltage of the power supply line is detected and the magnitude of the voltage of the second power supply line larger than a second predetermined value is detected by the second detection means, A semiconductor memory device comprising: a power supply line; and switching means for disconnecting the second power supply line. 3. A first power supply line connected to a first internal circuit, a second power supply line connected to a second internal circuit, and a magnitude of a current consumption flowing through the first power supply line. Current consumption detecting means for detecting the power consumption, and when the current consumption exceeding a predetermined value is detected by the current consumption detecting means, the first power supply line and the second power supply line are connected. And a switching unit for disconnecting the first power supply line and the second power supply line when the magnitude of the current consumption detected by the current consumption detection unit is equal to or smaller than the predetermined value. apparatus. 4. A semiconductor memory device comprising: a plurality of power supply lines; and a fuse connecting at least two of the power supply lines. 5. A semiconductor memory device comprising: a plurality of power lines; and a plurality of power pads for connecting at least two of the power lines by wiring. 6. A semiconductor memory device having a normal operation mode and a test mode, wherein the test mode is generated by a first power supply line, a second power supply line, and an input timing of an external control signal. A semiconductor memory device comprising: a test mode detecting unit for detecting; and a switching unit for connecting the first power line and the second power line in the test mode detected by the test mode detecting unit. 7. A semiconductor memory device having a normal operation mode and a test mode, wherein the test mode is generated by a first power supply line, a second power supply line, and an input timing of an external control signal. A test mode detecting means for detecting, an external input terminal, and the first test mode detecting means detects the occurrence of the test mode and supplies a voltage exceeding a predetermined value to the external input terminal. A semiconductor memory device comprising: switching means for connecting a power supply line to the second power supply line. 8. When a voltage exceeding a predetermined value is supplied to a first power supply line, a second power supply line, an external input terminal, and the external input terminal, the first power supply line and the second power supply line Switching means for connecting the power supply line to the power supply line. 9. A semiconductor memory device having an internal circuit operated by an internal power supply voltage generated by an external power supply voltage, wherein said step-down means lowers said external power supply voltage; Switching means for supplying the internal power supply voltage to the internal circuit as the internal power supply voltage and, in a predetermined case, supplying the external power supply voltage to the internal circuit as the internal power supply voltage. 10. An external control signal input terminal further comprising: a plurality of external control signal input terminals, wherein when an external control signal is input to the external control signal input terminal at a predetermined timing, the switching means outputs the external power supply voltage to the internal power supply as it is. The semiconductor memory device according to claim 9, wherein the semiconductor memory device supplies a voltage to the internal circuit. 11. The switching device according to claim 9, further comprising an external terminal, wherein the switching unit supplies the external power supply voltage as it is to the internal circuit as an internal power supply voltage according to a voltage supplied to the external terminal. Semiconductor storage device. 12. A semiconductor memory device having an internal circuit that operates with an internal power supply voltage generated from an external power supply voltage, wherein the first voltage step-down step generates a first internal power supply voltage by lowering the external power supply voltage. Means, step-down means for stepping down the external power supply voltage to generate a second internal power supply voltage, and any one of the first internal power supply voltage, the second internal power supply voltage, and the external power supply voltage Switching means for selectively supplying the internal power supply voltage to the internal circuit as the internal power supply voltage. 13. The system according to claim 12, further comprising a plurality of external terminals, wherein said switching means switches a voltage supplied to said internal circuit as said internal power supply voltage according to a voltage supplied to said external terminals. Semiconductor storage device.