JPH1023247A - Image processor and image-processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output processed image, stored in an image memory in the unit of fields in real time and to prevent image deterioration resulting from image processing for each field. SOLUTION: Data corresponding to a zoom magnification, an offset selected by a 1st selector 100 or a fraction part outputted from an adder 102 are given to the adder 102, and a part of the result of arithmetic operation which is integers is given to an address counter 104. The count of the address counter 104 is incremented by 2 or 4, depending on the received integral part, and when no integral part is received, a 2nd selector 110 selects an output of an adder 106 summing the count and '1', and when the integer part indicates '2', the 2nd elector 110 selects an output of a subtractor 108 which is a sum of the count and -1, and when the integral part indicates '1', the count is selected and the selected value is outputted as a vertical read address of the image memory 16 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing method for performing electronic zoom processing for electronically reducing and enlarging a digital video signal, and more particularly to an interlaced video signal in units of fields. The present invention relates to an image processing device and an image processing method for performing image processing.

[0002]

2. Description of the Related Art An image pickup apparatus such as an electronic camera, a movie, and a scanner for capturing an image of a subject and recording or outputting a corresponding video signal on a recording medium, and a reproducing apparatus, display the captured and recorded image on a television (TV) screen. There are those that output in real time. It is expected that such a device is equipped with an electronic zoom function for electronically and continuously enlarging and reducing an image, particularly for consumer equipment.

On the other hand, a video signal in a normal television is
TV signals of interlaced (interlaced) scanning method such as NTSC standard or PAL standard are adopted, and the TV is output in real time by performing image processing such as zooming and correction on the field image unit for each field image. Display the video on the screen.

A patent application filed by the present applicant, Japanese Patent Application No. 6-8686
In No. 3, real-time processing cannot be performed, but the image signal stored in the first image memory is read out, electronic zoom processing is performed in small block units, and the processed image is stored in the second image memory. Discloses a "digital image processing apparatus" that can display a high definition image on a monitor TV.

[0005]

However, when image processing such as reduction or enlargement is performed by thinning or interpolating in units of field images, the number of pixels in the vertical direction (the number of scanning lines in the horizontal direction) is reduced by half. Since the image whose information is reduced by half in the direction is individually processed, there is a problem that the image quality in the vertical direction is significantly deteriorated. In particular, the image processed for each field image is referred to as T
When displaying on the V screen, one screen is composed of two separately processed field images, so that a consistent processed image may not be obtained as one screen.

More specifically, when an image enlarged or reduced for each field is displayed on an interlaced scanning type TV monitor, an image of each scanning line of two fields is displayed for each field within a predetermined time. When one image is viewed as one screen, a horizontal line in order from the top is displayed upside down (back and forth), or an image of a horizontal line that is farther apart from the horizontal line next to the image of a certain horizontal line is displayed. Or be displayed. As a result, there is a problem in that an unnatural image is displayed on the playback screen as a result of performing the electronic zoom processing on the image.

For this reason, it is conceivable to perform image enlargement or reduction processing on a frame basis to prevent image deterioration. However, in the processing in units of frame images, for example, it is speedy to process a stored image in a frame memory composed of a DRAM (Dynamic Random Access Memory) in real time and sequentially output each screen to a TV monitor. Have difficulty. Also, in this case, many memory elements for storing field images are required, and this is not practical because many memory elements are required to reduce the cost, which causes a cost increase. .

The present invention solves the above-mentioned drawbacks of the prior art, and can process and process a field image stored in an image memory in a time unit of the field and output the image in real time. It is an object of the present invention to provide an image processing apparatus and an image processing method capable of preventing image deterioration caused by image processing.

[0009]

According to the present invention, in order to solve the above-mentioned problems, image signals representing a desired image are sequentially stored in a storage means, and the stored image signals are read out by reduction or enlargement processing. In an image processing apparatus that outputs an image signal by interlaced scanning, the apparatus includes an input unit that inputs an image signal and stores the image signal in a storage unit, and a process that reads the image signal stored in the storage unit in accordance with the interlaced scanning. Means for outputting an image signal read from the storage means, and the processing means generates and stores an address signal designating a read address for reading the image signal stored in the storage means. Address control means for supplying read means for one vertical field in interlaced scanning.
An address signal for specifying a line of another field different from the field under the read address generation processing is generated according to magnification data for specifying a magnification for reducing or enlarging an image.

[0010] In this case, the address control means is based on magnification data for generating a read address and a reference position sequentially updated from the image end position of each field.
A first calculating means for calculating an integer part representing a line interval equal to or more than the line distance at the same magnification and a decimal part representing a line interval less than the line distance, and a calculation result of the first calculating means, Counting means for counting a value corresponding to the value of the integer part; address correction means for outputting, as an address signal, a value obtained by correcting the output value of the counting means according to the value of the integer part obtained by the first arithmetic means; May be included.

In this case, the address correcting means further comprises:
A second arithmetic means for correcting the count value from the counting means to a read address designating a line of the other field with respect to the field under the read address generation processing, and an output of the second arithmetic means according to the value of the integer part And selecting means for outputting the selected value as an address signal to the storage means.

The input means stores the image signal in the storage means in the order of frames, and the address correction means stores the output value of the counting means in correspondence with the previous or next line in the processing order in the frame order represented by the output value. It is preferable to correct the read address to be read.

The input means stores the image signal in the storage means in the order of fields, and the address correction means stores the output value of the counting means in the other field corresponding to the processing line in the field order represented by the output value. It is preferable to correct the read address of the line.

The address control means includes offset means for specifying a line position to be processed in the virtual address space, and the first arithmetic means uses the position specified by the offset means as a reference position, It is good to calculate the decimal part.

In this case, the processing means has means for generating background data for arranging a background image around the processed image represented by the image signal read from the storage means, and the output means is generated by the address control means. The background data may be output according to the read address to be read.

Preferably, the processing means includes a pixel value calculating means for interpolating and outputting the image signal read from the storage means.

In this case, the pixel value calculating means may interpolate and output the image signal read from the storage means using the calculation result of the first calculating means.

The address control means includes address generation means for generating a horizontal address for the image, and generates and stores a read address for reading each pixel on a line corresponding to the generated vertical read address. It may be supplied to the means.

Further, according to the present invention, in order to solve the above-mentioned problems, image signals representing a desired image are sequentially stored in a storage means, and the stored image signals are read out by reducing or enlarging the image signal to perform interlaced scanning. In the image processing method of outputting an image, the method adds a value indicating a reference position of each line in a vertical direction of a screen to be processed, and magnification data set in accordance with reduction or enlargement of an image. If the result indicates that the distance exceeds the line distance at the same magnification, the count value of the counting means for generating a read address for the storage means is counted up according to the addition result, and the addition result indicates twice the distance between the lines. In such a case, the count value is corrected to a read address that is one line before the line indicated by the count value of the counting means and specifies the line of the other field, and this correction result is obtained. It may be output as a read address in the vertical direction with respect to 憶 means.

In this case, in this method, when the addition result does not exceed the distance between the lines at the same magnification, the counting means is not incremented, and the reading is performed to designate the line next to the line indicated by the current count value. The count value may be corrected to the address, and the result of the correction may be output as a vertical read address for the storage means.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an image processing apparatus and an image processing method according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 2, there is shown an embodiment of a film scanner device 10 to which the present invention is applied. The apparatus 10 periodically reads an image recorded on a silver halide photographic film 12, sequentially converts the read image into field-based image signals, performs digital zoom processing on the image signals, and processes the processed image signals. Is an image input and image processing apparatus for displaying an image corresponding to.

The image processing apparatus 10 according to the present embodiment has an electronic zoom processing function of reading out digital image signals sequentially stored in the image memory 16 in units of fields in the horizontal and vertical directions, in real time. ,
In particular, in the reduction and enlargement processing in the vertical scanning (V) direction of the screen, an image equivalent to the image processed in frame units is displayed on the monitor TV14. This monitor TV14
Is detachably connected to the output terminal 18 of the device 10,
Further, the video signal of the NTSC system or the PAL system supplied in the interlace system of one screen and two fields (2: 1) is displayed on a display device such as a cathode ray tube or an LCD (Liquid Crystal Display). In the following description, parts not directly related to the present invention are not shown and described, and reference numerals of signals are represented by reference numerals of connection lines in which the signals appear.

In this embodiment, the image displayed on the monitor TV 14 is an image pickup device for picking up an image formed on the film 12.
(CCD) 20. Specifically, the device 10 is a film
An imaging lens 22 that forms a recording image formed on 12 is disposed in front of the imaging surface of the imaging device 20.
The position of the lens 22 is controlled so that the recorded image is focused on the imaging surface of the imaging device 20. In the example shown in FIG.
The position where 12 is transported, that is, the lens 22 and the image sensor 20
Further, a light source 24 is provided as a lighting device for irradiating the film 12 with light, further in front of the imaging range by. This illumination light transmits the image formed on the film 12 and passes through the lens 22.
Is projected on the imaging surface of the imaging device 20 via the.

The driving of the light source 24, the conveyance of the film 12, and the position control of the lens 22 are controlled and driven by driving means 26a, 26b and 26c, respectively, which are conceptually shown by broken lines in FIG. For example, when the light source 24 is a fluorescent lamp, the driving unit 26a turns on the fluorescent lamp at a high frequency so as not to cause an adverse effect such as flicker on the captured image. Further, the driving means 26b is used to transfer a desired recorded image portion of the film 12 stored in the cartridge 27 to the lens 22 and the image pickup device 20.
Is moved to the field position determined by. Further, the driving means 26c adjusts the focus by moving the lens 22 back and forth. As described above, the scanner device 10 according to the present embodiment constitutes a transmission type image input device, but the present invention is not limited to this, and may be a reflection type. For example, the light source 24 may be provided on the imaging surface side of the film 12, and the lens 22 and the imaging device 20 may be configured to capture the reflected light from the subject. In this case, instead of the film 12, it is possible to image a subject such as another image recording medium such as a photographic print or a printed original, or actual scenery.

The film 12 in this embodiment is a developed silver halide photographic film in the form of a roll film housed in a cartridge 27 so as to be drawn out. Images of a plurality of frames corresponding to the photographing are recorded and formed on the film 12, and basically, the image for each frame is captured by the image sensor 22. Of course, the film 12 may be a sheet film on which one frame of image is recorded for each frame, a mount state fixed to a slide frame for each frame, or a carrier for holding the film 12 cut for a plurality of frames. May be set.

An image pickup device (CCD) 20 for picking up an image recorded on the film 12 is a solid-state image pickup device for outputting a color pixel signal corresponding to an image exposed on the image pickup surface. The image sensor 22 in the present embodiment is a CCD (Charge Coupled
vice) or a two-dimensional image sensor or a one-dimensional line sensor. An image pickup surface of the image pickup device 22 is provided with, for example, an RGB color filter for dispersing each color component, and the incident light from the lens 22 passes through the filter and reaches a light receiving unit on the image pickup surface. The image sensor 20 has its control input 20
In response to drive signals such as a horizontal charge transfer pulse and a vertical charge transfer pulse that are input to 0, a charge corresponding to the amount of received light is generated, and an interlaced three-primary color image signal corresponding to the charge is generated in each field. Output 20 for each of a and b
Output to 2. Between the image sensor 20 and the light source 24, for example, the base color of the film 12 is used as a correction filter for limiting the transmission amount of a specific spectral component of the illumination light so that the captured image has an appropriate color balance. A color filter to be corrected may be provided.

The drive circuit 28 connected to the control input 200
A drive signal such as a horizontal and vertical charge transfer pulse for driving the image sensor 20, various biases, and a vertical synchronization signal VD is generated and supplied to the control input 200 of the image sensor 20. The drive circuit 28 receives these drive signals 200 based on a reference clock supplied from a general control unit (CPU) 30 via a connection line 203.
Generate

The output 202 of the image sensor 20 is connected to an amplifier 31. The amplifier 31 clamps the DC level of the image signal input to the input 202 to a predetermined level, and converts the image signal to a level corresponding to the output destination. This is a gain control amplifier that amplifies the current. The output 204 of the amplifier 31 is connected to an analog / digital (A / D) conversion circuit 32, and the A / D conversion circuit 32
Samples the RGB image signal appearing at the input 204 in synchronization with the timing signal input to the input 206, and converts the value to a digital value. The level of the signal input to the A / D conversion circuit 32 is adjusted by the amplifier 31 so as to appropriately fall within the input voltage range of the A / D conversion circuit 32. A / D
The conversion circuit 32 outputs the digital image signal after the conversion processing in bit parallel to an output 208 to which the signal processing device 34 is connected. As described above, an image input device that reads an image recorded on the film 12 using the image sensor 20, the lens 22, the light source 24, and the amplifier 31, and generates a color image signal corresponding to the image is formed.

The signal processing device 34 is a digital signal processing circuit including a white balance adjustment circuit for adjusting the white balance of the digital image signal input to the input 208, a gamma correction circuit for correcting a gamma characteristic, and the like.
As shown in FIG. 3, the signal processing device 34 receives the white balance adjustment and the gamma correction which are input to the input 210.
The image signal processing circuit 300 includes a video signal processing circuit 300 for converting an RGB image signal into YC image data formed by a luminance signal Y and a color difference signal C. The video signal processing circuit 300 is constituted by a predetermined matrix operation circuit and the like. You. Video signal processing circuit
The output 304 of 300 is connected to the electronic zoom processing circuit 302,
The electronic zoom processing circuit 302 converts the YC image data input to the input 304 into an image memory (DRAM) 16 connected to the connection line 210a.
It has a memory control function for accumulating data in the memory. The electronic zoom processing circuit 302 is a memory control circuit that controls writing and reading of YC image data to and from the image memory 16, and in particular,
Basically, an electronic zoom process for reading out image data stored in the image memory 16 by reducing and enlarging it in units of each field is realized. The image memory 16 is a randomly accessible image memory having a storage capacity for storing at least one frame of YC image data converted into YC data. The image memory 16 in the present embodiment is a one-chip DRAM (DRAM).
Dynamic Random Access Memory). The electronic zoom processing circuit 302 supplies a write and read address for writing and reading image data and various memory control signals to the image memory 16 based on a clock signal from the overall control unit 30 input to the input 212. And generate The electronic zoom magnification in this embodiment is from 1/2 to 2
Although it is a range of magnification, it is possible to expand to a magnification outside this range.

An output 306 of the electronic zoom processing circuit 302 is connected to an encoder circuit 308. The encoder circuit 308 converts the image data for each field read from the image memory 16 into an NTSC video signal (NTSC composite signal). NTSC encoder. The encoder circuit 308
A matrix circuit for calculating a luminance signal and a color difference signal according to a predetermined arithmetic expression is included. The encoder circuit 308 may have a function of converting the image signal into a video signal of another interlaced scanning system such as the PAL system in accordance with the output destination of the image signal. The output 310 of the encoder circuit 308 constitutes the output of the signal processing unit 34, and this output 310 is connected to the digital / analog (D / A) conversion circuit 36 shown in FIG.

The D / A conversion circuit 36 is a circuit for converting a digital video signal appearing at the input 310 into an analog NTSC video signal in synchronization with a timing signal input to the input 206. The D / A conversion circuit 36 outputs the converted analog video signal to the output 214. The output 214 is connected to a terminal 18 constituting the output of the apparatus 10, and the terminal 18 is a connection terminal to which the monitor TV 14 is connected. The D / A conversion circuit 36
After converting the input digital image signal into an analog value, the analog image signal is blanked and shaped.
A sync signal and a color burst signal are added to the
An encoding function for generating a video signal may be provided.

The overall control section 30 is a control circuit for controlling each section of the image processing apparatus 10. The overall control unit 30 generates a reference clock as a reference for the operation of each unit and a drive signal for driving each unit. The overall control unit 30 according to the present embodiment performs control for imaging control such as feeding of the film 12 and signal processing based on operation information corresponding to an operation state of an operator detected by an operation unit (not illustrated). Generate signals and drive signals.
Further, the overall control unit 30 generates an instruction signal for instructing a zoom magnification corresponding to the reduction / enlargement ratio based on operation information corresponding to the image reduction / enlargement instruction, and outputs the signal processing device 34 via a connection line 212. To supply. Further, the overall control unit 30 generates a field discrimination signal for distinguishing the a field and the b field of the image to be zoomed, and supplies the signal to the signal processing device 34 connected to the connection line 212. These various signals are generated by a timing generator (not shown) provided in the overall control unit 30. The overall control unit 30 in this embodiment is constituted by a microprocessor unit (CPU), and generates a control signal and a drive signal for controlling each unit according to a processing program stored in advance in a storage unit (not shown). The overall control unit 30 is provided in an electronic zoom processing circuit 302 (FIG. 3), which will be described later. For example, the arithmetic processing function in the pixel value calculation unit 316 and the control unit 32
8 may be configured to include the control function.

Next, the detailed configuration of the electronic zoom processing circuit 302 will be described with reference to FIG. The electronic zoom processing circuit 302 in this embodiment includes a switch 312 for selectively switching between the connection line 304 and the connection line 310 and connecting to the connection line 210a. The switch 312 connects the output 304 of the video signal processing circuit 300 to the input 210a of the image memory 16 in accordance with the control signal given to the control input 314, and stores the YC image data in the image memory.
Supply 16 The switch 312 outputs the image data 210a read from the image memory 16 to the connection line 310 side in accordance with the control signal 314 as shown in the figure, and
Supply 316. It is preferable that the image memory 16 be constituted by a RAM having a switching terminal for input / output data. In this case, the control signal 314 is supplied to the image memory 16 and the connection line 304 is connected without passing through the switch 312. Directly connected to the input port of the image memory 16 and its output port
It is configured to be connected to the pixel value calculation unit 316 via 310.

The pixel value calculation unit 316 calculates the pixel value of each pixel read from the image memory 16 according to the zoom ratio representing the reduction ratio or the enlargement ratio of the image based on the image data input to the input 310. This is an interpolation processing unit. More specifically, as shown in FIG.
The pixel value of the input pixel 310 is calculated based on the interpolation coefficient k input to the input and the control signal input to the input 320. Specifically, the pixel value calculation unit 316 converts the input current pixel data b into 1H
A delay circuit 400a that delays by (horizontal scanning) by one line in the vertical scanning direction and further delays the pixel data a, the input pixel data b, and the interpolation coefficient k by the delay circuit 400a. make use of,

[0035]

[Equation 1] An arithmetic circuit for calculating the output pixel value Y by performing the arithmetic processing of Y = a (1-k) + bk
Including 402a.

As shown in FIG. 5, the pixel value calculation unit 316
Vertical interpolation processing circuit 316a that performs vertical pixel interpolation processing
And horizontal interpolation processing circuit that performs horizontal pixel interpolation processing
316b, and the vertical interpolation processing circuit 316a has a delay circuit 400a and an arithmetic circuit 402a. The horizontal interpolation processing circuit 31
6b includes a delay circuit 400b that delays the input pixel data b by one pixel in the horizontal scanning direction, and an arithmetic circuit 402b having the same configuration as the arithmetic circuit 402a described above. Figures (a) and (b)
As shown in (1), the order in which the pixel interpolation processing is performed in the horizontal and vertical directions may be first. The pixel value calculation unit 316 outputs the calculated value of the interpolation pixel to the output 322. Pixel calculator
The output of 316 is connected to one input of a switch 324 shown in FIG.

The switch 324 is a selection circuit that selects one of the input 322 and the other input 325 in accordance with a control signal input to the control input 326, and connects the selected input to the output 306. The input 322 of the switch 324 receives the pixel data after the zoom processing calculated by the pixel value calculation unit 316, and the input 325 receives, for example, background image data representing a peripheral image of the image reduced by the zoom processing. Is entered. Switch 324 outputs the image data appearing on the selected input to output 306. This output 306 constitutes the output 306 of the processing circuit 302 and is connected to the encoder circuit 308.

A control section 328 for outputting various control signals 314, 320 and 325 is a control circuit for controlling each section of the electronic zoom processing circuit 302. The control unit 328 in the present embodiment includes:
The switch 324 has a function of supplying background image data, and generates background image data for adding a background image of a specific color and / or pattern to a peripheral portion of an image reduced by the electronic zoom processing. The control unit 328 supplies the generated background image data to the input 325 of the switch 324.

The control unit 328 is a control circuit for controlling the electronic zoom processing function. More specifically, in order to perform electronic zoom processing for reducing or enlarging image data input to the electronic zoom processing circuit 302, the control unit 328
It has a function of outputting zoom magnification corresponding data corresponding to the reduction and enlargement ratio to an output 330a based on an instruction signal for designating the zoom ratio sent from the connection line 212 from FIG. 2 (FIG. 2). Further, the control unit 328 has a function of generating an image end position signal in the horizontal direction and the vertical direction synchronized with the timing at which the image end of the image stored in the image memory 16 is read, and outputting the signal to the output 330b. The processing start timing at the time of performing the zoom processing is determined by the image end position signal.

Further, the control unit 328 has a function of setting a storage area of the image memory 16 as a virtual address space, generating an offset signal indicating an offset position in the virtual address space, and outputting the signal to the output 330c. As shown in FIG. 7, the control unit 328 sets the origin of the image to be zoomed to (−320, −240) with the upper left end of the original image composed of, for example, 640 × 480 pixels as the origin (0,0). 1280 × 960
Processing is started at a virtual address where processing is performed as a pixel image. As a result, as shown by oblique lines on the right side of the figure, an image having a reduction ratio of about 0.5 times is obtained in a screen composed of, for example, 640 × 480 pixels. The control unit 32
8 is to correct the generated offset so that the center of the image after the zoom processing does not shift.

Further, when reading the image data stored in the image memory 16 as the b field, the control unit 328 outputs a value obtained by correcting the offset value of the a field as the offset value of the b field. That is, assuming that the offset value of the a field is the offset a, the offset b of the b field is

[0042]

## EQU2 ## Offset b = offset a + 1/2 (current zoom magnification-zoom magnification at the same magnification).

Here, the zoom magnification at the time of equal magnification is a value where the distance between lines in the vertical direction is 2 ⁸ = “256”. Therefore, when the zoom magnification is set to about 0.7 times ("360"), the value "128" of the offset a is corrected, and the offset b becomes the value "180". The field discrimination signal for distinguishing between the a-field and the b-field is supplied from the overall control unit 30 (FIG. 2) to the control unit 328 via the connection line 212.
The current processing field is recognized based on this field discrimination signal.

Returning to FIG. 3, the control unit 328 includes a clock signal CLK as a reference for calculating an address in the address control unit 332, and a reset signal for initializing the calculated address.
RESET is generated and output to outputs 330d and 330e, respectively. The control unit 328 transmits these generated control signals to the connection line 33.
The address is supplied to the address control unit 332 connected via 0.
Further, the control unit 328 generates a memory control signal such as a chip selection signal and a write instruction signal for controlling writing and reading of image information in the image memory 16, and transmits the generated control signal to the image memory 16 via the connection line 210c. Supply.

The address control section 332 is a control section for generating address information for designating a storage address of the image memory 16. The address control unit 332 generates a write address and a read address of the image memory 16, and supplies the generated address information to the image memory 16 via the connection line 210b.

The write address generation processing in this embodiment is performed, for example, as shown in FIG.
Image data of two fields, i.e., a field and a b field, are mapped to alternate horizontal scanning lines in the frame order, and a write address signal for storing the image data in the address of the image memory 16 is generated. In this case, as shown in the figure, a write address signal is generated in which the line numbers in the frame order of the horizontal lines of the image correspond to the RAW addresses of the image memory 16. In the illustrated example, the even line including the 0th line is assigned to the a field, and the odd line is assigned to the b field. However, the present invention is not limited to this. For example, in an embodiment to be described later, a write address signal for mapping the image data of each field to the image memory 16 in the field order is generated.

Further, address control section 332 generates a read address designating a storage address of image memory 16 in which the image data is stored, and generates a read address for reducing and enlarging the image represented by the image data stored in image memory 16. It has a zoom processing function. In particular, the address control unit 332 in the present embodiment reads out the image data mapped in the frame order in the image memory 16 in the field correspondence in accordance with the interlaced scanning of the monitor TV 14. At this time, the address control unit 332 basically reads out the image data for each field similar to that at the time of image storage, but depending on the situation, transfers the image data of the horizontal line of the other field different from the field of the initially stored image. By generating a read address to be selected, image data for forming one high-quality screen is output from the image memory 16 by interlaced scanning.

The main configuration for generating the read address will be described. As shown in FIG.
Includes a first selector 100, an adder 102, an address counter 104, an adder 106, a subtractor 108, and a second selector 110. An address control unit 332 shown in the figure is an address generation circuit that generates a line address in the vertical scanning direction of an image. Although an address control circuit for generating an address in the horizontal direction of the image is not shown in the figure, for example, the output of the address counter 104 in FIG.
20 may be output at a pixel rate in the horizontal direction as a read address in the horizontal scanning direction.

The first selector 100 inputs the offset signal supplied from the control unit 328 to one input 330c, and sets the distance between pixels (lines) at the same magnification in the addition result of the adder 102 to "256". In this case, a fractional part (a value less than "256") representing the distance between pixels (lines) smaller than that is input to the other input 112, and the offset signal 330c and the decimal part 112 are input to the control input 330b. A changeover switch that selectively switches according to an input image edge position signal. In other words, the first selector 100 selects the input 330c and outputs the selected offset signal when an image edge position signal synchronized with the first line of each field is input to the control input 330b.
Output to 114. Further, when a significant image edge position signal is not input to the control input 330b, that is, when it is not the first line of each field, the first selector 100 selects the input 112 and outputs the selected decimal part 112 to the output 114. In this way, the first selector 100 updates and outputs the information indicating the reference position for generating the read address for each line.

The output 114 of the first selector 100 is
2 is connected to one input (Y) of input 2 and adder 102
4 is an arithmetic circuit that adds the offset 114 or the decimal part 112 input to 4 and the zoom magnification data input to the other input (X) 330a and outputs the result to the output (Z) 116. In the present embodiment, when the pixel-to-pixel distance at the same magnification is converted to a value of 2 ⁸ = 256, a value exceeding 8 bits (2 ⁸
<256 × n) is called an integer part, and a value up to 8 bits smaller than “256” is called a decimal part. Similarly, for the zoom magnification data, for example, a value of “360” indicates a reduced zoom magnification of about 0.7 times. When the zoom magnification data is, for example, a value "210", it indicates an enlarged zoom magnification of about 1.2 times.

The adder 102 outputs the integer part ("256") corresponding to the ninth bit of the addition result to the output 116a, and outputs the integer part ("512") corresponding to the tenth bit to the output 116b. I do.
These outputs 116a and 116b are used as address counters, respectively.
104 are connected to the first and second inputs. The connection line 112 from which the decimal part (d) of the output 116 of the adder 102 is output is connected to the input 112 of the first selector 100. A decimal part (d) is input to this input 112. Further, the decimal part (d) of the output 116 of the adder 102 is
2 is also supplied to the pixel value calculation unit 316 (FIG. 3).

The address counter 104 inputs a bit representing "256" to a first input 116a, a bit representing "256" .times.2 = "512" to a second input 116b.
This is a counting circuit for incrementing (counting up) a value corresponding to a, 116b. Specifically, the address counter 104
When the ninth bit integer part "256" is input to the first input 116a, the count value is incremented by "2". When the integer part "512" of the tenth bit is input to the second input 116b, the count value is counted up by "4". Address counter 104
Starts counting in response to an image edge position signal input to the input 330b, and outputs a counting result according to the clock CLK input to the input 330d. Also, the address counter 104
The count result is initialized to 0 according to a reset signal input to the input 330e for each screen. Address counter 104
Calculates the count value by an adder 106, a subtractor 108, and a second selector 11
0 is output to the output 120 to which it is connected.

Adder 106 converts the value appearing at input 120 to "
Is an arithmetic circuit that adds 1 "to the output 122. That is, the adder 106 corrects the address indicated by the input value and specifies the address of the next line.
Numeral 8 denotes an arithmetic circuit for subtracting "1" from the value appearing at the input 120 and outputting the result to the output 124. That is, the subtractor 108
Modifies the address indicated by the input value and specifies the address one line before the address. As described above, the adder 106 and the subtracter 108 have a function of converting the current field address into the address of the other field. The outputs 122 and 124 of these arithmetic circuits are respectively connected to a second selector 110, and the second selector 110 outputs the first output 11 of the adder 102.
A selection circuit for selectively selecting the input according to the integer part output from 6a and the second output 116b.

More specifically, the second selector 110 is connected to the adder 102
Are connected to the control input (SEL), respectively. When the bit (9th bit) indicating the value "256" output from the adder 102 is input to the control input (SEL) 116a, the input 120 And the value "5" output from the adder 102 is selected.
The bit (bit 10) indicating 12 "is the control input (SEL) 116b
Is input, the input 124 is selected. Second selector 110
Selects input 122 when these integer parts are not input. The second selector 110 connects the selected input to the output 210b and outputs the value appearing at the selected input as a read address to the image memory 16 to the output 210b to which the address input of the image memory 16 is connected. This output 210b constitutes the output of the address control circuit 332. In this way, the second selector 110 determines the read address for reading the image data of the next line from the image memory 16 according to the interval, that is, the distance between the horizontal scanning lines. At this time,
A predetermined line in a field different from the field currently being read is set to a value "25" determined according to the distance between lines
6 "or the value" 512 "(the 9th and 10th bits of the output of the address counter), and the image data of the determined horizontal scanning line can be read.

The operation of the film scanner 10 in the present embodiment having the above-described configuration will be described. First, the device 10
Is loaded with the cartridge 27 of the film 12, and the image of the desired frame is loaded to the position of the scene. the film
The image formed on 12 is projected on the imaging surface of the imaging device 20,
A pixel signal corresponding to the recorded image is read out by interlaced scanning in units of fields in accordance with the drive signal supplied from the drive circuit 28 to the image sensor 20. The pixel signal 202 is supplied to the amplifier 31
After the signal is amplified to a predetermined level at the A / D converter circuit
The signal is converted into a digital image signal according to the timing signal supplied to 206.

The image signal is input to the video signal processing circuit 300 of the signal processing device 34, converted into YC image data, and supplied to the image memory 16 through the electronic zoom processing circuit 302. At this time, the control unit 328 of the electronic zoom processing circuit 302 switches the connection of the switch 312 so as to select the connection line 304 opposite to that shown in the figure, and the image data output from the switch 312 is input to the image memory 16. . At the same time, a memory control signal 210b such as a write address signal for mapping this image data in frame order is supplied from the address generation unit 332 of the control unit 328 to the image memory 16, and the image data output from the video signal processing circuit 300 is The image data is sequentially stored at the addresses in the line order of the image memory 16 shown in FIG.

FIGS. 10 and 11 show the electronic zoom processing when the image data for one screen, in which the line numbers of the scanning lines are mapped in the RAW address order of the image memory 16 in a reduced or enlarged manner, is read out. This will be described below with reference to FIG. First, the electronic zoom processing circuit 302 initializes each part thereof before processing (step 1000).
The zoom factor corresponding data corresponding to the instruction signal 212 generated by the operation unit (not shown) is generated by the control unit 328 (step 1002). Here, for example, zoom magnification data "360" (0.7 ≒ 256/360) to reduce the image to about 0.7 times
And zoom magnification data for enlargement to about 1.2 times
0 "(1.2 ≒ 256/210) is set, and the generated zoom magnification data is supplied to the adder 102 via the connection line 330a. Further, in accordance with the instruction signal input to the input 212 of the control unit 328, Then, the zoom start position is set to the center or an arbitrary position (step 1004) In step 1006 where the zoom start position is set to the center and step 1008 where the zoom start position is set to the arbitrary position, the processing start address / offset value is set. The calculated and generated address offset values are supplied to the first selector 100 via the connection line 330C.

Next, the routine proceeds to step 1010, where it is determined whether or not V blanking has been detected. If the current period is a blanking period, the routine proceeds to step 1012, and if it is a video period, the routine proceeds to step 1014.

When the process proceeds to step 1012 in which the blanking period is determined in step 1010, the address counter 104 is preset to an address offset value corresponding to the zoom start position. Is determined based on the field determination signal.

In the case of the read address generation processing for the a field, the process proceeds to step 1018, where the offset value a (for example, "128") is preset in the adder 102. Thereafter, it is determined in step 1022 whether the line being processed is the last of the screen, and if it is the last line (YES).
In step (480th line), the flow returns to step 1002 to perform processing for the next screen. If there is a next line, the process returns to step 1010. Further, in the case of the read address generation processing for the b field, the offset b
(For example, "180" = 128 + 1/2 (360-256)) is preset in the adder 102, the count value of the address counter 104 is counted up by "1", and the process returns to step 1010.

In step 1014, which is determined to be the image period in step 1010, H blanking is further detected. When the image period becomes one horizontal scanning period in which H blanking is completed, the process proceeds to step 1024, and zooming is performed. The scaling factor data and the output 114 of the first selector 100 are added. In this case, particularly in the case of the first line of the field, the offset signal input to the input 330c is output to its output 114 by the image end position signal 330b supplied from the control unit 388 to the first selector 100, and is output to the adder 102. The respectively input offset value and zoom magnification data are added.
When processing other lines, the output 112 (decimal part) of the adder 102 selected by the first selector 100 and the zoom magnification corresponding data are added.

Then, the process proceeds to a step 1100, wherein the address counter 104 detects whether or not the higher-order ninth or tenth bit corresponding to the integer part of the addition result in the adder 102 has occurred. If these integer parts are not detected in step 1100, the process proceeds to step 1104, where the count value of the address counter 104 is not updated and its output 120
Is output to This count value is input to the adder 106, and the value obtained by adding "1" to the count value is input to the second selector 110 (step 1106). At this time, the second selector 110
Since the integer part is not input to the control input 116, the signal input to the input 112 is selected. As a result, the output of the adder 106 is output from the output 210b of the second selector 110 (step 1108). ).

In step 1102 when the integer part is detected in step 1100, the generated value is "256".
Step 11 when the integer part (9th bit) corresponding to
Proceed to 10, and the integer part corresponding to "512" (10th bit)
If so, the process proceeds to step 1112. When the integer part is detected, the address counter 104 counts up according to the value. Specifically, when the integer part 116a ("256") is input to the address counter 104, the current count value becomes "2".
The count is incremented (step 1110), and the counted value is output from the address counter 104.
At this time, the second selector selects the input 120 in response to the ninth bit integer part input to the control input, and the count value output from the address counter 104 is stored in the image memory 16.
Is output from output 210b as a read address for (steps 1114 and 1108).

In step 1102, the integer part 116b
("512") is detected by the address counter 104, the current count value is counted up by "4" (step 111).
2), the counted value is the address counter 1
Output from 04. The output count value 120 is subtracted by the subtractor 108
And a value obtained by subtracting "1" from the count value is output to its output 124 (step 1116). At this time, the second selector 110 selects the input 124 in response to the 10-th integer part input to the control input 116b, and
8 is output from the output 210b of the second selector 110 (step 1108). The values output from the second selector 110 in step 1108 are stored in the image memory 16 respectively.
Is supplied to the image memory 16 as a read address of the screen in the vertical (V) direction.

When the memory address is output in step 1108, the process returns to step 1010 to continue the subsequent processing. On the other hand, it is determined whether the output memory address is a negative value (step 1118). If the memory address is a negative value, the process proceeds to step 1120, where the background color data output from the control unit 328 is output. 325 is selected by the switch 324 and output to the output 306. When the memory address is a positive value, the read address is further stored in the image memory 16.
Is determined to be within the real address of the image memory 16, and if the generated memory address exceeds the real address of the image memory 16, the background color data 325 is similarly output from the control unit 328.

When the generated memory address is the real address of the image memory 16, various control signals for accessing the image memory 16 are supplied to the image memory 16, and the generated vertical read address and the horizontal read address are supplied. One line of image data corresponding to the read address in the direction is sequentially read (step 1124). The read image data is input to a pixel value calculation unit 316 through a switch 312, and the pixel value of each pixel is calculated by a decimal part functioning as an interpolation coefficient, and the interpolated image data is output through a switch 324. It is input to the encoder circuit 308. The image data input to the encoder circuit 308 is NT
A signal processing circuit that is sequentially converted to SC video signal data
The signal is output to an output 310 at 34 and further converted to an analog signal by the D / A converter 36. The analog video signal is input to the monitor TV, and a corresponding one-line image is displayed on the display screen.

The read address generation process in the horizontal direction is shown in FIG.
As shown in FIGS. 12 and 13, portions denoted by the same reference numerals shown in FIGS. 10 and 11 may be subjected to similar processing. Here, the processing of steps 1000 to 1010 is performed, and if a blanking period is detected in step 1010, step 12 is executed.
Proceeding to 00, the loop of steps 1010 and 1200 is repeated during the blanking period, and returns to step 1002 when it is time to process the next screen. Step 1010
In the video period after the blanking period, the process proceeds to step 1014. During the detection of H blanking, the process proceeds to step 1214.
At 02, the address counter and the offset value are preset.

When the image period of the horizontal scanning period is reached,
Proceeding to 1024, the offset value or the output (decimal part) of the adder 102 is added to the set zoom magnification corresponding data, and when the integer part of the addition result is generated, it is supplied to the address counter 104. When this integer part is detected in step 1100, the process proceeds to step 1102, and if the integer part represents "256", the address counter 104 is counted up by "1" in step 1204. If the integer part represents "512", the address counter 104 is incremented by "2" at step 1206. If these integer parts are not detected, the address counter 104
The process proceeds to step 1208 without counting, and the output of the address counter 104 is output as a read address for the image memory 16 in the horizontal scanning direction.

Thereafter, similarly to the flow shown in FIG.
Each pixel in the horizontal direction on the line addressed in the flow of FIGS. 10 and 11 is read from the image memory 16. Also at this time, in steps 1118 to 1120,
When the generated read address is a negative value or a real address of the image memory 16, the background color data is selected and output.

When the horizontal address generation for one line is completed in this manner, the next vertical address generation processing is started. The address generation for specifying the address of the line in the subsequent horizontal scanning period is performed in the same manner as in step 10.
In the video period after the detection of the H blanking period in 14,
The zoom magnification data and the decimal part already output from the adder 102 are added by the adder 102, and the address counter
Supplied to 104. Therefore, step 11 is performed according to the bits (116a, 116b) representing the integer part values "256", "512", respectively.
The process proceeds to 00 or step 1112, and the address counter 104 is incremented according to the value of the integer part (step 1110 or 1111).
12). If the integer part is not detected, step 11
In step 04, the address counter 104 is not updated, and the adder 106 adds "1" to the current count value and outputs the result.

As described above, the generated read address in the vertical (V) direction is, for example, in the first field (a field) after the reduction processing as shown in FIG. Following the 0th line and the 2nd line, it is the address information for reading the 5th line. The fifth line before the processing is a line of the second field (b field) before the processing. Similarly, in the second field (b field) after the processing, an address for reading the fourth line following the first line before the processing is generated. The fourth line before this processing is the line of the first field.

Each line after zoom processing is designated by the read address generated in this way, and when the read image is displayed on the monitor TV 14 as viewed on a single screen basis, it is shown on the right side of FIG. Thus, the 0th, 1st,
2, 4, 5, 7, 8, 9, 11,... Lines are displayed, the distance between lines (the distance between pixels in the vertical direction) is a maximum (2), and the lines are in a large state. That has been prevented. Therefore, a natural pattern can be obtained.

However, in the example of reduction of each field according to the conventional method, as shown in FIG. 21, for example, when the processed image is viewed on a screen basis, the 0th, 1, 2, 5,.
6, 7, 8, 9, 12,... Lines are displayed, and the maximum line-to-line distance becomes (3). As a result, the degree of inconsistency as one screen increases. Therefore, the displayed image could not be said to be good.

Further, at the time of enlargement in the above embodiment, FIG.
As shown in the figure, in the first field (a field) after the processing, the read address for reading the fifth line following the 0th line, the 2nd line, and the 4th line of the first field before the processing is Generated. The fifth line before the processing is a line of the second field (b field) before the processing. Similarly, in the second field (b field) after the processing, the first line, the third line,
Following the fifth line, a read address for reading the sixth line is generated. The sixth line before the processing is a line of the first field (a field) before the processing.

Each line after zoom processing is designated by the read address generated in this way, and when an image from the image memory 16 is displayed on the monitor TV 14, one line is displayed.
When viewed on a screen-by-screen basis, as shown on the right side of the figure, the images of the 0th, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8,... Line inversion does not occur in screen units. However, in the example of the conventional method,
As shown in FIG. 23, the displayed line is the 0th,
1, 2, 3, 4, 5, 4, 5, 6, 7, ...
The upper and lower sides (front and rear) of the display line in one screen unit are reversed, and the image after the electronic zoom processing has an unnatural picture.

In the horizontal image, the horizontal pixel position does not shift left and right in each field constituting one screen. There is no adverse effect due to the processing (see FIGS. 24 (a) and (b)).

Next, an image processing apparatus 10b for storing image data in the image memory 16 by field mapping and storing the image data and performing electronic zoom processing on the image data will be described below. The image processing device 10b according to the present embodiment includes:
A control unit 328b and an address control unit 332b shown in FIG. 15 are provided instead of the control unit 328 and the address control unit 332 in the electronic zoom processing circuit 302 of the embodiment shown in FIG. The other configuration of the image processing device 10b may be the same as the configuration shown in FIGS. 1 and 2, and the description thereof will be omitted.

In the address control section 332b shown in FIG. 15, adders 150 and 152 and subtractors 154 and 156 are connected to the output 120 of the address counter 104b, respectively. Connected to selector 110b. First, the address counter 104b in this embodiment counts up “1” when the integer part “256” output from the adder 102 is input to the input 116a, and “2” when the integer part “512” is input to the input 116b. "It is configured to count up.

The adder 150 is an arithmetic circuit for inputting the count value 120 of the address counter 104b and adding "256" thereto, and the subtracter 154 is for calculating the count value 12 of the address counter 104b.
This is an arithmetic circuit that inputs 0 and subtracts "255" from it. The adder 152 is an arithmetic circuit for adding "255" to the count value 120 of the address counter 104b.
Is an arithmetic circuit for subtracting "256" from the count value 120 of the address counter 104b. As described above, the adders 150 and 152 in the field-mapped embodiment correct the output value of the address counter during the processing of the a-field and output the memory address specifying the line of the other b-field. Having. Also, the subtractor 154 and
Reference numeral 156 has a function of correcting the output value of the address counter during the processing of the b field and outputting a memory address designating the other line of the a field. The outputs 158, 160, 162, 164 of the arithmetic circuits 150 to 156 are connected to the second selector 110b.

The second selector 110b compares the outputs of the adder and the subtractor with the integers 116a and 116b of the signal 116 output from the adder 102 and the field supplied from the controller 328b via the connection line 330f. Switching is selected based on the discrimination signal, and is connected to the output 210b. The second selector is 11
0b is input when the current processing field is the a field based on the field discrimination signal input to the input 330f when the integer part indicating the value "512" is input to the control input 116b.
160 is selected, and input 164 is selected for the b field. When the integer part indicating the value “256”, “512” is not input to the control input 116 (no carry bit), the second selector 110b determines the value of the “a” field based on the field determination signal input to the input 330f. When input 158 is selected,
Select input 162 for b field. The second selector 110b selects the input 120 when an integer part indicating the value "256" is input to the control input 116a. Second selector
110b connects these selected inputs to the output 210b, and outputs the output of the address counter 104b or a value obtained by adding or subtracting a predetermined value to or from the output value thereof as a vertical read address signal to the image memory 16.

The operation of the image processing apparatus according to the present embodiment having the above configuration will be described below with reference to FIGS. In the following description, the horizontal address generation processing may be the same processing as the above-described processing (FIGS. 12 and 13). In the field mapping, for example, as shown in FIG. 14, the image of each field is mapped in the order of addresses in the image memory 16. As shown in the figure, in this mapping process, each line of the field a, that is, even lines (0th line to 48th) as one screen
The write address is generated such that the image data of each (even line of the 0th line) is sequentially stored in the addresses 0 to 240 of the image memory 16. Further, a write address is generated such that image data of each line of the b field, that is, an odd line (each odd line of the first line to the 479th line) is sequentially stored in addresses 256 to 496 of the image memory 16. You.

Electronic zoom processing when image data read out from the image pickup device is stored in two areas of the image memory 16 in the order of fields and image data for one screen is reduced or enlarged and read out. This will be described below with reference to FIGS.

First, each part of the electronic zoom processing circuit 302 is initialized (step 1600) prior to processing, and then data corresponding to zoom magnification corresponding to an instruction signal 212 generated by an operation unit (not shown) is generated. It is generated by the control unit 328 (step 1602). Here, for example, zoom magnification corresponding data "360" (0.7 ≒ 25
6/360) and zoom magnification corresponding data "210" (1.2 / 256/205) for enlargement to about 1.2 times are set, and the generated zoom magnification corresponding data is supplied to the adder 102 through the connection line 330a. Is done. Further, the zoom start position is set to the center or an arbitrary position according to the instruction signal input to the input 212 of the control unit 328 (step 1604). In step 1606 in which the zoom start position is set at the center or in step 1608 in which the zoom start position is set at an arbitrary position, a processing start address / offset value is calculated, and the generated address / offset value is stored in the first line via the connection line 330C. It is supplied to the selector 100.

Next, the routine proceeds to step 1610, where it is determined whether or not V blanking has been detected. If the current period is a blanking period, the routine proceeds to step 1612, and if it is a video period, the routine proceeds to step 1614.

At step 1610, when the blanking period is determined and the routine proceeds to step 1612, the address counter 104b is preset to an address offset value corresponding to the zoom start position. At subsequent step 1616, the current field is set to a
It is determined whether the field is a field or a b field.

In the case of the read address generation processing for the a field, the process proceeds to step 1618, where the offset value a (for example, “128”) is preset in the adder 102. Thereafter, it is determined in step 1622 whether the line being processed is the last of the screen, and if it is the last line (YES).
In step (480th line), the flow returns to step 1602 to perform processing for the next screen. If there is a next line, the process returns to step 1610. Further, in the case of the read address generation processing for the b field, the offset b
(For example, "180" = 128 + 1/2 (360-256)) is preset in the adder 102, and the count value of the address counter 104b is counted up by "1", and the process returns to step 1610.

In step 1614, which is determined to be the video period in step 1610, H blanking is further detected. When the video period of one horizontal scanning period in which H blanking has been completed is reached, the process proceeds to step 1624, where the zoom magnification The data and the output 114 of the first selector 100 are added. In this case, particularly in the case of the first line of the field, the offset signal input to the input 330c is output to its output 114 by the image end position signal 330b supplied from the control unit 388 to the first selector 100, and the adder 102 Are added to the offset value and the zoom magnification data, respectively.
Further, when processing other lines, the output 112 (decimal part) of the adder 102 selected by the first selector 100 and the zoom magnification data are added.

Then, the process proceeds to a step 1700, wherein, in the addition result in the adder 102, whether the upper 9th bit (“256”) or the 10th bit (“512”) corresponding to the integer part is generated or not. Is detected by the address counter 104b, and if an integer part is detected, the process proceeds to step 1702; otherwise, the process proceeds to step 1704. In step 1704, the count value of the address counter 104b is not updated (+0), and the process proceeds to step 1708, where it is determined whether the current field is the a field or the b field. In the former case, the process proceeds to step 1710, and in the latter case, the process proceeds to step 1712.

In step 1710, the input 158 of the second selector 110b is selected and the output 120 of the address counter 104b is selected.
The value obtained by adding "256" to is output to the output 210b. Further, in step 1712, the input 162 of the second selector 110b is selected, and "25" is output from the output 120 of the address counter 104b.
The value obtained by subtracting 5 "is output to the output 210b (step 1
714).

At step 1702, the address counter 104b
If integer part 116a ("256") is input to
Then, the count value of the address counter is counted up by "1". Next, proceeding to step 1718, the output of the address counter 104b is input to the input 120 of the second selector 110b. In the second selector 110b, the input 120 is selected according to the integer part "256" input to the control input 116a, and the output of the address counter 104b is output from the output 210b of the second selector 110b (step 1714).

In step 1702, the address counter
Step if the integer part 116b ("512") is input to 104b
Proceeding to 1720, the count value of the address counter is counted up by "2".

Then, the flow advances to step 1722, where the current field is determined by the field determination signal. If the current field is the a field, the flow advances to step 1724, where "255" is added to the output of the address counter 104b by the adder 152, and the calculation is performed. The result is input to the input 160 of the second selector 110b. Second
In the selector 110b, the input 160 is selected according to the integer part ("512") input to the control input 116b and the field discrimination signal (a field) input to the control input 330f. The output is output to the output 210b of the second selector 110b (step 1714).

If it is determined in step 1722 that the current field is the b field, the process proceeds to step 1716, where the output of the address counter 104b is input to the subtractor 156, and "256" is subtracted from the count value. . This calculation result is input to the input 164 of the second selector 110b, and the input 164 is input according to the integer part ("512") input to the control input 116b and the field discrimination signal (b field) input to the control input 330f. Is selected, and the operation result of the subtractor 156 is output to the output 210b of the second selector 110b (step 17).
14).

The values output from the second selector 110b in this way are supplied to the image memory 16 as read addresses of the image memory 16 in the vertical direction of the screen.

When the memory address is output in step 1714, the process returns to step 1610 to continue the subsequent processing. On the other hand, it is determined whether the output memory address is a negative value (step 1728). If the memory address is a negative value, the process proceeds to step 1730, where the background color data output from the control unit 328b is output. 325 (Figure 3) is switch 324
Is selected and output to the output 306. Even if the memory address is a positive value, it is determined whether or not the address is within the real address of the image memory (step 1732). In some cases, the generated memory address exceeds the real address of the image memory 16. Similarly, background color data is output (step 1730).

When the generated memory address is the real address of the image memory 16 in step 1732, various control signals for accessing the image memory 16 are supplied to the image memory 16 to generate the generated vertical direction. One line of image data corresponding to the read address and the horizontal read address is sequentially read (step 173).
Four). The read image data is input to the pixel value calculation unit 316 through the switch 312, and the pixel value of each pixel is calculated by a decimal part functioning as an interpolation coefficient.
The interpolated image data is input to the encoder circuit 308 via the switch 324. The image data input to the encoder circuit 308 is sequentially converted to NTSC video signal data, output to the output 310 of the signal processing circuit 34, and further converted to an analog signal by the D / A converter 36. The analog video signal is input to the monitor TV 14, and a corresponding one-line image is displayed on the display screen.

When the horizontal address generation for one line is completed, the next vertical address generation processing is started. Similarly, the address generation for specifying the address of the line in the subsequent horizontal scanning period is performed during the video period after the detection of the H blanking period in step 1614, with the zoom magnification data and the decimal part already output from the adder 102. Are added by the adder 102 and supplied to the address counter 104b. Therefore, the process proceeds to step 1716 or 1720 according to the bits (116a, 116b) representing the integer part values "256" and "512", respectively, and the address counter 10 according to the integer part value.
The count of 4b is incremented. If the integer part is not detected, the process proceeds to step 1704, where the address counter 104b
Is not updated, and the read address in which the current count value is corrected according to the current field is supplied to the image memory 16.

Next, another embodiment of the address control unit shown in FIG. 1 will be described. Referring to FIG. 18, another configuration example of the address control unit is shown.

This embodiment is applied to a case where electronic zoom processing (simple zoom) is performed without performing secondary interpolation processing. The address control unit 1800 in the embodiment shown in FIG.
The output (Z) 112 of the adder 1802 is connected to only the first selector 100. Otherwise, the configuration of the address control unit 1800 may be the same as that of the address control unit 332 shown in FIG. Similarly, in the address control unit 1900 shown in FIG. 19, the output 112 of the adder 1802 is connected to only the first selector 100. Otherwise, the configuration may be the same as that of the address control unit 332b shown in FIG. Thus, the address control units 1800 and 1900
Is applied when the pixel value of the image data read from the image memory 16 shown in FIG.

As described above, in these embodiments,
For example, at the time of electronic zoom processing for reducing an image by about 0.7 times, the original image is read from the image memory 16 from the even-numbered line of the a-field in the 0th line, as shown conceptually in FIG. The image data of the second line, the fourth line,... Is read out in each field of one screen, and the original image is the first line, the fifth line, the seventh line, among the odd-numbered lines of the b field. Is read out in each field of one screen.

At this time, during the reproduction of the b field, the data of the original image is read out from the a line (the fourth line of the original image) on the fourth line, and during the reproduction of the a field, Then, the data of the b field of the original image (the fifth line of the original image) is read (see the arrow in FIG. 3C).

In the conventional zoom processing, the original second line (field a) is displayed on the third line and the original fifth line is displayed on the fourth line as shown in FIG. The line (field b) was displayed. As described above, in the conventional example, when each field is viewed as one screen, a line having a large distance between lines is adopted and displayed over the fields.

In the present invention, a case where a state in which the line-to-line distance is large is expected is detected by the output of the adder 102 (an integer part of the line-to-line distance). In such a case, the line of the other field is adopted. Therefore, a more natural image of one screen can be obtained, especially after the reduction zoom processing.

As shown in the conceptual display pixel arrangement in FIG. 9, during the electronic zoom processing for enlarging the image by 1.2 times, referring to the conventional processing example of FIG. Are reversed (the 4th and 5th lines and the 14th and 15th lines of the original image). However, in the above embodiment, by controlling the output of the address counter, an image after natural enlargement processing can be obtained as shown in FIG. That is, in any of the above-described embodiments, the output value of the address counter is not limited to the line corresponding to the field currently being processed, and the line of the other field is changed according to the value of the integer part output from the address counter. By changing to specify
Images after the natural electronic zoom processing as shown in FIGS. 8 and 9 can be obtained.

In the above embodiment, a film scanner was described as an example, but the present invention is not limited to this. For example, the signal processing device 34 is applicable not only to an imaging device such as an electronic still camera, a digital video camera, and other scanners, but also to a playback device that reads and outputs image signals recorded on a recording medium such as a semiconductor memory or an optical disk. Is done. For example, two screens supplied from a reproducing apparatus that reads image signals stored in a magnetic storage medium such as a magnetic tape or a magnetic disk, an optical disk, an optical card, or a semiconductor memory such as a flash memory and reproduces a video signal. The present invention can be effectively applied to a signal processing device that inputs a video signal composed of fields and zooms the image.

Further, the signal processing device 34 in the above embodiment is used.
Is an ASIC (Application Specific Integrated Circuit)
However, it is not limited to this, and the device 34
May be composed of individual components. The field scanning method is NTSC (National Television System Committ
ee) Not only the scanning method but also PAL (Phase Alternating
by Line) method or another method.

[0107]

As described above, according to the present invention, a read address designating a line in a field different from the field currently being processed is generated based on magnification data corresponding to the zoom magnification, and stored in the storage means. Image signal can be read out. Therefore, problems such as the line spacing that occurs in the conventional electronic zoom processing for each field and the inversion of the front and back of the line are prevented, and a proper field image that is consistent as one screen is stored from the storage unit. It can be read out and output in real time.

In this case, there is no need to store the read image signal in the memory again on the read side of the storage means.
In addition, since it is not necessary to perform the zoom process for each frame, a high quality image processing result can be obtained with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an address control unit in a signal processing device to which an image processing device according to the present invention is applied.

FIG. 2 is a block diagram showing a film scanner device to which the present invention is applied.

FIG. 3 is a block diagram illustrating an example of an internal configuration of the signal processing device illustrated in FIG. 2;

FIG. 4 is a diagram illustrating a configuration example of a pixel value calculation unit in the electronic zoom processing circuit illustrated in FIG. 3;

FIG. 5 is a diagram illustrating a processing order in horizontal and vertical directions in the electronic zoom processing circuit illustrated in FIG. 3;

6 is a conceptual diagram showing a state in which image signals are mapped to the image memory shown in FIG. 3 in frame order.

FIG. 7 is a diagram showing a virtual address space in the embodiment shown in FIG. 3;

FIG. 8 is a conceptual diagram for comparing and explaining a line array after a reduction process in a specific image with a conventional processing example.

FIG. 9 is a conceptual diagram for comparing and explaining a line array after a magnification process in a specific image with a conventional processing example.

FIG. 10 is a flowchart showing a vertical zoom processing procedure in the embodiment shown in FIG. 1;

FIG. 11 is a flowchart showing a vertical zoom processing procedure in the embodiment shown in FIG. 1;

FIG. 12 is a flowchart showing a horizontal zoom processing procedure in the embodiment shown in FIG. 1;

FIG. 13 is a flowchart showing a horizontal zoom processing procedure in the embodiment shown in FIG. 1;

14 is a conceptual diagram showing a state in which image signals are mapped in the image memory shown in FIG. 3 in the order of fields.

FIG. 15 is a block diagram illustrating another example of the configuration of the address control unit illustrated in FIG. 3;

FIG. 16 is a flowchart showing a vertical zoom processing procedure in the embodiment shown in FIG. 15;

FIG. 17 is a flowchart showing a vertical zoom processing procedure in the embodiment shown in FIG. 15;

FIG. 18 is a block diagram illustrating another configuration example of the address control unit illustrated in FIG. 3;

FIG. 19 is a block diagram illustrating another configuration example of the address control unit illustrated in FIG. 3;

FIG. 20 is a diagram showing the arrangement of each line during reduction processing according to the present invention.

FIG. 21 is a diagram showing the arrangement of each line during reduction processing according to the conventional method.

FIG. 22 is a diagram showing an arrangement of each line at the time of enlargement processing according to the present invention.

FIG. 23 is a diagram showing the arrangement of each line at the time of enlargement processing according to the conventional method.

FIG. 24 is a diagram illustrating an example of a pixel arrangement in the horizontal direction at the time of reduction and enlargement.

[Explanation of symbols]

 10 Film scanner device 30 Overall control unit (CPU) 34 Signal processing device 100 First selector 102 Adder 104 Address counter 106 Adder 108 Subtractor 110 Second selector 302 Electronic zoom processing circuit 328 Control unit 332 Address control unit

Claims (12)

[Claims] 1. An image processing apparatus for sequentially accumulating image signals representing a desired image in a storage means, reducing or enlarging the accumulated image signals, reading out the signals, and outputting the signals by interlaced scanning. Input means for inputting the image signal and storing the image signal in the storage means; processing means for reading the image signal stored in the storage means in accordance with the interlaced scanning; and an image read from the storage means Output means for outputting a signal, wherein the processing means generates an address signal designating a read address for reading an image signal stored in the storage means, and supplies the generated address signal to the storage means. The address control means, when generating a vertical read address of one of the fields in the interlaced scanning, sets a magnification for reducing or enlarging the image. Depending on the constant scale factor data, the image processing apparatus characterized by generating an address signal for specifying the lines of different other fields as the fields in the read address generation process. 2. The image processing apparatus according to claim 1, wherein the address control unit is configured to generate the read address based on the magnification data and a reference position sequentially updated from an image end position of each field. First arithmetic means for calculating an integer part representing a line interval equal to or more than the line distance at the same magnification and a decimal part representing a line interval less than the line distance, and a calculation result of the first arithmetic means Counting means for counting a value corresponding to the value of the integer part, and a value obtained by correcting the output value of the counting means according to the value of the integer part obtained by the first arithmetic means as the address signal. An image processing apparatus, comprising: an address correcting means for outputting. 3. The image processing apparatus according to claim 2, wherein the address correction unit converts the count value from the counting unit into a read address that designates a line of the other field with respect to the field under the read address generation process. Second arithmetic means for correcting, and selecting means for selecting an output of the second arithmetic means according to the value of the integer part and outputting the selected value as an address signal to the storage means. Characteristic image processing device. 4. The image processing apparatus according to claim 2, wherein said input means stores said image signal in said storage means in frame order, and said address correction means outputs an output value of said counting means to said output. An image processing apparatus, wherein a read address corresponding to a previous or next line in a processing line in the frame order represented by a value is corrected. 5. The image processing apparatus according to claim 2, wherein the input unit stores the image signals in the storage unit in the order of fields, and the address correction unit outputs the output value of the counting unit to the output unit. An image processing apparatus, wherein a read address of a line in the other field corresponding to the processing line in the field order represented by the output value is corrected. 6. The image processing apparatus according to claim 2, wherein the address control unit includes an offset unit that specifies a line position to be processed in a virtual address space, and the first arithmetic unit includes the offset unit. An image processing apparatus for calculating the integer part and the decimal part using a position designated by (1) as the reference position. 7. The image processing apparatus according to claim 6, wherein said processing means has means for generating background data for arranging a background image around a processed image represented by an image signal read from said storage means. The image processing apparatus according to claim 1, wherein the output unit outputs the background data according to a read address generated by the address control unit. 8. An image processing apparatus according to claim 1, wherein said processing means includes a pixel value calculating means for interpolating and outputting an image signal read from said storage means. . 9. The image processing apparatus according to claim 8, wherein the pixel value calculation means interpolates and outputs an image signal read from the storage means using a calculation result of the first calculation means. An image processing apparatus characterized by the above-mentioned. 10. The image processing apparatus according to claim 1, wherein said address control means includes address generation means for generating a horizontal address for said image, and corresponds to said generated vertical read address. An image processing apparatus, wherein a read address for reading each pixel by a line is generated and supplied to the storage means. 11. An image processing method for sequentially accumulating image signals representing a desired image in a storage means, reducing or enlarging the accumulated image signals, reading out the signals, and outputting the signals by interlaced scanning. Adding a value indicating the reference position of each line in the vertical direction of the screen to be processed and magnification data set in accordance with reduction or enlargement of the image, and calculating the addition result to obtain a line-to-line distance at the same magnification. If it exceeds, the count value of the counting means for generating a read address for the storage means is counted up according to the addition result. If the addition result indicates twice the distance between lines, the counting is performed. The count value is corrected to a read address that is one line before the line indicated by the count value of the means and specifies the line of the other field, and the corrected result is stored in the storage means. An image processing method for outputting a read address in a vertical direction. 12. The image processing method according to claim 11, wherein, if the addition result does not exceed the line-to-line distance at the same magnification, the counting means does not count up and the current total number is not counted. An image processing method, wherein the count value is corrected to a read address designating a line next to a line indicated by a numerical value, and the correction result is output as a vertical read address to the storage means.