JPH10229265A - Mounting method and mounting structure - Google Patents
Mounting method and mounting structureInfo
- Publication number
- JPH10229265A JPH10229265A JP9029467A JP2946797A JPH10229265A JP H10229265 A JPH10229265 A JP H10229265A JP 9029467 A JP9029467 A JP 9029467A JP 2946797 A JP2946797 A JP 2946797A JP H10229265 A JPH10229265 A JP H10229265A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- board
- ceramic
- mounting
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
Landscapes
- Coupling Device And Connection With Printed Circuit (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、実装技術に関し、
特に、パーソナルコンピュータ等の高機能、低価格な中
央演算装置の実装を必要とする分野に適用して有効な技
術に関する。The present invention relates to a packaging technology,
In particular, the present invention relates to a technique which is effective when applied to a field requiring a high-performance, low-cost central processing unit such as a personal computer.
【０００２】[0002]
【従来の技術】たとえば、パーソナルコンピュータ（以
下、パソコンと略記する）は、あらゆる分野で利用され
ているが、ユーザからの多機能化、高性能化の要求が非
常に強くなってきている。パソコンの機能（特に高速
化）は、中央演算装置（ＭＰＵ：Micro Processor Uni
t）によってほとんど決まってしまうため、日進月歩で
高速のＭＰＵの開発が行われている。このため、最近の
パソコンでは、ＭＰＵをパソコンの実装基板から脱着可
能にし、ＭＰＵの交換によって旧型のパソコンでも高速
化ができるようになっている。2. Description of the Related Art For example, personal computers (hereinafter abbreviated as personal computers) are used in various fields, but users are increasingly demanding multi-functionality and high performance. The functions of the personal computer (especially high speed) are provided by a central processing unit (MPU: Micro Processor Uni
Since it is almost determined by t), the development of high-speed MPUs is progressing rapidly. For this reason, in recent personal computers, the MPU can be detached from the mounting board of the personal computer, and the speed of an old personal computer can be increased by replacing the MPU.
【０００３】たとえば、１９９７年１月１日、マックワ
ールドコミュニケーションズジャパン編集発行「マック
ワールドジャパン１月号」Ｐ５１〜Ｐ５２等の文献にも
記載されているように、パソコンでは、ガラスエポキシ
製のプリント基板上にＭＰＵ、メモリ等のパッケージが
実装される。このとき、ＭＰＵやメモリは、交換・増設
可能なようにコネクタを介して取り付けられることが一
般的である。このコネクタには、幾つかの種類がある
が、一般的には、電極が一列に並んだタイプのコネクタ
に、小型の配線基板の一辺に設けられた電極を差し込ん
で接続する。ＭＰＵはパッケージに入れた状態で、この
小型の実装基板上に取り付けられている。この小型の配
線基板は、ガラスエポキシ製が用いられている。[0003] For example, as described in a document such as "MacWorld Japan January Issue" P51 to P52 edited by MacWorld Communications Japan on January 1, 1997, a personal computer is made of a glass epoxy printed circuit board. A package such as an MPU and a memory is mounted thereon. At this time, the MPU and the memory are generally attached via a connector so that they can be replaced or added. Although there are several types of this connector, in general, an electrode provided on one side of a small wiring board is inserted and connected to a connector of a type in which electrodes are arranged in a line. The MPU is mounted on the small mounting board in a state of being packaged. This small wiring board is made of glass epoxy.
【０００４】[0004]
【発明が解決しようとする課題】ＭＰＵの高性能化に伴
って、ＭＰＵの外部接続端子（ピン）の数は増大してお
り、これに伴って、実装方法も、挿入実装からＢＧＡ
（Ball Grid Array ）等の面実装に移行することが予想
されるが、従来のようなガラスエポキシ製の配線基板を
用いる場合には、たとえば数百〜千個にも及ぶと予想さ
れる外部接続端子数を有するＭＰＵの表面実装は困難で
ある、という技術的課題がある。The number of external connection terminals (pins) of the MPU has been increasing with the high performance of the MPU, and the mounting method has been changed from the insertion mounting to the BGA.
(Ball Grid Array) is expected to shift to surface mounting. However, when a conventional glass epoxy wiring board is used, for example, the number of external connections expected to reach hundreds to thousands is expected. There is a technical problem that surface mounting of an MPU having the number of terminals is difficult.
【０００５】また、ＢＧＡ等の面実装を行う場合には、
ＭＰＵの動作中の発熱等に起因する熱応力の緩和に配慮
する必要があるが、たとえばセラミックスパッケージ等
で封止されたＭＰＵを材質の異なるガラスエポキシ製の
配線基板に表面実装する場合には、熱膨張率の差によっ
て熱応力が発生し、表面実装の接合部の信頼性の低下が
懸念される、という技術的課題もある。When performing surface mounting of a BGA or the like,
Although it is necessary to consider the relaxation of thermal stress caused by heat generation during operation of the MPU, for example, when the MPU sealed with a ceramic package or the like is surface-mounted on a glass epoxy wiring board of a different material, There is also a technical problem that a thermal stress is generated due to a difference in thermal expansion coefficient, and there is a concern that the reliability of a surface-mount joint is reduced.
【０００６】また、パソコン等の機器では、低価格化へ
の配慮は必須であり、上述のような技術的課題を低価格
で解決することが必要となる。[0006] Further, in equipment such as personal computers, consideration for price reduction is indispensable, and it is necessary to solve the above-mentioned technical problems at low cost.
【０００７】本発明の目的は、外部接続端子数の多い表
面実装タイプの半導体装置を、材質の異なる配線基板に
実装することが可能な実装技術を提供することにある。It is an object of the present invention to provide a mounting technique capable of mounting a surface mounting type semiconductor device having a large number of external connection terminals on a wiring board made of a different material.
【０００８】本発明の他の目的は、外部接続端子数の多
い表面実装タイプの半導体装置を、高い信頼性にて、材
質の異なる配線基板に実装することが可能な実装技術を
提供することにある。Another object of the present invention is to provide a mounting technique capable of mounting a surface mounting type semiconductor device having a large number of external connection terminals on a wiring board made of a different material with high reliability. is there.
【０００９】本発明の他の目的は、外部接続端子数の多
い表面実装タイプの半導体装置を、低コストにて、材質
の異なる配線基板に実装することが可能な実装技術を提
供することにある。Another object of the present invention is to provide a mounting technique capable of mounting, at low cost, a surface-mount type semiconductor device having a large number of external connection terminals on a wiring board made of a different material. .
【００１０】本発明の他の目的は、半導体装置の交換を
容易に行うことが可能な実装技術を提供することにあ
る。Another object of the present invention is to provide a mounting technique capable of easily replacing a semiconductor device.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【００１３】たとえば、表面実装技術の採用により、半
導体装置から多くの電極を引き出すには、半導体装置の
微細な電極を受けることができる実装基板が必要であ
る。そこで、本発明の実装技術では、ＢＧＡ等の表面実
装における微細な電極を受けるため、ガラスエポキシ製
に比べて微細な加工が可能なセラミックス製の基板を採
用する。そして、セラミックス製の基板を直接、プリン
ト基板上のコネクタに接続する。For example, in order to draw out many electrodes from a semiconductor device by employing the surface mounting technology, a mounting substrate capable of receiving fine electrodes of the semiconductor device is required. Therefore, in the mounting technique of the present invention, a ceramic substrate that can be processed more finely than glass epoxy is used to receive fine electrodes in surface mounting such as BGA. Then, the ceramic substrate is directly connected to the connector on the printed circuit board.
【００１４】このように、セラミックス製の基板を採用
することで、表面実装対応の微細な接続電極の加工が可
能になり、多ピン化が達成できる。また、セラミックス
は半導体装置の素子やセラミックスパッケージと熱膨張
率が近いので熱応力の発生を提言できる。これらのこと
により、パソコンの高速化および信頼性の向上が可能に
なる。また、セラミックス製の基板を直接、プリント基
板上のコネクタに接続することで、半導体装置の交換が
容易になるとともに、従来用いられていた、小型の実装
基板が不必要になり、コストの低減が可能になる。As described above, by employing a ceramic substrate, it is possible to process a fine connection electrode compatible with surface mounting, and it is possible to increase the number of pins. In addition, since ceramics have a coefficient of thermal expansion close to that of an element of a semiconductor device or a ceramic package, generation of thermal stress can be suggested. As a result, the speed and reliability of the personal computer can be improved. In addition, by directly connecting the ceramic substrate to the connector on the printed circuit board, replacement of the semiconductor device is facilitated, and a small mounting substrate, which has been conventionally used, becomes unnecessary, thereby reducing costs. Will be possible.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照しながら詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１６】（実施の形態１）図１は、本発明の第１の
実施の形態である実装構造の一例を示す側面図であり、
図２は、その一部を取り出して示す平面図である。(First Embodiment) FIG. 1 is a side view showing an example of a mounting structure according to a first embodiment of the present invention.
FIG. 2 is a plan view showing a part thereof.
【００１７】半導体装置１は、ＣＣＢ（Controlled Col
lapse Bonding ）はんだバンプ２によって、たとえばア
ルミナや窒化アルミニウム等のセラミックスからなるセ
ラミックス製配線基板３上に表面実装されている。半導
体装置１とセラミックス製配線基板３の間には、アンダ
ーフィル用樹脂４が注入されており、封止とＣＣＢはん
だバンプ２の補強を行なっている。The semiconductor device 1 is a CCB (Controlled Col
The surface is mounted on a ceramic wiring board 3 made of ceramics such as alumina or aluminum nitride by solder bumps 2. An underfill resin 4 is injected between the semiconductor device 1 and the ceramic wiring board 3 to seal and reinforce the CCB solder bumps 2.
【００１８】図２に例示されるように、セラミックス製
配線基板３の側端縁には、複数の電極３ａが設けられて
おり、個々の電極３ａは、セラミックス製配線基板３の
表面や内部等に設けられた図示しない配線パターンを介
して個々のＣＣＢはんだバンプ２に電気的に繋がってい
る。As illustrated in FIG. 2, a plurality of electrodes 3a are provided on the side edges of the ceramic wiring board 3, and each electrode 3a is connected to the surface or the inside of the ceramic wiring board 3 or the like. Are electrically connected to the individual CCB solder bumps 2 via a wiring pattern (not shown) provided on the substrate.
【００１９】一方、たとえばガラスエポキシ樹脂等で構
成されるプリント基板６には、挿抜溝５ｂの内部に複数
の圧接電極５ａを備えたコネクタ５が配置されている。
セラミックス製配線基板３は、複数の電極３ａが設けら
れた端縁部を、コネクタ５の挿抜溝５ｂの内部に圧入さ
れることによって、プリント基板６に対して挿抜自在に
実装され、この時、個々の電極３ａがコネクタ５内の圧
接電極５ａに接触して電気的に接続される。On the other hand, on a printed board 6 made of, for example, glass epoxy resin, a connector 5 having a plurality of press-contact electrodes 5a is arranged inside an insertion / extraction groove 5b.
The ceramic wiring board 3 is mounted so as to be freely inserted into and removed from the printed circuit board 6 by press-fitting the edge provided with the plurality of electrodes 3 a into the insertion groove 5 b of the connector 5. The individual electrodes 3a are in contact with the pressure contact electrodes 5a in the connector 5 and are electrically connected.
【００２０】このプリント基板６は、たとえば、パソコ
ン等におけるマザーボードであり、一方、半導体装置１
は、たとえばＭＰＵ等のＬＳＩである。The printed circuit board 6 is, for example, a motherboard for a personal computer or the like, while the semiconductor device 1
Is an LSI such as an MPU, for example.
【００２１】半導体装置１からの信号伝達経路は、セラ
ミックス製配線基板３内に設けられた図示しない配線構
造にて拡大されて引き回され、コネクタ５を介してプリ
ント基板６に伝わる。本第１の実施の形態では、セラミ
ックス製配線基板３上に１つの半導体装置１を搭載した
例を示してあるが、複数の半導体装置１を搭載すること
も同様に可能である。また、特に図示しないが、セラミ
ックス製配線基板３の片面だけでなく、両面に半導体装
置１を搭載してもよい。さらに、複数のコネクタ５をプ
リント基板６上に並列に近接して配列することにより、
各々がＭＰＵ等の半導体装置１を搭載したセラミックス
製配線基板３を実装して、高い実装密度にて、いわゆる
マルチＭＰＵ構成を容易に実現することができる。The signal transmission path from the semiconductor device 1 is enlarged and routed by a wiring structure (not shown) provided in the ceramic wiring substrate 3, and transmitted to the printed circuit board 6 via the connector 5. In the first embodiment, an example is shown in which one semiconductor device 1 is mounted on the ceramic wiring board 3, but a plurality of semiconductor devices 1 can be mounted in the same manner. Although not specifically shown, the semiconductor device 1 may be mounted not only on one side of the ceramic wiring board 3 but also on both sides. Further, by arranging a plurality of connectors 5 close to each other in parallel on the printed circuit board 6,
By mounting the ceramic wiring board 3 on which the semiconductor device 1 such as an MPU is mounted, a so-called multi-MPU configuration can be easily realized at a high mounting density.
【００２２】図３は、図１に例示された実装構造におい
て、半導体装置１上に放熱用のアルミニュウム製フィン
７を取り付けた例である。半導体装置１からの発熱量が
大きい場合、放熱部品を半導体装置１の裏面に取り付け
る。FIG. 3 shows an example in which aluminum fins 7 for heat dissipation are mounted on the semiconductor device 1 in the mounting structure illustrated in FIG. When the amount of heat generated from the semiconductor device 1 is large, a heat radiating component is attached to the back surface of the semiconductor device 1.
【００２３】本第１の実施の形態の場合、半導体装置１
とセラミックス製配線基板３の間の熱膨張率の差が小さ
いため、ＣＣＢはんだバンプ２に加わる熱応力が軽減さ
れる。また、アンダーフィル用樹脂４によりＣＣＢはん
だバンプ２が補強されるのでＣＣＢはんだバンプ２に作
用する熱応力が緩和される。また、セラミックス製配線
基板３とプリント基板６の熱膨張率の差はコネクタ５の
部分にて吸収され、緩和される。In the case of the first embodiment, the semiconductor device 1
Since the difference in the coefficient of thermal expansion between the substrate and the ceramic wiring board 3 is small, the thermal stress applied to the CCB solder bump 2 is reduced. Further, since the CCB solder bumps 2 are reinforced by the underfill resin 4, the thermal stress acting on the CCB solder bumps 2 is reduced. In addition, the difference in the coefficient of thermal expansion between the ceramic wiring board 3 and the printed board 6 is absorbed and mitigated by the connector 5.
【００２４】また、ＭＰＵ等の半導体装置１の交換は、
セラミックス製配線基板３ごと交換することで簡単に行
うことができ、たとえばＭＰＵの進化に伴うアップグレ
ードに容易に対応することが可能になる。The replacement of the semiconductor device 1 such as an MPU is
This can be easily performed by exchanging the entire ceramic wiring board 3, and for example, it is possible to easily cope with an upgrade accompanying the evolution of the MPU.
【００２５】（実施の形態２）図４は、本発明の第２の
実施の形態である実装構造の側面図である。(Embodiment 2) FIG. 4 is a side view of a mounting structure according to a second embodiment of the present invention.
【００２６】本第２の実施の形態の場合、半導体装置１
は、ＣＣＢはんだバンプ２によって、セラミックス製パ
ッケージ基板８上に表面実装されている。半導体装置１
とセラミックス製パッケージ基板８の間には、アンダー
フィル用樹脂４が注入されており、封止とＣＣＢはんだ
バンプ２の補強を行なっている。セラミックス製パッケ
ージ基板８は、当該セラミックス製パッケージ基板８の
底面に形成されたＢＧＡ用はんだバンプ９により、セラ
ミックス製配線基板３に接続されている。In the case of the second embodiment, the semiconductor device 1
Are surface-mounted on the ceramic package substrate 8 by the CCB solder bumps 2. Semiconductor device 1
The underfill resin 4 is injected between the substrate and the ceramic package substrate 8 for sealing and reinforcing the CCB solder bumps 2. The ceramic package substrate 8 is connected to the ceramic wiring substrate 3 by BGA solder bumps 9 formed on the bottom surface of the ceramic package substrate 8.
【００２７】半導体装置１からの信号伝達経路は、セラ
ミックス製パッケージ基板８内で拡大され、さらに、Ｂ
ＧＡ用はんだバンプ９を介してセラミックス製配線基板
１０内を引き回され、コネクタ５を介してプリント基板
６に接続される。本第２の実施の形態では、セラミック
ス製配線基板１０上に１つのセラミックス製パッケージ
基板８を搭載した例であるが、複数のセラミックス製パ
ッケージ基板８も同様に搭載可能である。The signal transmission path from the semiconductor device 1 is expanded in the ceramic package substrate 8 and
It is routed inside the ceramic wiring board 10 via the GA solder bumps 9 and connected to the printed board 6 via the connector 5. In the second embodiment, one ceramic package substrate 8 is mounted on the ceramic wiring substrate 10, but a plurality of ceramic package substrates 8 can be mounted similarly.
【００２８】図４の本第２の実施の形態の場合、半導体
装置１とセラミックス製パッケージ基板８の間の熱膨張
率の差に起因してＣＣＢはんだバンプ２に作用する熱応
力は、アンダーフィル用樹脂４により当該ＣＣＢはんだ
バンプ２を補強することで緩和される。また、セラミッ
クス製配線基板１０とプリント基板６の熱膨張率の差
は、コネクタ５の部分により吸収され、緩和される。In the case of the second embodiment shown in FIG. 4, the thermal stress acting on the CCB solder bump 2 due to the difference in the coefficient of thermal expansion between the semiconductor device 1 and the ceramic package substrate 8 is underfilled. It is alleviated by reinforcing the CCB solder bumps 2 with the resin 4. The difference in the coefficient of thermal expansion between the ceramic wiring board 10 and the printed circuit board 6 is absorbed by the connector 5 and reduced.
【００２９】一方、セラミックス製パッケージ基板８と
セラミックス製配線基板１０は同一材質のため、熱膨張
率の差がほとんど無く、ＢＧＡ用はんだバンプ９の長寿
命化が実現できる。On the other hand, since the ceramic package substrate 8 and the ceramic wiring substrate 10 are made of the same material, there is almost no difference in the coefficient of thermal expansion, and the life of the BGA solder bumps 9 can be extended.
【００３０】（実施の形態３）図５は、本発明の第３の
実施の形態である実装構造の側面図である。(Embodiment 3) FIG. 5 is a side view of a mounting structure according to a third embodiment of the present invention.
【００３１】この第３の実施の形態の場合には、図４に
例示される実装構造において、セラミックス製パッケー
ジ基板８ａのサイズを、搭載される半導体装置１と同程
度の寸法としたものである。また、セラミックス製配線
基板１０の上には、セラミックス製パッケージ基板８ａ
の他に、はんだバンプ１１ａを介して電子部品１１が搭
載されている。この電子部品１１としては、たとえば半
導体装置１がＭＰＵの場合、当該ＭＰＵ用のキャッシュ
メモリとして機能する半導体メモリ素子等が考えられ
る。In the case of the third embodiment, in the mounting structure illustrated in FIG. 4, the size of the ceramic package substrate 8a is approximately the same as the size of the semiconductor device 1 to be mounted. . A ceramic package substrate 8a is placed on the ceramic wiring substrate 10.
In addition, the electronic component 11 is mounted via the solder bump 11a. When the semiconductor device 1 is an MPU, for example, the electronic component 11 may be a semiconductor memory element or the like that functions as a cache memory for the MPU.
【００３２】この場合、ＣＣＢはんだバンプ２は、たと
えば、Ｐｂ−９８％／Ｓｎ−２％の組成の比較的融点の
高いはんだで構成され、一方、ＢＧＡ用はんだバンプ９
は、たとえば、Ｐｂ−３７％／Ｓｎ−６３％の組成の比
較的融点の低いはんだで構成される。これにより、セラ
ミックス製パッケージ基板８ａに半導体装置１を搭載し
た状態でユーザに供給され、ユーザ側にてセラミックス
製配線基板１０に、他の電子部品１１とともに実装する
場合、半導体装置１をセラミックス製パッケージ基板８
に固定するＣＣＢはんだバンプ２の溶融等を懸念するこ
となく、ＢＧＡ用はんだバンプ９や、はんだバンプ１１
ａのリフローによる、セラミックス製パッケージ基板８
ａおよび電子部品１１の実装作業を行うことが可能にな
る。In this case, the CCB solder bump 2 is made of, for example, a solder having a composition of Pb-98% / Sn-2% and having a relatively high melting point, while the BGA solder bump 9 is formed.
Is composed of, for example, a relatively low melting point solder having a composition of Pb-37% / Sn-63%. Accordingly, the semiconductor device 1 is supplied to the user in a state where the semiconductor device 1 is mounted on the ceramic package substrate 8a. When the user mounts the semiconductor device 1 on the ceramic wiring substrate 10 together with other electronic components 11, the semiconductor device 1 is mounted on the ceramic package substrate 8a. Substrate 8
The BGA solder bumps 9 and the solder bumps 11 can be formed without worrying about the melting of the CCB solder bumps 2 fixed to the solder bumps.
Package substrate 8 made of ceramics by reflow of a
a and the mounting operation of the electronic component 11 can be performed.
【００３３】（実施の形態４）図６は、本発明の第４の
実施の形態である実装構造の断面図である。(Embodiment 4) FIG. 6 is a sectional view of a mounting structure according to a fourth embodiment of the present invention.
【００３４】この第４の実施の形態では、前述の図４の
構成において、半導体装置１ａがセラミックス製パッケ
ージ基板８に対してワイヤボンディングにて電気的に接
続されている点が異なっている。The fourth embodiment is different from the configuration shown in FIG. 4 in that the semiconductor device 1a is electrically connected to the ceramic package substrate 8 by wire bonding.
【００３５】すなわち、半導体装置１ａの底面は、セラ
ミックス製パッケージ基板８に対して接着材１２を介し
て固定され、半導体装置１ａの上面に設けられた複数の
図示しないボンディングパッドと、セラミックス製パッ
ケージ基板８の上に設けられた複数の図示しない配線パ
ターンとの間は、複数のボンディングワイヤ１３が架設
されることによって電気的に接続されている。さらに、
半導体装置１ａおよびボンディングワイヤ１３は、たと
えばポッテイング等の方法で形成される封止樹脂１４に
よって覆われることにより封止されている。That is, the bottom surface of the semiconductor device 1 a is fixed to the ceramic package substrate 8 via the adhesive 12, and a plurality of bonding pads (not shown) provided on the upper surface of the semiconductor device 1 a A plurality of bonding wires 13 are electrically connected to a plurality of wiring patterns (not shown) provided on the wiring 8. further,
The semiconductor device 1a and the bonding wires 13 are sealed by being covered with a sealing resin 14 formed by a method such as potting, for example.
【００３６】（実施の形態５）図７は、本発明の第５の
実施の形態である実装構造の断面図である。(Embodiment 5) FIG. 7 is a sectional view of a mounting structure according to a fifth embodiment of the present invention.
【００３７】この第５の実施の形態の場合には、セラミ
ックス製配線基板１５が、半導体装置１の搭載領域部分
が選択的に多層配線構造部１５ａをなし、それ以外の部
分が表面配線構造部１５ｂをなすようにしたものであ
る。これにより、セラミックス製配線基板１５の構造の
簡単化、軽量化、低価格化を実現することができる。In the case of the fifth embodiment, the ceramic wiring board 15 is such that the mounting area portion of the semiconductor device 1 selectively forms the multilayer wiring structure portion 15a and the other portions are the surface wiring structure portion. 15b. Thus, the structure of the ceramic wiring board 15 can be simplified, lightened, and reduced in cost.
【００３８】以上説明したように、本発明の各実施の形
態の実装構造によれば、セラミックス配線基板３，１
０，１５を採用することで、表面実装用の微細な電極の
加工が可能になり、搭載される半導体装置１の多ピン化
が達成できる。このことで、ＭＰＵ等の半導体装置１を
使用するパソコンの高速化が可能になる。また、セラミ
ックス製配線基板３，１０，１５等を直接、プリント基
板６上のコネクタ５に接続することで、従来用いられて
いた、小型の実装基板が不必要になり、コストの低減に
なる。As described above, according to the mounting structure of each embodiment of the present invention, the ceramic wiring substrates 3, 1
By employing 0 and 15, fine electrodes for surface mounting can be processed, and the number of pins of the semiconductor device 1 to be mounted can be increased. Thus, the speed of a personal computer using the semiconductor device 1 such as an MPU can be increased. In addition, by directly connecting the ceramic wiring boards 3, 10, 15 and the like to the connector 5 on the printed board 6, a conventionally used small mounting board becomes unnecessary and the cost is reduced.
【００３９】以上本発明者によってなされた発明を実施
の形態に基づき具体的に説明したが、本発明は前記実施
の形態に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is.
【００４０】たとえば、セラミックスとしては、アルミ
ナや窒化アルミニウム等に限らず、任意の組成のものを
用いることができる。For example, the ceramic is not limited to alumina, aluminum nitride or the like, but may be of any composition.
【００４１】[0041]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.
【００４２】本発明の実装方法および実装構造によれ
ば、外部接続端子数の多い表面実装タイプの半導体装置
を、材質の異なる配線基板に実装することができる、と
いう効果が得られる。According to the mounting method and the mounting structure of the present invention, an effect is obtained that a surface-mount type semiconductor device having a large number of external connection terminals can be mounted on a wiring board made of a different material.
【００４３】また、本発明の実装方法および実装構造に
よれば、外部接続端子数の多い表面実装タイプの半導体
装置を、高い信頼性にて、材質の異なる配線基板に実装
することができる、という効果が得られる。Further, according to the mounting method and the mounting structure of the present invention, it is possible to mount a surface mounting type semiconductor device having a large number of external connection terminals on a wiring board made of a different material with high reliability. The effect is obtained.
【００４４】また、本発明の実装方法および実装構造に
よれば、外部接続端子数の多い表面実装タイプの半導体
装置を、低コストにて、材質の異なる配線基板に実装す
ることができる、という効果が得られる。Further, according to the mounting method and mounting structure of the present invention, it is possible to mount a surface-mount type semiconductor device having a large number of external connection terminals on a wiring board made of a different material at low cost. Is obtained.
【００４５】また、本発明の実装方法および実装構造に
よれば、半導体装置の交換を容易に行うことができる、
という効果が得られる。According to the mounting method and the mounting structure of the present invention, the semiconductor device can be easily replaced.
The effect is obtained.
【図１】本発明の第１の実施の形態である実装構造の一
例を示す側面図である。FIG. 1 is a side view showing an example of a mounting structure according to a first embodiment of the present invention.
【図２】本発明の第１の実施の形態である実装構造の一
部を取り出して示す平面図である。FIG. 2 is a plan view showing a part of a mounting structure according to the first embodiment of the present invention;
【図３】本発明の第１の実施の形態である実装構造の変
形例を示す側面図である。FIG. 3 is a side view showing a modification of the mounting structure according to the first embodiment of the present invention.
【図４】本発明の第２の実施の形態である実装構造の側
面図である。FIG. 4 is a side view of a mounting structure according to a second embodiment of the present invention.
【図５】本発明の第３の実施の形態である実装構造の側
面図である。FIG. 5 is a side view of a mounting structure according to a third embodiment of the present invention.
【図６】本発明の第４の実施の形態である実装構造の断
面図である。FIG. 6 is a sectional view of a mounting structure according to a fourth embodiment of the present invention.
【図７】本発明の第５の実施の形態である実装構造の断
面図である。FIG. 7 is a sectional view of a mounting structure according to a fifth embodiment of the present invention.
１，１ａ 半導体装置 ２ ＣＣＢはんだバンプ ３ セラミックス製配線基板 ３ａ 電極 ４ アンダーフィル用樹脂 ５ コネクタ ５ａ 圧接電極 ５ｂ 挿抜溝 ６ プリント基板 ７ アルミニュウム製フィン ８ セラミックス製パッケージ基板 ８ａ セラミックス製パッケージ基板 ９ ＢＧＡ用はんだバンプ １０ セラミックス製配線基板 １１ 電子部品 １１ａ はんだバンプ １２ 接着材 １３ ボンディングワイヤ １４ 封止樹脂 １５ セラミックス製配線基板 １５ａ 多層配線構造部 １５ｂ 表面配線構造部 DESCRIPTION OF SYMBOLS 1, 1a Semiconductor device 2 CCB solder bump 3 Ceramic wiring board 3a electrode 4 Underfill resin 5 Connector 5a Pressure contact electrode 5b Insertion / extraction groove 6 Printed circuit board 7 Aluminum fin 8 Ceramic package board 8a Ceramic package board 9 BGA solder Bump 10 Ceramic wiring board 11 Electronic component 11a Solder bump 12 Adhesive material 13 Bonding wire 14 Sealing resin 15 Ceramic wiring board 15a Multilayer wiring structure part 15b Surface wiring structure part
Claims (9)
セラミックス配線基板を、プリント基板上に設置したコ
ネクタに差し込んで取り付けることを特徴とする実装方
法。1. A mounting method, wherein a ceramic wiring board on which at least one semiconductor device is mounted is inserted and attached to a connector installed on a printed circuit board.
セラミックスパッケージ基板を、さらにセラミックス配
線基板に表面実装し、そのセラミックス配線基板を、プ
リント基板上に設置したコネクタに差し込んで取り付け
ることを特徴とする実装方法。2. A mounting method, wherein a ceramic package substrate on which at least one semiconductor device is mounted is further surface-mounted on a ceramic wiring substrate, and the ceramic wiring substrate is inserted into and attached to a connector mounted on a printed circuit board. Method.
たセラミックス配線基板を、プリント基板上に設置され
たコネクタに差し込んで取り付けてなることを特徴とす
る実装構造。3. A mounting structure wherein a ceramic wiring board on which at least one semiconductor device is mounted is inserted and attached to a connector provided on a printed circuit board.
半導体装置が前記セラミックス配線基板上に取り付けら
れ、封止されていることを特徴とする実装構造。4. The mounting structure according to claim 3, wherein said semiconductor device is mounted and sealed on said ceramic wiring board.
半導体装置が前記セラミックス配線基板上に表面実装さ
れ、前記半導体装置と前記セラミックス配線基板との間
には、アンダーフィル用樹脂が注入されていることを特
徴とする実装構造。5. The mounting structure according to claim 3, wherein the semiconductor device is surface-mounted on the ceramic wiring board, and an underfill resin is injected between the semiconductor device and the ceramic wiring board. Mounting structure characterized by that.
セラミックス配線基板は、前記半導体装置が表面実装さ
れる領域に選択的に形成された多層配線構造領域と、そ
れ以外の表面配線領域とからなることを特徴とする実装
構造。6. The mounting structure according to claim 3, wherein the ceramic wiring substrate comprises a multilayer wiring structure region selectively formed in a region where the semiconductor device is surface-mounted, and a surface wiring region other than the multilayer wiring structure region. Mounting structure characterized by becoming.
たセラミックスパッケージ基板が、さらにセラミックス
配線基板に表面実装され、前記セラミックス配線基板
を、プリント基板上に設置されたコネクタに差し込んで
取り付けてなることを特徴とする実装構造。7. A ceramic package substrate on which at least one semiconductor device is mounted is further surface-mounted on a ceramic wiring substrate, and the ceramic wiring substrate is inserted and attached to a connector provided on a printed circuit board. Characteristic mounting structure.
半導体装置は当該半導体装置とほぼ同程度の外形寸法を
有する前記セラミックス配線基板上に表面実装されてい
ることを特徴とする実装構造。8. The mounting structure according to claim 7, wherein said semiconductor device is surface-mounted on said ceramic wiring substrate having substantially the same external dimensions as said semiconductor device.
において、前記セラミックス配線基板上には、前記半導
体装置または前記セラミックスパッケージ基板の他に任
意の電子部品が実装されていることを特徴とする実装構
造。9. The mounting structure according to claim 3, wherein an arbitrary electronic component is mounted on the ceramic wiring board in addition to the semiconductor device or the ceramic package board. Mounting structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9029467A JPH10229265A (en) | 1997-02-13 | 1997-02-13 | Mounting method and mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9029467A JPH10229265A (en) | 1997-02-13 | 1997-02-13 | Mounting method and mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10229265A true JPH10229265A (en) | 1998-08-25 |
Family
ID=12276917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9029467A Pending JPH10229265A (en) | 1997-02-13 | 1997-02-13 | Mounting method and mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10229265A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011077445A (en) * | 2009-10-01 | 2011-04-14 | Tokyo Electron Ltd | Probe card |
-
1997
- 1997-02-13 JP JP9029467A patent/JPH10229265A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011077445A (en) * | 2009-10-01 | 2011-04-14 | Tokyo Electron Ltd | Probe card |
| CN102549735A (en) * | 2009-10-01 | 2012-07-04 | 东京毅力科创株式会社 | Probe card |
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