JPH1022829A - Digital modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce quantization errors, without preparing any special hardware that is dedicated for quantization. SOLUTION: This digital modulator modulates the modulation data inputted from the outside into a digital modulation signal (2) and then converts this modulation signal into an analog modulation signal by a D/A converter 3 for outputting it. Then the modulator is provided with a table 7 which stores the table information that is used for modulation of the modulation data, a table data production means 5 which produces the table information for the digital filter processing when the converted data are modulated, and a quantization means 6 applies the processing to the table information to reduce the quantization noise and also quantizes the table information into the resolution of the converter 3 to, output it as the table information that is stored in the table 7. In such a constitution, the quantization noise can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulator and, more particularly, to a digital modulator having a feature in quantization of digital data.

[0002]

2. Description of the Related Art In a signal generator for outputting a digital modulation signal such as π / 4DQPSK, it is necessary to use a digital baseband filter in order to realize high modulation accuracy. As a means for easily realizing a high sampling rate FIR digital filter, a table type digital modulator has been conventionally used for a signal generator.

On the other hand, a modulated signal modulated by a digital filter needs to be finally converted into an analog signal by a D / A converter. Here, since the output of the digital filter requires high-precision data, the word length of the table is increased when a table-type digital filter is used.

However, since the D / A converter needs to ensure high-speed operation, it is not practical to handle data having an excessively long word length, and the data obtained by quantizing the digital filter output is used. D / A is performed.

When performing such quantization, if the number of bits is reduced by truncation or rounding, quantization noise is generated. That is, in the digital modulator of the table system, since the D / A converter has a finite number of bits, quantization noise exists.

As a technique for reducing such quantization noise, there is a ΔΣ modulation method. ΔΣ modulation is a method of performing quantization so as to reduce a component of a quantization error near frequency 0. Generally, a uniform quantization error of the spectrum occurs at the time of quantization, but by using ΔΣ modulation, the component of the quantization error near the frequency 0 can be reduced.

FIG. 10 is a block diagram showing a configuration of a conventional digital modulator using a ΔΣ modulator as a quantization device. As shown in the figure, the modulation data input to the digital modulator is first converted into a digital modulation signal in the table type modulator 71.

Next, the digitally modulated signal is subjected to ΔΣ modulation in a ΔΣ modulator 72 to reduce the number of bits.
That is, it is quantized and input to the D / A converter 73.
Then, the quantized digital modulation data is D / A
The signal is converted into an analog modulation signal by the converter 73, and is further output as a final analog modulation signal via the analog filter 74.

[0009]

As described above, in the digital modulator, the ΔΣ modulation is performed immediately before the D / A converter 73, that is, after the digital filter. In order to realize such ΔΣ modulation, it is necessary to configure the ΔΣ modulator 72 with high-speed hardware such as an ASIC.

However, if not only the digital filter of the table-type modulator 71 but also the ΔΣ modulator 72 is constituted by high-speed hardware, not only the hardware configuration of the entire modulator becomes complicated, but also The manufacturing cost of the modulator is also expensive.

In addition, the digital filter needs to perform a high-precision operation, and when a table-type digital filter is used, the table word length needs to be increased, and the storage capacity of the table increases. .

The present invention has been made in consideration of such circumstances, and has as its object to provide a digital modulator capable of reducing a quantization error without providing special hardware for quantization. I do.

[0013]

In order to solve the above-mentioned problems, the invention corresponding to claim 1 has a table, and selects and selects the table according to digital modulation data input from the outside. A digital modulator comprising: a table type modulator for generating a digital modulation signal based on data in a table; and a D / A converter for converting the digital modulation signal into an analog modulation signal and outputting the same. A table information creating means for creating table information by performing processing, a process of changing frequency characteristics of quantization noise with respect to the table information, and converting the table information into a resolution of a D / A converter. And a quantization means for outputting the data as data to be stored in the table, so that the frequency characteristic of the quantization noise can be changed. It is a digital modulator.

Next, a second aspect of the present invention is the digital modulator according to the first aspect, wherein the quantization means is a Δ 行 う modulator for performing ΔΣ modulation on table information. .

According to a third aspect of the present invention, in the first or second aspect, the pseudo random number generating means for outputting a pseudo random number including a PN sequence of the number of stages corresponding to the impulse response time of the digital filter is provided. The table data creation means is a digital modulator that performs processing of the quantization means in accordance with the order of generation of pseudorandom numbers.

Further, the invention corresponding to claim 4 is the invention according to claim 1 or 3, wherein the quantizing means includes the following (1) in a signal route from the output of the table information creating means to the input of the table. A first signal processing unit for calculating the equation and a quantizer body for outputting the resolution of the table information output from the table information generating means in accordance with the resolution of the table, and A second signal processing unit for performing the calculation of the following equation (2) is provided on a return route to the output of the information generating means. A digital modulator comprising: a synthesizing unit for synthesizing an output and an output of the second signal processing unit and inputting the output to the first signal processing unit.

[0017]

(Equation 2) (Operation) Therefore, first, in the digital modulator according to the first aspect of the present invention, table information for digital filter processing when generating a conversion signal is generated by the table data generating means.

Next, processing for reducing specific frequency components having quantization noise is performed on the table information by the quantization means, and the table information is quantized to the resolution of the D / A converter. And output as table information.

The table stores the table information output from the quantization means. Therefore, a specific frequency component having a quantization error can be reduced, and the table word length can be reduced to the number of bits of the D / A converter.

Next, in the digital modulator according to the second aspect of the present invention, in addition to the same operation as the first aspect of the present invention, a ΔΣ modulator for performing ΔΣ modulation is used as quantization means. It is possible to reduce a component around the frequency 0 of the quantization error.

The digital modulator according to the third aspect of the present invention operates in the same manner as the first or second aspect of the present invention. In addition, the pseudo-random number generating means corresponds to the impulse response time of the digital filter. Stage number P
A pseudo-random number including the N sequence is output.

The table data creating means creates table information in accordance with the order in which the pseudo random numbers are generated. When referring to a table on which quantization noise reduction processing has been performed, an error occurs due to discontinuity between symbols in the table.

The error due to the discontinuity is smaller than the case where the processing for reducing the quantization noise is not performed. However, according to the invention of claim 3, the error due to the discontinuity can be reduced.

That is, by creating table information in the order of generation of the above pseudo random numbers, when referring to a table based on the next modulation symbol, the order of table reference and the quantization noise by the quantization means are reduced. The probability that the arrangement of the table information (table information) subjected to the reduction processing is the same order is １ ／.

Therefore, when the sequence of the continuous quantization processing and the table information reference is in the same order, an error due to discontinuity between symbols does not occur, so that an error due to discontinuity between modulation symbols can be reduced. As a whole, the quantization error can be further reduced as a whole.

In the digital modulator according to the fourth aspect of the present invention, in addition to the same operation as the first to third aspects of the present invention, the following operation is performed by the quantization means.

First, the quantizer main unit outputs the signal from the first signal processing unit and the table information generating means for calculating the above equation (1) along the signal route from the output of the table information generating means to the input of the table. The resolution of the table information is output according to the resolution of the table.

Next, the second signal processing section performs the calculation of the above equation (2) on the feedback route from the input of the table to the output of the table information creating means. Further, the output of the table information generating unit and the output of the second signal processing unit are synthesized between the table information generating unit and the first signal processing unit by the synthesizing unit, and input to the first signal processing unit.

[0029]

Embodiments of the present invention will be described below. (First Embodiment of the Invention) FIG. 1 is a block diagram showing an example of a digital modulator according to a first embodiment of the present invention.

The digital modulator shown in FIG. 1A includes a quantization table data generator 1 and a table type modulator 2.
, A D / A converter 3 and an analog filter 4.

The quantization table data creation unit 1 has a table creation unit 5 and a quantization unit 6, creates and quantizes table data, and converts the result into a table type modulation unit 2
To Table 7 in the table.

The table creating section 5 is configured to generate a digital modulation signal for certain modulation data. At this time, the generated digital modulation signal is high-precision data having a large number of data bits so as to reduce quantization noise. Further, the table creating section 5 outputs digital modulation signals for all combinations of modulation data (corresponding to the addresses in the table 7) necessary for creating the table.

The quantization section 6 quantizes the digital modulation signal output from the table creation section 5 and stores it in the table 7 of the table type modulation section 2. The quantization method used in the present embodiment is ΔΣ modulation, and the quantization unit 6 is provided with a ΔΣ modulator.

The quantization system used in the quantization unit 6 may be any other quantization system as long as the process changes not only the ΔΣ modulation but also the frequency characteristic of the quantization noise. For example, a signal processing unit in which the transfer functions G and H are represented by the following equations in the configuration shown in FIG. 1B may be provided in the quantization unit 6.

[0035]

(Equation 3)

[0036] Such transfer function while reducing the quantization noise in the frequency 0 as with ΔΣ modulation is to reduce the quantization noise in the frequency components omega _i. Further, the table creation unit 5 and the quantization unit 6 may be constituted by high-speed hardware such as an ASIC, but high-speed real-time processing is not required at the table creation stage. Table data creation and quantization are realized by a wear process.

The table type modulator 2 uses the table 7 to generate a digital modulation signal according to the modulation data, and inputs the digital modulation signal to the D / A converter 3. Here, the table 7 stores the table information created by the quantization table data creation unit 1. This information is obtained by continuous ΔΣ modulation processing for one symbol time. The information stored in the table 7 has been quantized by the quantization unit 6 with the same precision as the data handled by the D / A converter 3.

Therefore, the digital modulation data output from the table type modulator 2 has the same number of bits as the number of bits handled by the D / A converter 3. The D / A converter 3 performs D / A conversion of the digital modulation data input from the table type modulation unit 2 and
Is to further perform necessary filtering on the D / A-converted signal and output the analog-modulated signal.

Next, the operation of the digital modulator according to the embodiment of the present invention configured as described above will be described. First, the modulation data input to the table type modulator 2 is converted into a sequence of modulation symbols.

This symbol sequence is converted into a modulated signal quantized by the table 7. Here, the quantized modulated signal is represented by the same number of bits as the number of bits of the D / A converter 3, and is input to the D / A converter 3.

Then, the digital modulation signal is D / A converted and output as an analog modulation signal via the analog filter 4. In such an operation, in the digital modulator of the present embodiment, since the table information converted into ΔΣ is stored in the table 7, the effect of reducing the quantization noise as described below as compared with the conventional technique is obtained. Is obtained.

FIG. 2 is a diagram for explaining the effect of reducing the quantization noise in the digital filter table according to the present embodiment in comparison with the prior art. FIG. 9A shows a DC component of a quantization error when a conventional table-type digital modulator modulates with a digital filter table and then quantizes with a quantizer 81 that simply rounds off. .

As shown in FIG. 2A, in this case, a normal quantization error is generated in R samples within one symbol time, that is, in all the 16 samples in the example shown in FIG.

On the other hand, FIG. 2B shows a table-type digital modulator according to the present invention in which a quantized modulated signal output from a table 7 which is also a digital filter is quantized after being subjected to modulation processing. FIG. 4 is a diagram schematically illustrating a state of a DC component of a quantization error.

First, the quantized modulated signal output from the table 7 is subjected to digital filter processing that is continuous for one symbol time.
Σ The result of applying modulation and quantizing. That is, as described above, the table 7 generates a modulation signal in accordance with a certain symbol, and generates ΔΣ in advance within one symbol time.
It is configured to be the result of applying modulation.

Then, the same output as in the ΔΣ modulation system is obtained within this time only by reading the table, and the DC component of the quantization error becomes zero. However, since another table is referred after one symbol time has elapsed, an error due to discontinuity occurs at the beginning and end of one symbol time.

This is because ΔΣ modulation uses a delay element. For example, in the second-order ΔΣ modulation, there are two samples of delay elements, so that an error of two samples is generated.

Therefore, in the second-order ΔΣ modulation, FIG.
An error of four samples occurs as shown in FIG. For this reason, the quantization noise reduction rate is ₁₀ log 104 / R [dB]. However, when the oversample ratio is high, this error is relatively small, and an output close to that of the ΔΣ modulation method is obtained. For this reason, the output from the digital modulator of the present embodiment is equivalent to the ΔΣ modulation.

As described above, the digital modulator according to the embodiment of the present invention incorporates the ΔΣ modulation method into the digital filter of the table system, omits the hardware for ΔΣ modulation, and applies the ΔΣ modulation in advance. The same output as that obtained by the ΔΣ modulation method is obtained except that an error due to discontinuity occurs at the beginning and end of one symbol time, and a sufficient quantization error reduction effect can be obtained. Can be.

That is, an output equivalent to ΔΣ modulation is obtained,
Moreover, hardware dedicated to ΔΣ modulation can be omitted, and ΔΣ modulation can be realized by prior software processing.

Further, when the oversample ratio is high,
The error due to the discontinuity of the table information is relatively small, and an output almost similar to the ΔΣ modulation method can be obtained. Thus, the table of the table type digital modulator
Provides a way to incorporate Σ modulation, the processing of which is complete ΔΣ
Although the modulation is not modulation, some errors occur, but the quantization noise can be reduced, and the effect of the quantization noise reduction can be obtained only with the digital filter of the table system.

In the present invention, since the table after quantization is created, there is also an advantage that the word length of the table becomes shorter and the storage capacity of the table becomes smaller as compared with a method using a separate ΔΣ modulator.

In the embodiment, ΔΔ is used as the quantization means.
Although the case where the modulation is used has been described, the present invention
Is not limited to the method using ΔΣ modulation. For example, quantization may be performed by performing processing using the transfer functions shown in the above equations (1) and (2). Even in this case, an error due to discontinuity of the table information occurs. However, the above-described effect and a sufficient effect of reducing the quantization error can be obtained. (Second Embodiment of the Invention) In the digital modulator shown in the above embodiment, hardware for ΔΣ modulation can be omitted, but an error due to discontinuity occurs at the beginning and end of one symbol time. Was.

In the present embodiment, a description will be given of a digital modulator that can improve this point and reduce the probability of error occurrence at the beginning and end of one symbol time. In the present embodiment, the probability of occurrence of an error is reduced by using a PN (pseudo random number) generator as a means for specifying a table address. This concept will be described with reference to FIG.

FIG. 3 is a diagram showing how the probability of error occurrence can be reduced by designating a table address using the PN generator. The concept of the error generation reducing method is based on the fact that an error due to discontinuity does not occur if the order of the table when applying ΔΣ modulation matches the order when actually referring to the table.

Here, since the reference of the table address is performed based on the sequence of the modulation symbols, the order of referring to the table depends on the modulation data, and it is impossible to completely match the reference order. However, ΔΣ
By specifying a table address with a PN generator when applying modulation, it is possible to increase the probability that the reference order will match.

Firstly, because the table is referenced based on the input of the last N _s symbols, for example, as shown in FIG. 3 (a), the table address of the next symbol of the current table address by left shifting the next symbol From the right.

On the other hand, when the register value of the PN generator is used as the address designation value, the result obtained by shifting to the left and inputting the exclusive OR from the right as shown in FIG. Will be done.

Therefore, the next address specified by the next symbol and the next address specified by the PN generator match with a probability of 1/2. When all 0s are added to the PN sequence, all addresses are indicated. Therefore, it is possible to easily create a table that can correspond to all combinations of symbols only by making a round of the PN sequence in addition to all 0s.

As described above, by preparing a table to which ΔΣ modulation is applied in advance in accordance with the address order indicated by the PN generator, the digital modulator which can always reduce the probability of occurrence of an error due to discontinuity in the next symbol to １ ／ Can be obtained.

That is, in the digital modulator according to the present embodiment, the register value of the PN generator is used as the address when the table is created. Next, a specific configuration of the digital modulator according to the present embodiment will be described.

FIG. 4 is a block diagram showing an example of a digital modulator according to a second embodiment of the present invention. The same parts as those in FIG. Only the part will be described.

This digital modulator includes a quantization table data generator 1 and a digital modulator as in the case of the first embodiment.
It is composed of a table type modulator 2, a D / A converter 3, and an analog filter 4.

Here, the table type modulation section 2 is configured separately from the modulation processing section 11 and the table 7, but the processing content is the same as that of the first embodiment. That is, the modulation processing unit 11 to which the modulation data is input performs the modulation using the table 7. In the table 7, a table address is specified from a PN generator 13 described later, and data for performing modulation is input from a ΔΣ modulator 6a as a quantization unit.

The quantization table data generator 1 is composed of a sequence controller 12, a PN generator 13, a table data generator 14, and a ΔΣ modulator 6a. The sequence control unit 12 performs control for generating an all 0 and a PN sequence in sequence using a PN generator.

For example, first, all 0s (00... 00) are input to the parallel input of the register of the PN generator. Next, 00... 01 are input to the parallel input of the register of the PN generator, and the PN generator is operated for the period of the PN sequence.

Here, for example, if there are PN9 stages, P
00000000 to parallel input of N generator register
Enter 0. Next, 000000001 is input to the parallel input of the register of the PN generator, and the PN generator is operated 2 ⁹ −1 = 511 times. As a result, all combinations of ⁹ bits (2 ⁹ = 51) can be obtained from the parallel output of the PN generator.
2) are obtained.

The PN generator 13 is a pseudo random number generator having a number of stages corresponding to the length of the impulse response of the FIR digital filter. For example, if the length of the impulse response of the FIR digital filter is set to 9 symbol periods, the PN generator has 9 stages. FIG. 5 shows an example of a nine-stage PN generator.

FIG. 5 is a diagram showing a configuration example of a PN modulator used in the digital modulator according to the present embodiment. As shown in the figure, the PN modulator 13 includes shift registers 21 # 1 to 21 # 9 configured using D-flip-flops.
Are sequentially connected, and an XOR unit 22 is further provided.

Then, an exclusive OR (XOR) of predetermined outputs, that is, shift registers 21 # 5 and 21
The exclusive OR of # 9 is input serially from the XOR unit 22 to the shift register 21 # 1.

The parallel input of the PN modulator 13 forcibly sets the contents of the flip-flop. The parallel output outputs the contents of the flip-flop. The table data generator 13 includes an impulse response generator 31 and a convolution processor 32 as shown in FIG.

FIG. 6 is a block diagram showing an example of the configuration of the table data generator of the digital modulator according to the present embodiment. The impulse response generation unit 31 is configured by, for example, a ROM that stores an impulse response created in advance, or, for example, a unit that calculates an impulse response as illustrated in FIG.

FIG. 7 is a block diagram showing a configuration example of an impulse response generator of the digital modulator according to the present embodiment. The filter characteristic specifying unit 33 specifies the characteristics and parameters of the baseband filter according to the key input and the corresponding communication system. For example, the root Nyquist characteristic and the roll-off rate α = 0.5 are specified. The frequency characteristic generator 34 generates a frequency characteristic of the baseband filter. For example, in the case of the root Nyquist characteristic, the following frequency characteristic H (f) is generated.

[0074]

(Equation 4) Here, T is the symbol period. Actually, in order to perform digital signal processing, a finite number of discrete values are used. This is the same in the following description.

The frequency characteristic H (f) is converted to an inverse Fourier transform
In step 5, inverse Fourier transform is performed to convert the time response to f (t). In practice, a discrete Fourier transform such as a fast Fourier transform (FFT) is used. f (t) is a coefficient of the FIR digital filter. When an impulse response is created in advance and stored in a ROM, this f (t) is stored in the ROM.

Next, the convolution processing section 32 shown in FIG. 6 will be described. The convolution processing unit 32 converts all combinations within a finite time of the modulation data input into a modulation symbol sequence and performs a convolution operation for a symbol period of time. The result is written into the table using the modulation data input as an index. For example, if the length of the impulse response is 9 bits in the BPSK modulation, the modulated data sequence d _i (i
= 0, 1,..., 8) into modulation symbols S _i .

[0077]

(Equation 5) And outputs the f _T (t) of the time duration symbol period.

Since the convolution process is to create the table 7, the modulation data input is a signal generated by the PN generator 14 in a pseudo manner.

Next, the ΔΣ modulator 6a shown in FIG. 4 will be described. The ΔΣ modulator 6a is configured as shown in FIG. 8, for example, in the case of normal primary ΔΣ modulation.

FIG. 8 is a diagram showing a configuration example of a ΔΣ modulator used in the digital modulator according to the present embodiment. In the case shown in the figure, the ΔΣ modulator 6a includes signal combiners 41 and 42,
It is composed of delay units 43 and 44 for performing z ⁻¹ and a quantizer 45.

Here, z ^-1 of the delay section is a delay of one sample, and is constituted by a D-flip-flop. The quantizer 45 performs quantization corresponding to the resolution of the D / A converter. The characteristics of this first-order ΔΣ modulator are as follows. If we replace the quantizer with the addition of quantization noise q,

[0082]

(Equation 6) , And the quantization noise q becomes 1-z ^-1 times. Converting 1-z ^-1 to frequency response gives (2 (1-cos ωT)) ^1/2
Therefore, quantization noise is reduced at low frequencies.

For example, in the case of ordinary second-order ΔΣ modulation, the configuration is as shown in FIG. FIG. 9 is a diagram illustrating a configuration example of a ΔΣ modulator used in the digital modulator according to the present embodiment.

In the case shown in the figure, the ΔΣ modulator 6a includes signal synthesizers 51, 52, 53, 54, delay units 55, 56, 57, 58 for implementing z ⁻¹ , a multiplier 59, a quantum And a converter 45. Here, too, when the characteristics are obtained in the same way

[0085]

(Equation 7) Becomes Since the quantization noise is multiplied by 2 (1-cosωT), the effect of reducing the quantization noise at a low frequency is greater than that of the first-order ΔΣ modulation.

The table 7 is composed of, for example, a RAM having the same word length as the number of bits of the D / A converter. For example, let d _i be R
The lower 9 bits of the RAM address are sequentially incremented by setting the upper 9 bits of the AM address to the symbol cycle time Δ
(4) Write the output of the modulator to the RAM.

Since the above processing does not need to be executed in real time, it can be executed by low-speed hardware or software. When the table is constituted by a ROM, table data is created in advance in the same manner as described above and written in the ROM.

The modulation processing section 11 outputs a digital modulation signal using a table in response to the input of the modulation data. For example, in the case of BPSK, serial modulation data is input to a serial input of a shift register, and a parallel output is set to the upper 9 bits of a table address. The lower part of the table address is sequentially incremented by a counter. These operate according to a clock corresponding to the transmission speed. The table data becomes a digital modulation signal output.

The digital modulator according to the embodiment of the present invention configured as described above operates similarly to the case of the first embodiment. When the modulation processing unit 11 outputs a modulation signal using the table 7 in the table type modulation unit 2, the probability that the ΔΣ modulation process is continued in the table information at the address indicated by the next symbol is １ ／. . Therefore, the probability that an error due to discontinuity occurs at the beginning and end of one symbol time is reduced.

As described above, the digital modulator according to the embodiment of the present invention has a configuration similar to that of the above-described embodiment, and furthermore, has a ΔΣ in the order according to the register value of the PN (pseudo-random number) generator. Since the modulated table is created, the same effect as that of the digital modulator according to the embodiment of the present invention can be obtained. Can be reduced.

In the present embodiment, the quantization means
Although the description has been given of the case where Σ modulation is used, the present invention can apply various methods as quantization means. For example, the first
The quantization method using the equations (1) and (2) described in the above embodiment is also applicable. The present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof.

[0092]

As described above in detail, according to the present invention, the output corresponding to the digital filter processing is subjected to processing capable of reducing the quantization error and then stored in the table. A digital modulator capable of reducing a quantization error without providing any special hardware can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an example of a digital modulator according to a first embodiment of the present invention.

FIG. 2 is an exemplary view for explaining an effect of reducing quantization noise in the digital filter table according to the embodiment in comparison with a conventional technique;

FIG. 3 is a diagram showing a state in which the probability of occurrence of an error can be reduced by designating a table address using a PN generator.

FIG. 4 is a configuration diagram showing an example of a digital modulator according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a PN modulator used in the digital modulator of the embodiment.

FIG. 6 is a block diagram showing a configuration example of a table data creation unit of the digital modulator according to the embodiment.

FIG. 7 is a block diagram showing a configuration example of an impulse response generator of the digital modulator of the embodiment.

FIG. 8 shows Δ used in the digital modulator of the embodiment.
FIG. 6 is a diagram illustrating a configuration example of a modulator.

FIG. 9 shows Δ used in the digital modulator of the embodiment.
FIG. 6 is a diagram illustrating a configuration example of a modulator.

FIG. 10 is a block diagram showing a configuration of a conventional digital modulator using a ΔΣ modulator as a quantization device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Quantization table data preparation part 2 ... Table system modulation part 3 ... D / A conversion part 4 ... Analog filter 5 ... Table preparation part 6 ... Quantization part 6a ... delta-sigma modulator 7 ... Table 11 ... Modulation processing part 12 ... Sequence controller 13 PN generator 14 Table data generator

Claims (4)

[Claims] 1. A table type modulator having a table (7) for selecting a table according to digital modulation data inputted from the outside and generating a digital modulation signal based on the data of the selected table. A digital modulator comprising (2) and a D / A converter (3) for converting the digital modulation signal into an analog modulation signal and outputting the analog modulation signal, performs digital filter processing to convert table information. A table information creating means (5) for creating, a process for changing frequency characteristics of quantization noise for the table information, and quantizing the table information to a resolution of the D / A converter; A quantization means for outputting the data as data to be stored in the table, wherein a frequency characteristic of the quantization noise can be changed. Digital modulator. 2. The digital modulator according to claim 1, wherein said quantization means is a ΔΣ modulator (6a) for performing ΔΣ modulation on said table information. 3. A pseudo-random number generating means (13) for outputting a pseudo-random number including a PN sequence of a number of stages corresponding to an impulse response time of said digital filter, wherein said table data creating means is arranged in accordance with a generation order of said pseudo-random numbers. 3. The digital modulator according to claim 1, wherein the processing of the quantization means is performed. 4. A first signal processing unit (91) for performing an operation of the following equation (1) on a signal route from an output of a table information creating unit to an input of the table, and the quantization unit: A quantizer body (9) that outputs the resolution of the table information output from the creating means in accordance with the resolution of the table.
2), a second signal processing unit (93) for performing an operation of the following equation (2) on a feedback route from the input of the table to the output of the table information creating means, Synthesizing means (94) for synthesizing the output of the table information generating means and the output of the second signal processing part between the generating means and the first signal processing part and inputting the output to the first signal processing part; The digital modulator according to claim 1, further comprising: (Equation 1)