JPH10227843A - Test pattern generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a test pattern generator in which the generation of a subpattern related to a return signal can be limited to once by a method wherein the return signal is read out at a timing at which all subpatterns are read out. SOLUTION: First, a main sequencer 101B generates a substart address and a call signal, and the call signal is delayed by a pipeline 108. Then, a subpattern, a return signal and the like are made to stand by at a first buffer memory 106 and a second buffer memory 107. When the call signal is input to a changeover control part 105 in this state, a subclok is generated, and the memories 106, 107, a subsequencer 201B and the like start an operation. Then, the subpattern from the memory 106 is output from a changeover circuit 103. Then, when four subclocks are supplied to the memory 107, the return signal is read out from the memory 107, and the control part 105 returns a circuit 103 to the generation state of a main pattern. Consequently, the cycle of the return signal is finished in one cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator used for testing whether a semiconductor integrated circuit device operates normally or not.

[0002]

2. Description of the Related Art Conventionally, when testing a microprocessor or the like constituted by a semiconductor integrated circuit, for example, a test pattern is generated from a test pattern generator, and this test pattern is supplied to an input of an IC to be tested. The output data is compared with the expected value from the test pattern generator, and a mismatch is detected to detect the presence of a defect, thereby making a pass / fail decision.

As the functions of ICs are improved and the speed of the ICs is increased, the contents of the test tend to be complicated. For this reason, a test pattern generator in which a sub-pattern generator is juxtaposed to a main pattern generator for generating a main test pattern has been put to practical use. As an example using a sub-pattern generator,
For example, when testing a plurality of functions of a certain IC, a pattern for initializing a memory under test is generated from a sub-pattern generator at the start of each function test.

[0004] By providing the sub-pattern generator with the specified functions, the program for generating the main pattern for operating the main pattern generator can be shortened, and the creation of the main program becomes easy. The advantage is that the capacity of the memory for storing the main program can be reduced. FIG. 3 shows a schematic configuration of a conventional pattern generator having a sub-pattern generator.
In the figure, 100 is a main pattern generator, and 200 is a sub pattern generator. The main pattern generator 100 and the sub pattern generator 200 are both main address generators 1
01, a sub-address generator 201, and pattern storage memories 102 and 202 for reading and outputting test patterns based on the address signals output from the address generators 101 and 201.
In 00, a switching circuit 103 for selecting and outputting test pattern signals output from the pattern storage memories 102 and 202 is provided to constitute a pattern generator having a sub-pattern generator.

The main address generator 101 comprises a main case memory 101A and a main sequencer 101B, and the sub address generator 201 comprises a sub sequence memory 201A and a sub sequencer 201B. Note that reference numerals 104 and 204 denote pipeline circuits for matching the cycles of the address signals output from the address generation units 101 and 201, respectively.

The main case memory 101A stores the order in which addresses are generated in the main pattern storage memory 102. The sub-pattern generator 200 also stores a sequence command for switching the control right. The main sequencer 101B decodes and executes the contents of the main case memory 101A. The main pattern generator 100 outputs the data in the pattern storage memory 102 as a test pattern until an instruction for switching the control to the sub pattern generator 200 is executed.

Here, when the main sequencer 101B executes an instruction to switch the control to the sub-pattern generator 200, the main address generator 101 stops generating the address in the pattern storage memory 102. The main sequencer 101B outputs the switching control signal SEL, and switches the switching circuit 103 to the sub side.

[0008] A call signal CALL for instructing the sub-sequencer 201B to start generating a pattern on the sub-side and a start address for generating the sub-pattern are supplied. The sub pattern generator 200 is the main pattern generator 10
0, the pattern generation operation is not performed until the call signal CALL is input, and when the call signal CALL is input, the pattern storage memory is started from the start address of the sub-pattern generation according to the contents of the sub-sequence memory 201 of the sub-pattern generator 200. 202 is accessed to execute generation of a sub-pattern.

[0009] The sub-sequence memory 201 of the sub-pattern generator stores the order of occurrence in the pattern storage memory 202. An instruction for returning control to the main pattern generator 100 is also stored. Here, a signal for returning control to the main pattern generator 100 by the sub sequencer 201B of the sub pattern generator 200 (return signal RETU)
RN) is read, the sub-sequencer 201 of the sub-pattern generator 200
B stops generating addresses to the pattern storage memory 202.

A return signal RETURN for restarting the main-side pattern generation is generated for the main sequencer 101 B of the main pattern generator 100. The main sequencer 101B outputs a return signal RETU.
Upon receiving the RN, the switching circuit 103 is switched to the main pattern. Main pattern generator 100 and sub pattern generator 20
0 is a call signal CALL, a sub-pattern start address signal transmitted from the main pattern generator 100 to the sub-pattern generator 200 because they cannot be arranged close to each other;
Clock signal and return signal RETU sent from sub-pattern generator 200 to main pattern generator 100
The RN receives a delay on the line. If this delay exceeds the clock cycle, the following inconveniences occur.

FIG. 4 shows a mutual connection relationship between the main sequencer 101B and the sub-sequencer 201B. A call signal CALL sent from the main sequencer 101B,
Sub start address signal, main clock signal ACL
K is supplied to the sub-sequencer 201B through the delay DY1. The return signal RETURN and the sub clock BCLK sent from the sub sequencer 201B are supplied to the main pattern generator 100 via the delay DY2.

The sub-pattern generator 200 similarly converts the call signal CALL and the sub-start address signal sent from the main pattern generator 100 into the main clock signal ACL sent from the main pattern generator 100.
K is taken in synchronization with the subclock BCLK delayed by the delay DY1, and operates in synchronization with the subclock BCLK.

On the other hand, in the main pattern generator 100, the return signal RETURN sent from the sub-pattern generator 200 is also synchronized with the sub-clock BCLK sent from the sub-pattern generator 200.
The data is taken into the buffer memory 101C in synchronization with the transmitted subclock BCLK, read out from the buffer memory 101C in synchronization with the main clock signal ACLK, and input to the main sequencer 101B operating with the main clock signal ACLK. ing.

The main sequencer 101B receives the return signal RETURN, and switches the switching circuit 103.
Is switched to the main pattern generation side.

[0015]

As described above, the main pattern generator 100 includes the sub-pattern generator 200.
The switching control of the switching circuit 103 is executed by the return signal RETURN sent from the
The switching timing of 03 is at least a time delay of the delay DY2 of the line for transmitting the signal from the sub pattern generator 200 to the main pattern generator 100. Further, since the processing time of the buffer memory 105 is added to the delay DY2, the switching timing of the switching circuit 103 is delayed over a plurality of cycles from the time when the return signal RETURN is generated. As a result, the switching circuit 103 outputs the return signal RET.
When the return signal is read from the timing when the URN is read from the sequence memory 201, the sub-pattern that has been read from the pattern storage memory 202 is continuously output.

FIG. 5 shows this state. FIG. 5A shows a main clock ACL used in the main pattern generator 100.
K, FIG. 5B shows the sub clock BCLK delayed by DY1 sent from the main pattern generator 100 to the sub pattern generator 200. When the main pattern generator 100 generates the call signal CALL (FIG. 5C) and the sub start address signal, the switching circuit 103 is switched to the sub pattern generator 200 side. Call signal CAL
The L and substart address signals are sent to the subpattern generator 200 under the influence of the delay DY1 (FIG. 5).
D).

When the call signal CALL and the sub start address signal are sent to the sub pattern generator 200, the sub sequencer 201B
The sub-addresses AD0, AD1, and AD2 are read from 01A, the sub-addresses AD0 to AD2 are input to the pattern storage memory 202, and the sub-patterns SO, S1, S2 are read from the pattern storage memory 202 and output through the switching circuit 103.

In the fourth cycle, the return signal RETURN
Is read from the sub-sequence memory 201A, the return signal RETURN is sent to the main pattern generator 100 with a delay of DY2. Further, since delays in the writing and reading processes of the buffer memory 101C are added, a sub-pattern is generated a plurality of times before the return signal RETURN is taken into the main sequencer 101B and the switching circuit 103 is actually switched. . FIG. 5 shows an example in which the sub-pattern S occurs seven times.

Since this sub-pattern S is applied to the IC under test, when the sub-pattern S is given, the logical comparator performs a logical comparison in the same manner as usual, so that the sub-pattern S It is necessary to prepare an expected value pattern. In other words, the high-speed pattern generator provided with this type of sub-pattern generator 200 has a drawback that a sub-pattern not involved in the test is generated unnecessarily for a plurality of cycles after the generation of the sub-pattern. I
A user of the C test apparatus must create a program for generating a test pattern so as to generate a correct expected value pattern for a sub-pattern not involved in the test as well as a normal test pattern.

Sub-patterns generated in this way (sub-patterns related to return signal RETURN)
If a correct expected value pattern is not prepared for the IC, the IC test apparatus determines that the IC under test has a defective unit when the sub-pattern is generated, and causes an inconvenience such as stopping the operation. Therefore, when the pattern generation right is returned from the sub pattern generator 200 to the main pattern generator 100,
Sub pattern generator 200 to main pattern generator 1
The return signal RETURN transmitted to 00 should be limited to only one cycle.

An object of the present invention is to provide a high-speed pattern generator having a sub-pattern generator, in which when a pattern generation right is returned from the sub-pattern generator to the main pattern generator, generation of a sub-pattern related to the return signal RETURN is performed by one. It proposes a configuration that can be limited only once.

[0022]

According to the present invention, there is provided a switching control unit for executing switching control of a main clock and a sub clock and generation control of a switching control signal SEL of a switching circuit. A call signal CALL is input, a sub-start address is sent from the main sequencer to the sub-sequencer, a sub-pattern generation start address is specified by the sub-start address, and an order specified by the sub-sequence memory from the sub-start address. Read the sub address with.

The sub address read from the sub sequence memory is input to the sub pattern storage memory, and the sub pattern is read from the sub pattern storage memory. The sub-pattern read from the sub-pattern storage memory enters a standby state where it is written to the first buffer memory. At the same time, the return signal RETUR follows the subaddress.
When N is read from the sub-sequence memory, the return signal RETURN is written to the second buffer memory and waits. In this state, when the call signal CALL is supplied to the switching control unit, the switching control unit starts generation of a subclock, reads the subpattern written in the first buffer memory by the subclock, and reads this subpattern. It is output as a test pattern through the switching circuit.

The return signal RETURN is read from the second buffer memory at the timing when all the sub-patterns written in the first buffer memory are read, and the switching control unit executes control for switching to the main pattern generation state by the return signal RETURN. . Therefore, according to the present invention, as soon as the call signal CALL output from the main sequencer is input to the switching control unit, a subclock is generated, and the standby subpattern is output to the first buffer memory by the subclock, Sub-pattern generation is performed. At the same time, when all the sub-patterns have been output, the return signal RETURN read after the sub-address is read from the second buffer memory. The return signal RETURN is input to the switching control unit, and the state of the switching control unit is switched to the main side. As a result, the execution cycle of the return signal RETURN is limited to one cycle, and unnecessary sub-patterns do not occur over a plurality of cycles.

[0025]

FIG. 1 shows an embodiment of the present invention. In the figure, 100 and 200 indicate a main pattern generator and a sub pattern generator, respectively, as in the figure. The main pattern generator 100 includes a main address generator 101.
And the main pattern storage memory 102 are the same as in the description of the prior art.

In the present invention, the main pattern generator 100
Switch control unit 105 and first buffer memory 106
And a second buffer memory 107, and the switching control unit 105 is provided with a pipeline 108 for supplying a call signal CALL from the main sequencer 101B. To generate a sub-pattern, the main sequencer 101B simultaneously generates a sub-start address and a call signal CALL. Call signal CALL is delayed by pipeline 108 in cycle units. That is, the switching control unit 1
05 is shifted in the pipeline 108 in synchronization with the main clock ACLK output from the main clock ACCLK.
The call signal CALL is input to the switching control unit 105 when LK is supplied for a predetermined cycle.

According to the present invention, before the call signal CALL is input to the switching control unit 105, the sub-pattern, the return signal RETURN, and the sub-test signal SUB are stored in the first buffer memory 106 and the second buffer memory 107.
TEST and TEST are respectively operated. For this purpose, the sub start address output from the main sequencer 101B is input to the sub pattern generator 200 through the line delay DY1. In this example, a case is shown where a first-in first-out type memory (hereinafter, referred to as a FIFO memory) 205 is provided in the sub-pattern generator 200, and a sub-start address is provided to the sub-sequencer 201B through the FIFO memory 205. Writing of the sub start address to the FIFO memory 205 is performed by the delayed main clock ACLK (DY1) obtained by delaying the main clock ACLK sent from the main sequencer 101B by DY1 on the line. Reading is performed by the subclock BCLK output from the switching circuit 105. That is, since the sub-sequencer 201B operates by the sub-clock BCLK, the FIFO
Read from the O memory 205 and the sub-sequencer 201B
To the sub-start address.

The sub-sequencer 201B accesses the sub-sequence memory 201A based on the sub-start address, reads the sub-address written in the sub-sequence memory, and stores this sub-address in the pipeline 20.
4 to the sub-pattern storage memory 202.
The sub sequencer 201B is a sub sequence memory 201
Each time a sub-address is read from A, the next address to access the sub-sequence memory 201A is decoded,
The sub address is sequentially read by accessing the sub sequence memory 201A. Accordingly, the sub-pattern storage memory 202 sequentially generates sub-patterns according to the sub-address sent from the sub-sequencer 201B, and the sub-pattern is written into the first buffer memory 106.

On the other hand, the sub-sequencer 201B synchronizes with the start of the sub-address reading operation to synchronize the sub-test signal SU.
Generate BTEST. This subtest signal SUBTE
"1" at the same time as ST enters the sub address read operation.
The sub test signal SUBTEST is input to the second buffer memory 107 through the delay DY2 and written therein. The sub test signal SUBTEST is read from the second buffer memory 107 and the switching control unit 10
5, the switching control unit 105 stops the output of the subclock BCLK. This sub clock BCL
By stopping K, the first buffer memory 106 and the second buffer memory 107 enter a standby state.

In this standby state, the pipeline 10
8, the call signal CALL is input to the switching control unit 105 (the number of stages of the pipeline 108 such that the call signal CALL is input to the switching control unit 105 later than the timing at which the sub-test signal SUBTEST is read from the second buffer memory 107). Is set). The switching control unit 105 sends a switching control signal SEL for switching to the sub-pattern generation state to the switching circuit 103. At the same time, the output of the subclock BCLK is restarted. The first buffer memory 106 is generated by the sub clock BCLK.
Is read out, and this sub-pattern is output as a test pattern through the switching circuit 103.

In this example, the sub-clock BCLK is the signal shown in FIG.
As shown in (4), the second buffer memory 107 outputs a return signal RETURN by supplying four signals.
That is, in the fourth cycle of the sub-address, the return signal R
ETURN is read out, and the return signal RET is placed at the timing of the fourth cycle of the second buffer memory 107.
Since the URN is written, the return signal RETURN is read when four subclocks BCLK are supplied to the second buffer memory 107.

When the return signal RETURN is read from the second buffer memory 107 and input to the switching control unit 105, the switching control unit 105 switches the switching circuit 103 to the main pattern generation side. Therefore,
After that, the generation state of the main pattern is maintained until the call signal CALL and the sub-start address are output again from the main sequencer 101B.

The above operation will be described again with reference to the timing chart shown in FIG. 2A and 2B show the main clock ACLK. Main clock A shown in FIG. 2B
CLK indicates a delayed clock that is delayed by DY1 on the line while being transmitted from the main sequencer 101B to the sub-sequencer 201B. FIG. 2C shows the main sequencer 101.
B indicates the read call signal CALL and the sub-start address. The call signal CALL is output from the pipeline 108
Is sent to the switching control unit 105 through Further, the sub-start address receives the delay of the line delay DY1 and
The data is written to the FO memory 205 (FIG. 2D).

FIG. 2E shows the waveform of the sub-start address read from the FIFO memory 205. This FIF
The reading from the O memory 205 is performed at the rising timing of the subclock (delay DY1) BCLK (DY1) shown in FIG. 2F and is taken into the subsequencer 201B. FIG. 2G shows a sub address output from the sub sequencer 201B. This sub address AD
0, AD1, AD2, and AD3 are input to the sub-pattern storage memory 202 through the pipeline 204. Further, the sub-sequencer 201B outputs the return signal RETURN and the sub-test signal SUBTEST shown in FIGS. The return signal RETURN is the sub address AD3
Shows the state read from the sub-sequence memory 201A at the timing shown in FIG. Also, the sub test signal SUBTES
T rises to "1" logic at the timing of generation of the sub-address, and falls to "0" logic at the fall of the return signal RETURN.

The return signal RETURN and the sub-test signal SUBTEST are sent to the second buffer memory 107 through the delay DY2 shown in FIG. Writing to the second buffer memory 107 is performed by subclock BCLK shown in FIG. 2J in which subclock BCLK output from switching control section 105 is supplied through delays DY1 and DY2.
(DY2). Further, return signal RET
The URN and the subtest signal SUBTEST are delayed DY2
2K and L at the timings shown in FIGS. 2K and 2L.

Here, the timing at which the leading edge of the subtest signal SUBTEST is read from the second buffer memory 107 and input to the switching control unit 105 and the call signal C
The timing at which ALL is input to the switching control unit 105 is determined by the fact that the call signal CALL is set to the subtest signal SUBTES.
As input to the switching control unit 105 later than T,
Since the number of stages in the pipeline 108 is set, the leading edge of the sub-test signal SUBTEST is input to the switching control unit 105 at a timing before the call signal CALL is input to the switching control unit 105. The switching control unit 105 receives the “1” logic of the sub-test signal SUBTEST,
The sending of the subclock BCLK is stopped (see FIG. 2P). By stopping the sending of the sub clock BCLK, the first buffer memory 106 and the second buffer memory 1
07, the sub-sequencer 201B, the pipeline 204, etc. stop operating and enter a standby state.

In this standby state, the call signal CAL
When L is input to the switching control unit 105 at the timing shown in FIG. 2M, the switching control unit 105
Resume the occurrence of K. The first buffer memory 106 and the second buffer memory 107, the sub-sequencer 201B, the pipeline 204, and the like resume operations by the restart of the generation of the sub-clock BCLK. The switching control unit 105 outputs a switching control signal SEL supplied to the switching circuit 103 in FIG.
As shown in Q, the sub-pattern switching circuit 1 inverts the logic to “1” and reads out from the first buffer memory 106.
03 is output.

When four sub-clocks BCLK are supplied to the second buffer memory 107, the second buffer memory 10
7, the return signal RETURN is read, and when the return signal RETURN is input to the switching control unit 105, the switching control unit 105 drops the logic "0" of the switching control signal SEL shown in FIG. Return to the state where the main pattern occurred. Therefore, when returning from the sub-pattern generation state to the main pattern generation state, the cycle of the return signal ends in one cycle.

[0039]

As described above, according to the present invention, when returning from the sub-pattern generation state to the main pattern generation state, the generation cycle of the return signal RETURN is one.
The cycle ends, and unnecessary test patterns do not occur more than once. Therefore, since unnecessary test patterns are not applied to the IC under test, there is no need to create a pattern generation program for generating an expected value pattern that must be prepared when the unnecessary test patterns are applied. Benefits are obtained. Therefore, there is an advantage that an IC test apparatus that is easy for the user to use can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a block diagram for explaining a conventional technique.

FIG. 4 is a block diagram showing essential parts extracted from FIG. 3 for explaining inconvenience of the conventional technique;

FIG. 5 is a timing chart for explaining inconvenience of the conventional technique.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Main pattern generator 101 Main address generator 101A Main sequence memory 101B Main sequencer 102 Main pattern storage memory 103 Switching circuit 108 Pipeline 105 Switching controller 106 First buffer memory 107 Second buffer memory 200 Sub pattern generator 201 Sub address generation Section 201A Sub-sequence memory 201B Sub-sequencer 202 Sub-pattern storage memory 204 Pipeline 205 FIFO memory

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[Procedure amendment]

[Submission date] March 28, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

A return signal RETURN for restarting the main-side pattern generation is generated for the main sequencer 101 B of the main pattern generator 100. The main sequencer 101B outputs a return signal RETU.
Upon receiving the RN, the switching circuit 103 is switched to the main pattern. Main pattern generator 100 and sub pattern generator 20
0 is physically separated and the call signal CA sent from the main pattern generator 100 to the sub-pattern generator 200
LL, a start address signal of the sub-pattern, a clock signal, and a return signal RETURN sent from the sub-pattern generator 200 to the main pattern generator 100 are delayed by a line. If this delay exceeds the clock cycle, the following inconveniences occur.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0025

[Correction method] Change

[Correction contents]

[0025]

FIG. 1 shows an embodiment of the present invention. Figure 100 and 200 show main pattern generator and the sub-pattern generator, respectively. The point that the main pattern generator 100 includes a main address generation unit 101 and a main pattern storage memory 102 is the same as the description of the related art.

[Procedure amendment 4]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 5]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

Claims (1)

[Claims] 1. A. First Embodiment B. a main pattern generator including a main address generator and a main pattern storage memory for generating a main pattern based on the main address output from the main address generator; B. a sub-pattern generator composed of a sub-address generator and a sub-pattern storage memory for generating a sub-pattern based on the sub-address output from the sub-address generator; A switching circuit for switching between the main pattern and the sub-pattern output by the main pattern generator and the sub-pattern generator and outputting the same as a test pattern; B. a first buffer memory for storing a generated sub-pattern in the sub-pattern storage memory and controlled in a standby state; Storing a return signal and a subset signal indicating the end of the sub-address output by the sub-address generator,
B. a second buffer memory controlled to be in a standby state with the leading edge of the subset signal read; By reading and inputting the leading edge of the subset signal from the second buffer memory, the first buffer memory and the second buffer memory are controlled to be in a standby state, and the call output from the main address generator is output. When the command is input, the standby state is released, the switching circuit is switched to the sub-pattern generation state, and the return signal is read out from the second buffer memory and input, thereby switching the switching circuit. A test pattern generator, comprising: a switching control unit that switches to a main pattern generation state.