JPH10224620A - Image processing method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing method and its device in which optimum half tone processing is conducted and an image with high image quality is obtained by taking a weight corresponding to an area of each picture element into account even when a maximum luminance, a bit number and color expression capability differ from each picture element. SOLUTION: The device is provided with input frame buffers 2, 5, 8 that receive image data with a 1-picture element multi-value level, processor elements 3, 6, 9 that quantize the received image data based on a neural net algorithm so that an output area of one picture element corresponds to an output device different from a position of the picture element and output frame buffers 4, 7, 10 that provide an output of a quantization result, and the processor elements 3, 6, 9 executes an arithmetic operation based on the neural net algorithm based on a value resulting from multiplying a corresponding weight to the area of each picture element with an output value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus for quantizing input image data into data having a level smaller than the number of input levels of the input image data. The present invention relates to an image processing method and apparatus for performing a quantization process so as to adapt to different output devices.

[0002]

2. Description of the Related Art In order to reproduce a grayscale image on a black-and-white binary printer or display, an area gradation method for expressing a grayscale image by forming a pseudo digital halftone image has been used. Was. The area gradation method is a method of reproducing gradation by changing the ratio of black in a neighboring image, and comparing a grayscale image u (x, y) of an original image with a threshold value T calculated according to a certain rule. An error diffusion method for diffusing an error between an input grayscale image value and an output halftone image to unscanned pixels is practically used.

In the case of a color image, the input color image data is conventionally subjected to halftone processing into low bits (for example, 1-bit binary data) by using the dither method and the error diffusion method. A technique for forming a full-color image using a binary display device is known.

[0004]

However, the conventional dither method or error diffusion method requires that the output device has the same gradation expression capability in all pixels (all pixels have the same maximum luminance and the same number of bits). And has the same color expression capability). Therefore, there is a drawback that it cannot be used for output devices having different maximum luminance, the number of bits, and the color expression capability for each pixel. In a device with a fixed number of pixels, such as a liquid crystal display, when the number of pixels of display data is different from the number of pixels of the device, it is necessary to perform halftone processing after performing resolution conversion by interpolation processing or the like. .

The present invention eliminates the drawbacks of the prior art, and a quantum for outputting from an input multi-valued image data to an output device having different maximum luminance, the number of bits, the color expression capability, and the resolution for each pixel. It is an object of the present invention to provide an image processing method and apparatus capable of obtaining coded data (data subjected to halftone processing).

[0006]

In order to achieve the above-mentioned object, an image processing apparatus according to the present invention comprises an input means for inputting image data having one pixel multi-value level, and an image data input by the input means. A quantizing unit that quantizes the output area of one pixel so as to adapt to an output device that varies depending on the position of the pixel; and an output unit that outputs a quantization result from the quantizing unit. An operation for quantization processing is performed based on a value obtained by multiplying the output value by a weight corresponding to the area of each pixel.

Further, the image processing apparatus according to the present invention comprises: a grayscale image input means for inputting an input grayscale image; and at least two or more neurons in each pixel of the image. Dynamic quantization means for dynamically bringing a collective output amount obtained by multiplying and adding a weight corresponding to an output area ratio to a collective input amount obtained by weighting and adding an input grayscale image of a plurality of pixels, and the collective output amount And an area gradation output means for expressing the gradation of each pixel by an area corresponding to.

The image processing apparatus according to the present invention comprises: first product-sum calculating means for calculating a product sum of an input weight value and an input grayscale image in a neighboring image area; an output weight value in a neighboring image area; Second sum-of-products calculating means for calculating the sum of the weight value corresponding to the area ratio and the output value subjected to the quantization process, and adding means for adding the results from the first and second sum-of-products calculating means; It is characterized by comprising a quantizing means for quantizing the addition result from the adding means, and a control means for feeding back an output value obtained by the quantizing means to a second product-sum operation means.

Further, in the image processing method of the present invention, an input step of inputting image data having a multi-value level of one pixel, and an output area of one pixel differs depending on the position of the pixel. A quantization step of quantizing to adapt to an output device, and an output step of outputting a quantization result from the quantization step, wherein the quantization step outputs a weight corresponding to an area of each pixel to an output value. An operation for a quantization process is executed based on the multiplied value.

The image processing method according to the present invention further comprises a first sum-of-products calculating step of calculating a sum of products of an input weight value and an input grayscale image in a neighboring image area; A second sum-of-products operation step of calculating the product sum of the weight value corresponding to the area ratio and the quantized output value, and an adding step of adding the results from the first and second sum-of-products operations; A quantization step of quantizing an addition result from the addition step; and a control step of feeding back an output value obtained in the quantization step to a second product-sum operation step.

[0011]

Embodiments of the present invention will be described below in detail.

First, a case where halftone processing of input multi-valued image data into binary data based on an algorithm based on a cellular neural network will be described.

FIG. 1 is a diagram for explaining an algorithm based on a discrete-time cellular neural network (DTCNN) for performing binary halftone processing.

In FIG. 1, the output low bit image value Y in the 5 × 5 neighborhood image area of the output image for the target pixel is shown.
ij and the product sum of the output weight value Akl

[0015]

[Outside 1] Sum of the input grayscale image Uij and the input weight value Bk1 in the input image 5 × 5 neighborhood image area

[0016]

[Outside 2] And add

[0017]

[Outside 3] Ask for.

Here, the inputs Ui, j are -1.0 and +
A real value between 1.0 and output Yi, j is -1.0 or +
It takes two values of 1.0.

The values of Ak, 1, Bk, 1 are as follows, for example.

[0020]

[Outside 4]

Then, the result of equation (1) is obtained for each color, red (R), green (G), and blue (B), and input to the non-linear operation unit, where Yi, j = f (Xi, j) ( Equation 4) is obtained. The non-linear operation unit compares Xij for each color with a predetermined threshold (0 in this case) to determine Yi, j for each color.

The result Yi, j of the non-linear operation is set as the image value of the output image of the target pixel.

This operation is performed for all pixels in the image,
Repeat until the results converge.

The convergence will be described. First, the output results of all the pixels are set to random values, and the binarization results of all the pixels of the image are obtained based on (Equation 1). Next, based on the obtained binarization results, the binarization results are again obtained based on (Equation 1). An operation is performed to obtain a binarization result for all pixels. The first binarized result is compared with the second binarized result. As a result, if the number of changed pixels is equal to or more than a predetermined number, it is determined that the pixels have not converged, and the binarization result of all pixels is obtained again based on (Equation 1).
Then, the newly calculated binarization result is compared with the binarization result obtained immediately before, and the number of changed pixels is counted. Then, in the comparison of the binarization results, when the number of changed pixels becomes equal to or smaller than a predetermined number, it is determined that the pixels converge.

That is, the operation based on (Equation 1) is repeated until the result converges.

FIG. 1 shows a case where FIG. 2 performs binary halftone processing.
FIG. 8 is a diagram illustrating the operation of the non-linear operation unit f (x). FIG.
In the above, the calculation result Xi, j of (Equation 1) is compared with 0, and Yi, j is binarized to 1 when Yi, j is greater than 0 and −1 when Yi, j is less than 0.

Further, in order to perform the multi-value halftone processing by this method, the binary non-linear operation section may be changed to a multi-value.

For example, when performing quaternary halftone processing, as shown in FIG. 3, the operation of the non-linear operation unit f (x) in FIG. Output in four ways.

Next, a description will be given of an embodiment of the present invention in the case of a device having different luminance (area) and the number of gradations for each pixel, and a case of performing halftone processing while performing resolution conversion.

FIG. 4 is a diagram showing the details of the pixel configuration when an FLC display (ferroelectric liquid crystal display) capable of displaying a plurality of levels with one pixel is driven in a standard resolution mode (1024 × 768 dots). . FIG. 4 shows the state of one pixel.

In this standard resolution mode, sub-pixels (ar) are combined to form 0.0, 1..
0, 1.5, 2.0, 2.5, 3.0, 3, 5, 4.
0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.
0, 7.5, 8.0, 8.5, 9.0, 9.5, 10.
0, 10.5, 11.0, 11.5, 12.0, 12.
29 values of 5, 13.0, 13.5, 14.0, and 15.0 can be represented.

FIG. 5 shows an example of a combination of pixels for expressing the 29 values by r (red).

In FIG. 5, a, d, g, j, m, and p are symbols shown in FIG. 4 for specifying a pixel.

FIG. 6 shows an example of a combination of pixels for expressing the 29 values with g (green).

E, b, k, h, q, and n in FIG. 6 are symbols shown in FIG. 4 for specifying a pixel. FIG.
(Blue) shows an example of combinations of pixels for expressing the 29 values. C, f, i, l, o, and r in FIG.
This is a symbol shown in FIG. 4 for specifying a pixel. The output value Yi, j of the pixel can take a value from 0 to 15,
It is assumed that the value is normalized from 1.0 to +1.0.

FIG. 9 shows Xi, j in the standard resolution mode.
And the relationship between Yi and j. FIG. 9 shows an example in which Yi, j between −1 and +1 is quantized to 29 levels.

FIG. 8 is a diagram showing the details of the pixel configuration when the FLC display is driven in the high resolution mode (2048 × 1536 dots). As can be seen from FIG. 8, in the high resolution mode, the pixels in the standard resolution mode are divided into two in each of vertical (j) and horizontal (i), and the number of pixels is quadrupled.

In other words, in the standard resolution mode, one pixel can express up to 15 levels of 29 levels of luminance, but in the high resolution mode, the maximum is 15 per 4 pixels. It becomes the maximum brightness.

However, in the high resolution mode shown in FIG.
i: odd, j: r (red) and b (blue) at odd positions,
Also, since the maximum luminance of i: even number and j: odd number of g (green) is 5, 0 to 5 is calculated as -5 / (15/4) =-4/3 to + 5 / (15/4) = + 4 /. Y normalized to 3
i and j.

In FIG. 10, i: odd, j: odd r (red) and b (blue), i: even, j: odd g (green) Xi, j in the high resolution mode of FIG. And Yi, j
Shows the relationship. That is, in this case, Xi, j is quantized into binary values.

Similarly, in the high resolution mode shown in FIG.
Since the maximum luminance of i: odd number, j: odd number g (green), i: even number, j: odd number r (red) and b (blue) is 2.5, 0 to 2.5 is -2. .5 / (15/4) =-2 /
The value normalized from 3 to + 2.5 / (15/4) = + 2/3 is defined as Yi, j.

FIG. 11 shows that in the high-resolution mode of FIG. 8, i: odd, j: odd, g (green), i: even,
j: Xi, j and Y of odd r (red) and b (blue)
The relationship between i and j is shown. That is, in this case, Xi, j is quantized into binary values.

In the high resolution mode shown in FIG. 8, i:
Since the maximum luminance due to the two subpixels of odd, j: even r (red) and b (blue), and i: even, j: even g (green) is 5, 0 to 5 is −5 / (15/4)
Yi, j is obtained by normalizing from −4/3 to + 5 / (15/4) = + 4/3.

FIG. 12 shows that in the high resolution mode of FIG. 8, i: odd, j: even, r (red) and b (blue),
Also, i: even number, j: Xi, j and Yi of even g (green),
The relationship of j is shown. That is, in this case, for Xi, j,
Since there are two sub-pixels, they are quantized to four values.

In the high resolution mode shown in FIG. 8, i:
Since the maximum luminance by the two subpixels of odd, j: even g (green), and i: even, j: even r (red) and b (blue) is 2.5, 0 to 2.5 To -2.5 /
(15/4) = − ／ to + 2.5 / (15/4) =
The value normalized to +2/3 is defined as Yi, j.

FIG. 13 shows i: odd number, j: even number g (green), and i: even number, in the high resolution mode of FIG.
j: Xi, j and Yi of even r (red) and b (blue)
The relationship of j is shown.

That is, in this case, since Xi, j has two subpixels, it is quantized to four values.

When one pixel is composed of a plurality of subpixels, the output of one pixel can be represented by the sum of the output of each subpixel multiplied by the luminance (area) corresponding to the output.

[0049]

[Outside 5] Becomes

Here, Wn, i, j is an output maximum luminance weight value proportional to the area of each subpixel, and yn, i, j
j is the output of each subpixel, -1.0 or +1.0
Is the value of

In the standard resolution mode shown in FIG.
Weight value Wr1 Wr2 Wr3 Wr4 for (red)
The values of Wr5 and Wr6 are 1/15 and 1.5 /
15, 2/15, 2.5 / 15, 3/15, 5/15.

Wr1 Wr2 Wr3 Wr5 in FIG.
Wr6 represents the position of the corresponding pixel.

Weight value Wg1 Wg2 for g (green)
Wg3 Wg4 Wg5 Wg6 are also 1/1
5, 1.5 / 15, 2/15, 2.5 / 15, 3/1
5, 5/15, and the positions of the corresponding pixels are shown in FIG.

Weight value Wb1 Wb2 for b (blue)
Wb3, Wb4, Wb5, Wb6 are also 1/1
5, 1.5 / 15, 2/15, 2.5 / 15, 3/1
5, 5/15, and the positions of the corresponding pixels are shown in FIG.

In the high resolution mode shown in FIG. 8, i:
Odd, j: odd, weight Wloo1 for r (red) and weight Wboo1 for b (blue), and i: even,
j: Weight Wgeo1 for odd g (green) is 4/3

[0056]

[Outside 6] Becomes

I: odd number, j: odd number, weight Wgood1 for g (green), i: even number, j: odd number weight Wreo1 for r (red) and weight Wb for b (blue)
eo1 is 2/3

[0058]

[Outside 7] Becomes

I: odd number, j: even number, weights Wroe1 and Wroe2 for r (red) are respectively

[0060]

[Outside 8] Becomes

I: odd numbers, j: weights Wboe1, Wboe2 for even b (blue) are respectively

[0062]

[Outside 9] Becomes

Further, i: even number, j: weight Wgeo1 and Wgeo2 for even number g (green) are respectively

[0064]

[Outside 10] Becomes

The weights Wgoe1 and Wgoe2 for i (odd number) and j (even number) for g (green) are respectively

[0066]

[Outside 11] Becomes

Also, i: an even number, j: weights Wree1 and Wree2 for even r (red) are respectively

[0068]

[Outside 12] Becomes

Similarly, Wgeo1, Wg for b (blue)
eo2 is 4/15 and 2/5, respectively.

By substituting (Equation 2), (Equation 3) and (Equation 5) into (Equation 1), Xi, j is obtained. However, since Yi, j cannot be obtained by (Equation 4), the following method is used. Then, yn, i, and j as output values are obtained.

[0071]

[Outside 13] yn, i, j = f (xn, i, j) (Equation 7) where f (xn, i, j) is a function f (xn, i, j) = + 1.0 (xn , I, j> =
0) f (xn, i, j) = − 1.0 (xn, i, j <=
0).

That is, for n selected at random,
yn, i, j and (Expression 2) (Expression 3) (Expression 5) are substituted into (Expression 1), and Xi, j obtained is substituted into (Expression 6), and x
Find n, i, j.

This xn, i, j is substituted into (Equation 7), and y
Find n, i, j.

Until this processing converges (that is, y
(until there is no change in n, i, j). This is the result of obtaining yn, i, j at the time of convergence.

T in (Equation 6) is to give hysteresis to Yi, j obtained by the calculation of (Equation 6) and (Equation 7).
For example, in the standard resolution mode shown in FIG. 4, T = 1/15.

FIG. 9 shows the relationship between Xi, j and Yi, j in the standard resolution mode when T is given. T is 1 /
If it is smaller than 15, the value of Yi, j cannot be taken near Xi, j = 14/15 and near Xi, j = -14 / 15.

When T is larger than 1/15, X
i, j = 14/15 and Xi, j = -14 /
In the vicinity of 15, Yi, j can take a value, but the overlap of functions becomes large.

FIG. 12 and FIG.
This is a function of Xi, j and Yi, j in a pixel capable of displaying a value. Since the step width of the step-like function given by 2T needs to be 3/5, Te = 3/10 (2Te =
3/5).

In the case of the functions shown in FIGS. 10 and 11, To = 0 is set because there is no need for a stepped shape.

FIG. 14 is a block diagram showing the configuration of a display system incorporating the digital image processor of the present embodiment.

In FIG. 14, reference numeral 1 denotes an image input unit for inputting a gray-scale color image composed of a plurality of bits of pixels. Here, 8-bit data for each pixel of R, G, and B is input.
The image input unit 1 includes, for example, a digital camera, a scanner, and a computer. Reference numeral 2 denotes an input frame buffer for storing red (R) data, which temporarily stores image data for a plurality of lines.

Here, when determining the output data of the pixel of interest, since the product-sum operation is performed in a 5 × 5 area of the input image, data for at least five lines is temporarily stored.

In FIG. 14, reference numeral 3 denotes a processor element relating to R. Processor element is DTCN
Based on the algorithm of N, the product-sum operation of the output image data and the output weight value {Ak,
1 * Yi-k, j-1 and the product-sum operation ΣBk, 1 * Ui-k, j-1 of the input image data and the input weight value are added and output. In consideration of an input image and an output image of a predetermined area by the DTCNN algorithm, data as faithful as an input image is output to the output frame buffer 4 as data of a target pixel. Since the processor element 3 in the present embodiment uses the output device shown in FIG. 4, it performs more complicated processing of the basic form shown in FIG. 1, so that the details will be described with reference to FIG.

4 is an output frame buffer for R,
The quantized multi-valued image data is stored in correspondence with the sub-pixel of the liquid crystal display. The input frame buffers for green (G) and blue (B) are 5, 8 respectively, and the processor elements are 6, 9 respectively,
The output frame buffers are 7, 10 respectively.

11 is a ferroelectric liquid crystal display (FLC)
Display). One pixel of this display is composed of R, G and B sub-pixels as shown in FIG.

Reference numeral 12 denotes a CPU, which is connected to the input frame buffers 2, 5, 8, the image processing units 3, 6, 9, and the output frame buffers 7, 10, and performs address control of data transfer, control of the image processing unit, and the like. Do. The CPU 12 has a ROM storing a control program and an R as a work area.
AM is provided.

FIG. 15 is a block diagram showing details of the processor element 3. As shown in FIG. Processor elements 6, 9
Have the same configuration. The processor elements include an address calculator 30, an address calculator 31, an input weight memory 40, an input image value memory 41, an output weight memory 42,
Output luminance weight value memory 43, output image value memory 44, T
Value memory 90, product-sum operation unit 50, product-sum operation unit 51, product-sum operation unit 52, register 53, multiplier 54, adder 55,
It comprises a non-linear operation unit 56.

The address calculator 30 comprises an ALU 60, a PC register 61, and an NPC register 62. The address calculator 31 includes an ALU 63, a PC register 64, and an NPC register 65.

The PC register 61 stores the address of the pixel to be processed in the output image under the instruction from the CPU.
The NPC register 62 stores the image position of the neighborhood system.

The PC register 64 stores the address of the pixel to be processed of the input image under the instruction from the CPU.
The NPC register 65 stores the image position of the neighborhood system.

The values stored in the NPC register 62 and the NPC register 65 are values between (−2, −2) and (2, 2) when the size of the neighborhood used for processing is 5 × 5. , And for that purpose, a built-in increment so that their values can be updated.

The NPC register 62 and the PC register 6
The output weight memory 42 calculates the address of the neighboring pixel from the value of 1. The output luminance weight memory 43 and the output image memory 44 are controlled.

The output weight memory 42 stores the value of Ak, l (Equation 2) based on a command from the CPU 12.

The output luminance weight memory 43 has a CPU 1
2, the values of Wn, i, and j described above are stored.

The output image memory 44 stores the output image of each subpixel in the neighboring image area.

The T value memory 90 stores T = 1/15 used in the standard resolution mode and Te used in the high resolution mode.
= 3/10, To = 0.

The address of the neighboring pixel is calculated from the values of the NPC register 65 and the PC register 64, and the input weight memory 40 and the input image memory 41 are controlled.

The input weight memory 40 stores the value of Bk, l (Equation 3) based on a command from the CPU 12.

The input image value memory 41 stores the input grayscale image in the neighboring image area.

The product-sum operation unit 50 includes a register 70, a register 71, a multiplier 72, an adder 73, and an ACC register 74.
Consists of

The product-sum operation unit 51 includes a register 75, a register 76, a multiplier 77, an adder 78, and an ACC register 79.
Consists of

The product-sum operation unit 52 includes a register 80, a register 81, a multiplier 82, an adder 83, and an ACC register 84.
Consists of

The register 70 fetches the value of the input weight value memory 40. The register 71 fetches the value of the input image value memory 41. The register 75 fetches the value of the output weight value memory 42. The register 76 fetches the result value of the product-sum operation unit 52. Register 80
The value of the output luminance weight memory 43 is fetched. The register 81 fetches the value of the output image value memory 44.

The multiplier 72 includes a register 70 and a register 7
The value of 1 is multiplied, and Ak, l * yi-k, j-l are output. The adder 73 and the ACC register 74 are
And outputs the value of ΣAk, l * Yi-k, j-l.

The multiplier 77 comprises a register 75 and a register 7
6 and outputs Bk, l * Ui-k, j-1. The adder 78 and the ACC register 79 are connected to a multiplier 77.
And outputs the value of ΣBk, l * Ui-k, j-1.

The multiplier 82 includes a register 80 and a register 8
The value of 1 is multiplied, and Wm, i, j * yn, i, j is output. The adder 83 and the ACC register 84 are
And outputs the value of ΣWm, i, j * yn, i, j.

In the register 53, a value T for determining the threshold value read from the T value memory 90 is set in accordance with a command from the CPU 12.

The multiplier 54 multiplies the output image value memory 44 by the value in the register 53 and outputs T * yn, i, j.

The value of the result of the product-sum operation unit 50, the product-sum operation unit 51, the product-sum operation unit 52, and the multiplier 54 is input to the adder 55, and is shown in (Equation 6).

[0110]

[Outside 14] Is output.

The non-linear operation unit 56 performs the operation of (Expression 7), binarizes each sub-pixel, and updates the value of the output image value memory 44 with the result.

Binary data is determined for each sub-pixel,
In the standard resolution mode of FIG. 4, each of R, G and B can express 29 gradations as described above, and in the high resolution mode of FIG. Become.

After the operation has converged, the value of the output image value memory 44 is transferred to the output frame buffer.

Next, operation control flowcharts in the present embodiment are shown in FIGS. 16 and 17, and the control will be described. 16 and 17 are executed by the CPU 12.

In step S101, the output weight value (A), input weight value (B),
An output luminance weight value (W) and a step width (T) in a function of Xi, j and Yi, j are set.

FIG. 17 is a flowchart showing details of step S101. FIG. 17 is a flowchart illustrating an example of processing R data. In the control flowchart for the G and B data, the values of the weights (W) and (T) set in S204 are changed. Since this setting has been described above, FIG.
The flowchart corresponding to 7 is omitted.

In step S200 of FIG. 17, an output weight value A (formula 2) and an input weight value B (formula 3) are set. These weights are common to the standard resolution mode and the high resolution mode.

Next, in step S202, it is determined whether the resolution mode displayed on the FLC display is the standard resolution mode or the high resolution mode. This is set by a command from a not-shown host computer or the like.

In the case of the standard resolution mode, step S2
In step 03, weights W and T for the standard mode are set. The weight W is as described in FIG. 4 and T is as described in FIG.

On the other hand, in the case of the high resolution mode, step S
Proceed to 204. Here, the weights W and T for the high resolution mode are set. As shown in FIG. 8, the weight differs depending on the pixel position and the color. In S204, the weights used at the four pixel positions in the case of R are shown.

Since T has a different quantization level depending on the pixel position, To = 0 in the case of binarization corresponding to FIGS. 10 and 11, and T in the case of quaternization corresponding to FIGS. Sets Te = 3/10.

Returning to FIG. 16, in step S102, initial values are set in the output frame buffers 4, 7, and 10.
Here, +1 or -1 data is randomly set in the output frame buffer for all sub-pixels of all pixels. Then, initial values are also set in the input frame buffers 2, 5, and 8. Here, from the input data and the input weight value, ΣB
Calculate k, l * Ui-k, j-l and set it in the input frame buffer.

The value of Ak, l * Wn is calculated and set in the memory in the processor element from the output weight value and the output maximum luminance weight value.

Also, for all pixel input data of one screen,
When executing the product-sum operation, the operation order is set.
Here, the calculation order is such that all pixels are scanned at random. The lighting pattern of the output sub-pixel with respect to the input is also set in the table for performing the non-linear operation (an example of the lighting pattern is shown in FIG. 19).

In step S103, a command is issued to the three processor elements based on the order determined in step S102, and {Ak, l * Wn * yn, ik, j-l +
演算 Executes the calculation of Bk, l * Ui-k, j-l + T * yn, i, j and its non-linear calculation.

The result is sent to three frame buffers, and if different from the value already stored, the value is rewritten.

In step S104, the number of pixels whose output frame buffer value has been rewritten is determined.

In step S105, it is determined whether or not the number of pixels determined in step S104 is equal to or less than a predetermined value. If not, it is determined that the operation based on DTCNN has converged, and the calculation is terminated. Further, even when the number of repetitions has not reached the predetermined value, if the number of repetitions has reached the predetermined value, the calculation is terminated there. Otherwise, the process returns to step S103.

As described above, according to the present embodiment, even when the maximum luminance, the number of bits, and the color expression capability are different for each pixel, the optimum halftone processing can be performed by the algorithm based on the cellular neural network. And a high quality image can be obtained.

Further, in the standard resolution mode, 29 levels of R, G, and B halftone processing can be performed while performing resolution conversion in the same hardware mode.
Binary or quaternary halftone processing depending on the area of each pixel of G and B can be performed.

(Other Embodiments) Next, an example in which the processing is simplified by using a table operation will be described.

The output value of one pixel is the sum Yi, obtained by multiplying the sub-pixel in the pixel by the weight of the area ratio, as shown in (Equation 5).
j = ΣWn, i, j * yn, i, j.

Here, the values of Wn, i and j do not depend on the pixel at the standard resolution. For example, the value of the red pixel corresponds to each sub-pixel, and Wr1 = 1/15, Wr2 = 1.5 /
15, Wr3 = 2/15, Wr4 = 2.5 / 15, Wr
5 = 3/15 and Wr6 = 5/15.

At the time of high resolution, the value differs for each coordinate.
The values of Wn, i, j of the red pixel are: i: odd number, j: odd number, Wroo1 = 4/3 i: odd number, j: even number, Wreo1 = 2/3 i: even number, j: odd number When Wroe1 = 8/15, W
roe2 = 4/5 i: even number, j: even number, Wree1 = 4/15, W
ree2 = 2/5.

These are obtained by summing the product of the output image Yi, j and the output weight value Ak1, {Ak, l * Yi-k, j-1 =
Σ (Ak, 1 * Wn, ik, j-1) * yn, i-
Used for calculating k, j-1.

Since yn, ik and j-l take a value of +1 or -1, the product of (Ak, l * Wn, ik, j-l) and yn, ik, j-l is obtained. Sum operation is yn, ik, j-
(Ak, l * Wn, ik, j-
It can be calculated by addition and subtraction in l). (Ak, l * W
By calculating the value of (n, ik, j-1) in advance and storing it in the memory, the calculation can be performed without performing the product operation in the repeated calculation.

The input image Ui, j and the input weight value B
Since the value of the product sum ΣBk, l * Ui-k, j-1 with k, 1 does not change during the iterative calculation, it may be calculated first and stored.

FIG. 18 is a block diagram showing details of the processor element.

The overall structure of the other embodiment is the same as that shown in FIG. 14, and FIG.
7 shows details of a processor element for each color.

The processor element 100 includes an address calculator 120, a memory 130, a sign inverter 140, an adder 150, and a table 151. Address calculator 12
0 comprises an ALU 112, a PC register 110, and an NPC register 111.

The PC register 110 stores the address of the pixel to be processed under a command from the CPU 101. The NPC register 111 stores the image position of the neighborhood system. The value stored in the NPC register 111 is (−2, −2) if the neighborhood system used for processing has a size of 5 × 5.
A value between 2) and (2, 2) is stored, and therefore, an incrementer that can update those values is incorporated. The NPC register 111 and the PC register 110
, The address of the neighboring pixel is calculated from the value of, and the input frame buffer, output frame buffer, and memory are controlled.

In the memory 130, the product (Ak, l) of the output weight value and the area weight value calculated in advance by the CPU 101 is stored.
* Wn, ik, j-1).

The sign inverter 140 switches between inversion and non-inversion of the sign of the value in the memory 130 in accordance with whether the value of the output frame buffer for each subpixel is +1 or -1.

In the high-resolution mode composed of 6 sub-pixels for each color, the size of the A template is 5 × 5 = 25, and the product of the A template and the area ratio weight is used. Is required to store 5 × 5 × 6 = 150. Similarly, 150 sign inverters 140 are required.

The adder 150 outputs (Ak, l * Wn, ik, j-l) * yn, ik,
By adding j-l and the value of the input frame buffer 102 storing the result of the product-sum operation of the input value and the B template in advance, Σ (Ak, l * Wn, i-k, j-l)
* Yn, i−k, j−l + ΣBk, l * Ui−k, j−
Calculate l.

Here, since ΣBk, l * Ui-k, j-l is constant irrespective of repetitive calculation, it is calculated in advance by the CPU and stored in the input frame buffer 102.

The sub-pixel pattern table 151 stores the output Σ (Ak, l * Wn, ik, j-
l) * yn, ik, jl + ΣBk, l * Ui-k,
The correspondence between j-1 and the lighting pattern of the sub-pixel is stored. FIG. 19 shows an example of correspondence between inputs (z) and outputs (a, b, c, d, e, f) of the sub-pixel pattern table.

Next, an operation control flowchart in this embodiment is shown in FIG. 20, and the control will be described. This control is performed by the CPU 101 connected to the processor element. In step S101, the product (Ak, l * Wn, ik, j-1) of the output weight value (A) used by the processor element and the output luminance weight value (W) is calculated, and the memory 130 in the processor element is calculated. To be stored. Here, A and W indicate whether the resolution is standard or high resolution.
It changes depending on which color of G or B it is.

That is, the output luminance weight value W at the standard resolution is as described with reference to FIG. 4, and changes for each of R, G, and B colors without depending on the pixel position.

The output luminance weight value W at high resolution
Changes according to the pixel position and the color as described with reference to FIG.

In step S102, an initial value is set in the output frame buffer. Here, +1 or -1 data is randomly set in the output frame buffer for all sub-pixels of all pixels. Then, an initial value is also set in the input frame buffer. Here, ΣBk, l * Ui-k, j-1 is calculated from the input data and the input weight value, and is set in the input frame buffer.

For all pixel input data of one screen,
When executing the product-sum operation, the operation order is set.
Here, the calculation order is such that all pixels are scanned at random.

The lighting pattern of the output sub-pixel with respect to the input as shown in FIG. 19 is set in the table for performing the non-linear operation.

In step S103, based on the order determined in step S102, Σ (Ak, l * Wn, ik,
jl) * yn, ik, jl + {Bk, l * Ui-
The calculation of k, j-1 and the conversion by the sub-pixel pattern are executed.

This result is sent to the output frame buffer, and if different from the value already stored, the value is rewritten.

In step S104, the number of pixels whose output frame buffer value has been rewritten is determined.

In step S105, it is determined whether or not the number of pixels determined in step S104 is equal to or less than a predetermined value. If not, it is determined that the operation based on DTCNN has converged, and the calculation ends. Further, even when the number of repetitions has not reached the predetermined value, if the number of repetitions has reached the predetermined value, the calculation is terminated there. Otherwise, the process returns to step S103.

As described above, according to another embodiment, halftone processing in the standard resolution mode and the high resolution mode can be performed by rewriting the values of the table and the memory with the same hardware.

Further, the necessary product-sum operation (product-sum of output weight value and output luminance weight value) is decomposed for each sub-pixel,
By storing it in the memory in advance, it is possible to use Σ (Ak, l *
Wn, ik, j-1) * yn, ik, j-1 can be calculated only by addition.

Further, Σ (Ak, l * Wn, ik, j-
l) * yn, ik, jl + ΣBk, l * Ui-k,
Since the lighting pattern of the sub-pixel corresponding to j-1 is stored in advance, the processing can be speeded up.

In this embodiment, an example of an FLC display has been described as an output device.
It goes without saying that the present invention can be applied to a case where the number of bits and the color expression ability are different.

[0162]

As described above, according to the present invention, optimal halftone processing can be performed in different resolution modes even when the maximum luminance, the number of bits, and the color expression capability differ for each pixel. And high-quality images can be obtained.

[Brief description of the drawings]

FIG. 1 is a view for explaining the concept of image processing using a DTCNN in the present embodiment.

FIG. 2 is a diagram for explaining a non-linear operation unit in FIG. 1 when performing binary halftone processing;

FIG. 3 is a diagram for explaining a nonlinear operation unit in FIG. 1 when performing a four-value halftone process;

FIG. 4 Standard resolution mode (1024 × 768 dots)
The figure which showed the subpixel structure of one pixel of the FLC display at the time.

FIG. 5 is a diagram showing lighting sub-pixels with respect to luminance of R data in a standard resolution mode.

FIG. 6 is a diagram showing lighting sub-pixels with respect to luminance of G data in a standard resolution mode.

FIG. 7 is a diagram showing lighting sub-pixels with respect to luminance of B data in a standard resolution mode.

FIG. 8 is a high resolution mode (2048 × 1536 dots)
The figure which showed the subpixel structure for 4 pixels of the FLC display at the time.

FIG. 9 is a diagram showing a relationship between Yi, j and Xi, j in a standard resolution mode.

FIG. 10 shows the X of a given sub-pixel in high resolution mode
The figure which showed the relationship between i, j and Yi, j.

FIG. 11 shows the X of a given sub-pixel in high resolution mode.
The figure which showed the relationship between i, j and Yi, j.

FIG. 12 shows X of a predetermined sub-pixel in a high resolution mode.
The figure which showed the relationship between i, j and Yi, j.

FIG. 13 shows X of a predetermined sub-pixel in a high-resolution mode.
The figure which showed the relationship between i, j and Yi, j.

FIG. 14 is a block diagram illustrating a configuration of a display system including a processor for digital image processing according to an embodiment.

FIG. 15 is a block diagram showing details of a processor element in FIG. 14;

FIG. 16 is a control flowchart showing an operation in the embodiment.

FIG. 17 is a control flowchart showing an operation in the embodiment.

FIG. 18 is a block diagram illustrating details of a processor element according to another embodiment.

FIG. 19 is a diagram showing an example of a sub-pixel pattern table.

FIG. 20 is a control flowchart showing an operation in another embodiment.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Inoue 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Masamichi Oshima 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inside the corporation

Claims (15)

[Claims] 1. An input means for inputting image data having a multi-level of one pixel, and a quantizer for converting image data input by the input means to an output device in which the output area of one pixel differs depending on the position of the pixel. Quantizing means for quantizing, and output means for outputting a quantization result from the quantizing means, wherein the quantizing means performs a quantization process based on a value obtained by multiplying an output value by a weight corresponding to the area of each pixel. An image processing apparatus for performing an operation for 2. The image processing apparatus according to claim 1, wherein said quantization means performs a quantization process on the input image data based on a neural network algorithm. 3. The image processing apparatus according to claim 1, wherein the output device is capable of outputting an image at a plurality of resolutions, and the weight changes according to the resolution. 4. A gray-scale image input means for inputting an input gray-scale image, wherein each pixel of the image has two or more neurons, and a weight corresponding to an output area ratio is assigned to a nonlinear output value of the neurons of the plurality of pixels. Multiplying the total output amount by multiplying the input grayscale image of a plurality of pixels by weighting and dynamically approaching the total input amount; anda dynamic quantization means, An image processing apparatus comprising: an area gradation output unit for expressing gradation. 5. The image processing according to claim 4, wherein the input grayscale image is converted into the area gradation image corresponding to the resolution by making the number of neurons per pixel variable according to resolution. apparatus. 6. A first sum-of-products calculating means for calculating a sum of products of an input weight value and an input grayscale image in a neighboring image area, an output weight value in a neighboring image area, a weight value corresponding to an output area ratio, and Second sum-of-products calculating means for calculating the sum of products of the quantized output values; adding means for adding the results from the first and second sum-of-products calculating means; An image processing apparatus comprising: a quantizing unit for quantizing; and a control unit for feeding back an output value obtained by the quantizing unit to a second product-sum operation unit. 7. An image processing apparatus according to claim 6, wherein a weight value corresponding to an output area ratio in said second product-sum operation means is changed according to an output resolution. 8. An image processing apparatus according to claim 6, wherein said second sum-of-products calculating means executes a sum-of-products calculation using a table. 9. A display unit for displaying an image using a quantization result of the quantization unit, wherein the quantization unit stores a quantization result corresponding to the addition result in a table in advance. 7. The image processing apparatus according to claim 6, wherein: 10. An input step of inputting image data having one pixel multi-value level, and a step of converting the image data input in the input step so as to be adapted to an output device in which the output area of one pixel differs depending on the position of the pixel. A quantization step, and an output step of outputting a quantization result from the quantization step, wherein the quantization step is based on a value obtained by multiplying an output value by a weight corresponding to the area of each pixel. An image processing method comprising: performing an operation for: 11. The image processing method according to claim 10, wherein in the quantization step, input image data is quantized based on a neural network algorithm. 12. A first sum-of-products calculating step of calculating a product sum of an input weight value and an input grayscale image in a neighboring image area, an output weight value in the neighboring image area, a weight value corresponding to an output area ratio, and A second sum-of-products operation step of calculating the sum of products of the quantized output values; an adding step of adding the results from the first and second sum-of-products operations; An image processing method, comprising: a quantization step of quantizing; and a control step of feeding back an output value obtained in the quantization step to a second product-sum operation step. 13. The image processing method according to claim 12, wherein a weight value corresponding to an output area ratio in said second product-sum operation step is changed according to an output resolution. 14. The image processing method according to claim 12, wherein the second product-sum operation uses a table to execute the product-sum operation. 15. A display step of displaying an image using a quantization result of the quantization step, wherein the quantization step stores a quantization result corresponding to the addition result in a table in advance. Claim 12
The image processing method described in the above.