JPH10224162A - Gain variable amplifier circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent peaking characteristic possessed by a gain variable amplifier circuit from depending on gain by forming the emitter area of at least the positive phase side transistor of a differential transistor for control gain on an upper stage. SOLUTION: This gain variable amplifier circuit sets a Gilbert circuit to be a basic circuit and uses a trans-impedance circuit as its load means. Then the areas of the emitters of upper-stage differential transistor Q3 to Q6 are designed to be 1.5 to 10 times, preferably 2 to 3 times larger than the area of the emitters of lower-stage differential transistor Q1 and Q2. Consequently, the cross sectional area of a current route toward an emitter area 5 from an embedded layer 3 is increased to reduce the effective current density variation of the transistors Q3 to Q6 is reduced. As a result of it, the gain dependence of peaking characteristic provided for the amplifier circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a semiconductor integrated circuit technology and further to a variable gain type amplifier circuit, for example, to a technology effective when applied to a wide band gain variable amplifier circuit using a Gilbert circuit. .

[0002]

2. Description of the Related Art Conventionally, a circuit as shown in FIG. 5 has been known as a variable gain amplifier circuit using a Gilbert circuit.
The amplifier circuit of FIG. 5 has an emitter-coupled gain control voltage Vc.
Are connected to the common emitter side of two pairs of differential transistors Q3, Q4 and Q5, Q6 which are made to receive at their bases. Lower stage differential transistor pair Q
The constant current source IEE is connected to the common emitter terminals of 1 and Q2.

A variable gain amplifier using a Gilbert circuit is disclosed, for example, in Baifukan, 1990, P.S. R. Gray / R. G. FIG. Contributed by Mayer, translated by Minoru Nagata, "Analog Integrated Circuit Design Technology for Super LSIs", Vol.
78.

The variable gain amplifier circuit includes a control voltage Vc applied to the bases of upper differential transistors Q3 to Q6.
And the relationship between the gain and the control voltage is 2
It becomes a valence function. Further, the gain frequency characteristic shows a so-called peaking characteristic having a peak value in a high frequency region.

Now, when the control voltage Vc >> 0, the collector currents IC1, I2 flowing through the lower differential transistors Q1, Q2
Most of c2 flows to the transistors Q3 and Q6, and the amplification factor of the amplifier circuit becomes maximum. The control voltage Vc decreases and becomes 0
, Part of the signal current flowing only through the transistors Q3 and Q6 flows into Q4 and Q5,
The amplification rate decreases. When the control voltage Vc becomes 0, Q3 and Q
4, the signal currents flowing through Q5 and Q6 become the same, and the amplification factor becomes zero.

[0006]

As described above, in the variable gain amplifying circuit using the conventional Gilbert circuit, the gain can be controlled by the control voltage Vc. However, the operating states of the transistors Q3 to Q6 are controlled by the amplifying circuit. It has been found that the peaking characteristic of the amplifier circuit fluctuates according to the amplification factor in the high frequency region because the peaking characteristic varies according to the amplification factor. In a broadband amplifier represented by a signal amplifier for optical transmission, a flat gain frequency characteristic is required from a low frequency region close to DC to a high frequency region close to transmission bit rate,
This flatness needs to be maintained even if the amplification factor changes. Therefore, in such a field, if the variable gain amplifier circuit constituting the signal amplifier has the amplification factor dependency of the peaking characteristic as described above, the peak value fluctuates due to the amplification factor, and thus the signal in the frequency region where peaking is particularly likely to occur. When the signal is input, the waveform of the amplified signal differs depending on the amplification factor of the amplifier circuit, and there is a possibility that accurate “0” and “1” determination cannot be performed in digital signal transmission.

An object of the present invention is to provide a technique capable of making the peaking characteristic of a variable gain amplifier circuit independent of gain.

Another object of the present invention is to provide a variable gain amplifier circuit having a flat gain frequency characteristic over a wide range from a low frequency region to a high frequency region.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

Means for Solving the Problems In the present application, among the disclosed inventions, typical ones will be briefly described as follows.

That is, in a variable gain amplifier circuit composed of a Gilbert circuit, the emitter area of at least the positive-phase (or negative-phase) transistor of the upper gain control differential transistor is reduced by the emitter area of the lower input differential transistor. It is formed to be larger than the area.

Normally, when a wide-band variable gain amplifier circuit is designed using the above-mentioned Gilbert circuit, the upper-stage differential transistors (Q3 to Q6 in FIG. 5) optimize their high-frequency characteristics in accordance with the characteristics of the amplifier circuit. , And all transistors of the same size having a minimum necessary emitter area are used. However, since the gain control voltage is applied to the base of the differential transistor in the upper stage, only a signal having a frequency very low as compared with the input signal frequency is input, and it can be regarded that the base is almost grounded. For this reason, from the viewpoint of the lower differential transistor, the upper differential transistor can be considered as a cascode transistor, and it is not always necessary to use a transistor having a minimum necessary emitter area in order to maintain a wide band.

If the gain control voltage Vc is limited to 0 V or more (of course, it can be limited to 0 V or less), the relationship between the control voltage and the gain of the variable gain amplifier circuit composed of a Gilbert circuit is represented by a monovalent function. Can be considered. At this time, the upper stage differential transistor (Q3, Q4 or Q5, Q5 in FIG. 5)
The average current flowing in 6) is IEE / 4 to IEE / 2 or 0
ＩIEEE / 4. Peaking characteristics in the high frequency range
Depending on the operating state of the upper differential transistor, which is a load for the lower differential transistor (Q1, Q2 in FIG. 5),
Due to a large change in the average current flowing through these transistors, the current density changes and the fluctuation in the peaking characteristics increases.

According to the above means, since the emitter area of the upper differential transistor is made larger than the emitter area of the lower differential transistor, the effective current density of the upper differential transistor due to the change in the gain control voltage is increased. , And the gain dependency of the peaking characteristic can be reduced. As a result, a wide-band gain variable amplifier circuit with a stable dynamic frequency characteristic and a wide dynamic range is realized.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of a variable gain amplifier circuit suitable for applying the present invention.

The variable gain amplifier circuit shown in FIG. 1 has a configuration using a Gilbert circuit shown in FIG. 5 as a basic circuit and using a transimpedance circuit as a load means. That is, in the variable gain amplifier circuit of this embodiment, the emitter-coupled differential transistor pairs Q1 and Q2 are vertically stacked on the common emitter side of the two emitter-coupled differential transistor pairs Q3, Q4 and Q5, Q6. And a constant current source IEE is connected to the common emitter terminal of the lower differential transistor pair Q1 and Q2, and the collectors of the upper differential transistors Q3 and Q5 and Q4 and Q6 are cross-coupled to each other. It comprises a Gilbert circuit 10 and a load circuit 11 composed of a transimpedance circuit connected to the collectors of the upper differential transistors Q3 to Q6. A gain control voltage Vc is applied between the base terminals of the upper differential transistors Q3 and Q4 and between the base terminals of Q6 and Q5 so that the gain of the circuit is changed according to the control voltage Vc. I have. As a result, the lower differential transistors Q1, Q
The input voltage Vi input between the two base terminals is amplified in accordance with the amplification factor according to the gain, and is output from the output terminals OUT and / OUT connected to the collectors of Q3 and Q6.

The transimpedance circuit as the load circuit 11 includes a pair of differential transistors Q11 and Q12 commonly connected to an emitter, a current source IEEE2 connected to the common emitter, and the differential transistors Q11 and Q12.
Resistance elements R1 and R2 connected between the collector of Q12 and the power supply voltage terminal Vcc;
Negative feedback resistance elements R3 and R4 connected between the collector and the base of Q1, Q12.
The differential transistor Q3 of the variable gain amplifier circuit
The collector of Q5 and the collectors of Q4 and Q6 are connected respectively. By using such a circuit as a load means of the variable gain amplifier circuit (10) composed of a Gilbert circuit, the resistance R seen from the variable gain amplifier circuit (10) can be reduced to one-half the gain. As is clear from the equation f = k / CR, the operating frequency of the variable gain amplifier circuit can be improved.

FIG. 2 shows an example (a so-called vertical bipolar transistor) of the structure of the transistors Q1 to Q6 constituting the variable gain amplifier. 1, reference numeral 1 denotes a semiconductor substrate, 2 denotes an N-type buried layer provided in the semiconductor substrate 1, 3 denotes an epitaxial layer formed on the semiconductor substrate 1, and 4 denotes a P layer formed on the surface of the epitaxial layer 3.
The base region 5 is an N-type emitter region formed in a part of the base region 4, the N-type collector leading region 6 is formed so as to reach the buried layer 2, and the heat is applied to the surface of the epitaxial layer 3. A field insulating film formed by oxidation to electrically insulate between adjacent bipolar transistors.

In the variable gain amplifier of the embodiment of FIG. 1, the emitters of the upper differential transistors Q3 to Q6 are 1.5 to 10 times, more preferably 2 times, the area of the emitters of the lower differential transistors Q1 and Q2. It is designed to be up to three times as large.

As described above, the upper-stage differential transistors Q3 to Q3
The emitter area of Q6 is reduced by lower differential transistors Q1 and Q2.
2, the cross-sectional area of the current path from the buried layer 3 to the emitter region 5 is increased, and the effective current density change of Q3 to Q6 is reduced. be able to. As a result, the gain dependency of the peaking characteristics of the amplifier circuit can be reduced. It is not all of the transistors Q3 to Q6 that increase the emitter area, but rather the transistors Q4 and Q5 to which a positive control voltage is applied or the transistors Q3 and Q3 to which a negative control voltage is applied.
Any one of Q6 may be used. The emitter area of the upper-stage differential transistors Q3 to Q6 is
1.5 to 10 times the emitter area of Q2
If the emitter area of Q3 to Q6 is less than 1.5 times, the change in current density when the gain changes cannot be sufficiently reduced, and if it is 10 times or more, the parasitic capacitance of Q3 to Q6 becomes too large, which is desirable in circuit operation. Because there is no.

FIG. 4 shows lower stage differential transistors Q1, Q
When the emitter area of the transistor 2 is 1, the transistors Q3 to Q3
The simulation result of the gain frequency characteristic when the emitter area of Q6 is changed to 1, 2, and 3 is shown. When the gain is lowered from the maximum gain, the peaking characteristic near the relative frequency 10 changes. As the emitter area of Q3 to Q6 increases, the peaking characteristic becomes less even when the gain decreases. It can be seen that the characteristics do not change, and characteristics close to the frequency characteristics at the maximum gain can be obtained.

The following table shows the difference Δ between the gain at the relative frequency 1 and the gain near the relative frequency 10 where the peaking is applied.
Represents G. The relative frequency is, for example, a frequency when a frequency corresponding to a bit rate is set to a reference frequency “1”.

[0024]

[Table 1] According to the table, ΔG at the maximum gain is in the range of 4.32 to 4.35 dB even when the emitter area ratio is changed, and hardly changes, whereas ΔG at the minimum gain is the emitter area ratio. When changing to 1, 2, and 3, ΔG is changed from −0.2 dB to 1.8.
It can be seen that it changes by about 2 dB up to 2 dB. Also, by increasing the emitter area ratio, the difference AB between ΔG at the time of maximum gain and at the time of minimum gain can be reduced,
That is, it can be seen that the gain dependency of the peaking characteristic can be reduced.

FIG. 3 shows a configuration example of a signal amplifier for optical communication using the variable gain amplifier circuit of FIG. 1 using a Gilbert circuit and a transimpedance circuit as a load.

In the signal amplifier of this embodiment, a variable gain amplifier circuit is connected in two stages, and a differential amplifier circuit is connected in the subsequent stage, and the input signal Vi is amplified with a gain corresponding to the amplitude, that is, the signal Vi is amplified. The input signal having a small amplitude is amplified with a large gain and the input signal having a large amplitude is amplified with a small gain, and is output as a signal Vout having a predetermined amplitude. The number of cascaded variable gain amplifier circuits is not limited to two, and may be three or more.

As described above, in the above-described embodiment, in the variable gain amplifying circuit composed of a Gilbert circuit, at least the side of the upper gain control differential transistor that receives the base of the positive control voltage (or receives the negative control voltage). side)
The emitter area of the upper transistor is made larger than the emitter area of the lower input differential transistor, so that the change in the effective current density of the upper differential transistor due to the change of the gain control voltage can be reduced. Thus, there is an effect that the gain dependency of the peaking characteristic can be reduced.

This also provides an effect that a wide-band gain variable amplifier circuit with a stable dynamic frequency characteristic and a wide dynamic range can be obtained.

Further, as a load means of the variable gain amplifier circuit, a differential transistor pair commonly connected to an emitter,
A current source connected to the common emitter; a resistor connected between each collector of the differential transistor pair and a power supply voltage terminal; and a resistor connected between each collector and the base of the differential transistor pair. Since it is configured by a transimpedance circuit including a negative feedback resistor element, the operating frequency of the variable gain amplifier circuit can be improved, and a variable gain amplifier circuit having a flat gain frequency characteristic up to a high frequency region can be obtained. .

Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the above embodiment, a transimpedance circuit is used as a load means of the variable gain amplifier circuit, but it is also possible to simply replace the load with a resistor or the like.

In the above description, mainly the case where the invention made by the present inventor is applied to a variable gain amplifying circuit using a Gilbert circuit, which is an application field as the background, has been described, but the present invention is not limited thereto. Instead, it can be used in general circuits that apply Gilbert circuits.

[0032]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to realize a variable gain amplifier circuit whose peaking characteristic does not change depending on the gain. Further, a variable gain amplifier circuit having a flat gain frequency characteristic over a wide range from a low frequency region to a high frequency region can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a variable gain amplifier circuit suitable for applying the present invention.

FIG. 2 is a cross-sectional view showing a structural example of a bipolar transistor constituting the variable gain amplifier circuit according to the present invention.

FIG. 3 is a circuit configuration diagram showing a configuration example of a signal amplification circuit using a variable gain amplification circuit according to the present invention.

FIG. 4 is a graph showing a frequency characteristic of a gain of the variable gain amplifier circuit.

FIG. 5 is a circuit diagram showing a basic configuration example of a variable gain amplifier circuit using a Gilbert circuit.

[Explanation of symbols]

 Reference Signs List 10 Variable gain amplifier stage composed of Gilbert circuit 11 Load means (transimpedance circuit) Q1, Q2 Differential transistors for input Q3 to Q6 Differential transistors for gain control

Claims (4)

[Claims] 1. An emitter-coupled or source-coupled first and second differential transistor pair, a third differential transistor pair connected to a common emitter or source side, and the third differential transistor pair A current source connected to a common emitter or source terminal of the first and second differential transistor pairs, and a load means connected to the collector or drain side of the first and second differential transistor pairs. Are connected to each other, and a control voltage is applied to each base or gate terminal of the first and second differential transistor pairs so that the gain is controlled according to the control voltage. In the variable gain type amplifying circuit thus configured, at least a positive control voltage or a positive control voltage of the first and second differential transistor pairs is used. A variable gain amplifier circuit, wherein the size of one of the transistors receiving the negative control voltage at the base terminal or the gate terminal is larger than the size of the transistor forming the third differential transistor pair. 2. A transistor constituting the first, second and third differential transistor pairs is a bipolar transistor, and at least a positive control voltage or a negative control voltage of the first and second differential transistor pairs is provided. An emitter area of a transistor receiving a control voltage at a base is formed to be 1.5 times or more and 10 times or less than an emitter area of a transistor constituting the third differential transistor pair. 2. The variable gain amplifier circuit according to 1. 3. The load means includes a fourth differential transistor pair commonly connected to an emitter, a current source connected to the common emitter, each collector of the fourth differential transistor pair and a power supply voltage terminal. A resistance element connected between
3. The variable gain amplifying circuit according to claim 1, further comprising a transimpedance circuit including a resistance element connected between each collector and the base of said fourth differential transistor pair. 4. A semiconductor integrated circuit comprising a plurality of variable gain amplifier circuits according to claim 1, 2 or 3, which are connected in cascade.