JPH10223609A - Method of forming pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To finely machine a work difficult to machine by the present by the present photolithography. SOLUTION: On a working surface of a substrate 1 a laminate structure composed of a plagiarizing layer 20, conductive layer 3 and sensitive layer 4, is manufactured a probe 5 of a scan probe machine is scanned over the sensitive layer surface with a voltage applied to the conductive layer 3 through the probe 5 to draw this layer 4. After drawing, it is developed to form a pattern on the layer 4, the formed pattern on the layer 4 is etched to transfer it to the conductive layer 3 and the transferred pattern on the conductive layer 3 is etched to transfer it to the planarizing layer 2, thereby forming the pattern on the working surface of the substrate 1, using such a formed pattern as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pattern, and more particularly to a method for forming a pattern at high speed and finely regardless of the shape of a processed surface when performing fine processing using a scanning probe microscope.

[0002]

2. Description of the Related Art With the integration of dynamic random access memories (DRAMs) and the like, semiconductor lithography requires further fine processing techniques. However, with current optical lithography, processing with a minimum processing dimension of 100 nm or less is difficult. Therefore, a technology that replaces optical lithography is needed.

One of the promising candidates for a new technology to replace optical lithography is a nanometer-sized fine processing technology using a scanning probe microscope (hereinafter, referred to as “SP lithography (Scanning Probe Lithography)”). See Mine et al., Applied Physics Letter, Vol. 66 (1995), pp. 703-705, (SC Minne, et al., Appl. Phys. Let.
t., 66 (1995), PP703-705). This is a method in which a voltage is generally applied between a probe and a substrate to perform processing, and the resolution is high, and processing at an atomic level is also possible in principle.

[0004]

In the semiconductor lithography technology, not only high resolution but also high throughput and high processing accuracy are required. To achieve high throughput in SP lithography, it is necessary to scan the probe at high speed. In addition, in order to increase the processing accuracy, it is important to control the shape of the tip of the probe. However, with the integration of semiconductor elements, the element structure is becoming finer and more complicated, and the processed surface during lithography has large irregularities. In SP lithography, processing is performed by scanning the probe along the processing surface in the vicinity of the processing surface. If there is a large unevenness on the processing surface, the distance control of the vertical probe cannot catch up and the probe hits, resulting in high-speed scanning. Not only is it impossible, but also the shape of the tip of the probe is changed, so that there is a problem in that the processing accuracy is deteriorated.

An object of the present invention is to provide a method for performing fine processing with high resolution, high speed, and high accuracy regardless of the shape of the processed surface when performing fine processing using a scanning probe microscope.

[0006]

In order to achieve the above object, according to the present invention, a pattern is formed by applying a voltage to a sensitive layer by a pattern forming means using a resist layer having at least a planarizing layer and a sensitive layer. Is formed. The flattening layer of the resist layer is formed on the substrate, and the pattern forming means is a probe of a scanning probe microscope.

Further, a resist layer having a three-layer structure including a flattening layer formed on a substrate, a conductive layer formed on the flattening layer, and a sensitive layer formed on the conductive layer is provided. Using, by applying a voltage to the conductive layer by the pattern forming means to form a first pattern in the sensitive layer, form a second pattern in the conductive layer based on the first pattern, in the second pattern Forming a third pattern on the flattening layer based on the third pattern, and forming a fourth pattern on the substrate based on the third pattern. The pattern forming means is a probe of a scanning probe microscope. The flattening layer may be a material capable of performing anisotropic etching with high resolution, and may be an organic coated glass, polyimide, an organic photoresist, or silicon oxide. The conductive layer may be a material capable of forming a thin film having a high uniformity in thickness and capable of performing anisotropic etching at high resolution, and may be formed of aluminum, titanium, tungsten, copper, platinum, gold, titanium silica, polypyrrole, or It may be polythiophene. The sensitive layer
It may be a resist material from which a thin film having high uniformity of thickness can be easily formed, or may be polymethyl acrylate, polyglycidyl methacrylate or iodinated polystyrene.

Furthermore, using a resist layer having a two-layer structure having a flattening layer formed on a substrate and a sensitive layer formed on the flattening layer, a voltage is applied to the sensitive layer by a pattern forming means. To form a first pattern on the sensitive layer, form a second pattern on the planarization layer based on the first pattern, and form a third pattern on the substrate based on the second pattern. It is characterized by doing. The pattern forming means is a probe of a scanning probe microscope. The flattening layer may be a material capable of performing anisotropic etching with high resolution, and may be an organic coated glass, polyimide, an organic photoresist, or silicon oxide. The sensitive layer may be a material in which an oxide is generated by oxygen or water, and may be silicon, niobium, titanium, or chromium.

In the present invention, by forming a resist into a multilayer structure by SP lithography, the processing surface is flattened by a flattening layer, the probe can be scanned at high speed, and a voltage is applied from the resist layer to the probe. High precision and fine pattern can be produced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) A pattern forming method of this embodiment will be described with reference to FIG. In this embodiment, irregularities are formed on the surface of a substrate having a step by a pattern forming method using a resist having a three-layer structure. FIGS. 1A to 1C are process diagrams showing the main points of the present embodiment. Both figures are cross-sectional views. First, the drawing process will be described with reference to FIG. A structure in which a planarizing layer 2 is formed on a processed surface of a substrate 1, a conductive layer 3 is formed thereon, and a sensitive layer 4 is formed thereon is formed. The surface of the sensitive layer 4 is scanned with a probe 5 of a scanning probe processing apparatus such as an STM (scanning tunnel microscope) or an AFM (atomic force microscope) using a probe coated with a metal on the surface. A voltage is applied to the conductive layer 3 from the probe 5 to draw on the sensitive layer 4. After drawing,
By developing, a pattern is formed on the sensitive layer 4. Then, the pattern of the produced sensitive layer 4 is transferred to the conductive layer 3 by etching (FIG. 1B). Thereafter, the pattern transferred to the conductive layer 3 is transferred to the flattening layer 2 by etching (FIG. 1C). A pattern is formed on the processed surface of the substrate 1 using the pattern thus produced as a mask. Substrate 1
After the pattern formation, the flattening layer 2 is removed to complete the processing.

Hereinafter, this embodiment will be described in more detail.
Organic coating glass (SOG; Spin On) as a planarization layer 2 on the surface of a silicon substrate 1 having a step of 0.2 μm.
Glass) is laminated by a spin coating method to a thickness of 1 μm. Aluminum is deposited as a conductive layer 3 on the surface by sputtering to a thickness of 0.05 μm. PM as a sensitive layer 4 on the surface
MA (polymethyl methacrylate) is laminated to a thickness of 0.05 μm by a spin coating method. The flattening layer 2 is formed by spin-coating polyimide or organic photoresist in addition to SOG, or by laminating silicon oxide by sputtering or heat evaporation, and then CMP (Chemical Mechanical).
A material that has been flattened by a cal polishing method may be used. In addition, the conductive layer 3 may be formed by laminating a metal such as titanium, tungsten, copper, platinum, and gold by sputtering or heat evaporation in addition to aluminum. Titanium silica, polypyrrole, polythiophene, or the like may be formed by spin coating. They may be stacked. Further, the sensitive layer 4 may use another positive type electron beam resist. 1A, the distance between the tip of the probe 5 and the sensitive layer 4 is set to 1 nm to 10 n using, for example, an AFM.
while maintaining the voltage between the probe 4 and the conductive layer 3 from 5 V to 2
By applying 0 V and scanning the probe with 0.8 μm, a pattern having a width of 0.05 μm and a length of 0.85 μm is formed on the sensitive layer 4. At this time, the surface of the probe 5 is made conductive by covering titanium from 10 nm to 50 nm. The metal covering the probe 5 may be chromium, tungsten, platinum, or gold in addition to titanium. After forming the pattern, the pattern is developed, and the pattern formed on the sensitive layer 4 is transferred to the conductive layer 3 by reactive ion etching (hereinafter, referred to as “RIE”) (FIG. 1B). Further, the pattern of the conductive layer 3 thus manufactured is changed to R
It is transferred to the flattening layer 2 by IE (FIG. 1C). Finally, the substrate 1 is etched using the pattern transferred to the planarization layer 2 as a mask, so that the surface of the substrate 1 has a width of 0.06 μm.
m, a groove having a length of 0.9 μm can be manufactured.

Further, a negative type electron beam resist such as poly (glycidyl methacrylate) or iodinated polystyrene is used as the sensitive layer 4 instead of a positive type electron beam resist such as PMMA, and a similar forming process is performed to obtain a substrate. A projection pattern having a width of 0.06 μm and a length of 0.9 μm can be formed on the surface. As the resist, a resist for photolithography and a resist for X-ray lithography can be used in addition to a normal electron beam resist.

In this embodiment, since the processed surface of the substrate 1 is flattened by the flattening layer 2, the surface directly drawn by the probe 5 of the scanning probe fine processing apparatus becomes flat, and high-speed scanning of the probe becomes possible. . Further, in the conventional SP lithography, a voltage is applied between the probe and the substrate. In the present invention, since the voltage is applied from the probe to the conductive layer, the substrate, the planarizing layer, and the sensitive layer have conductivity. No need. Therefore, a flattening layer and a sensitive layer suitable for use, such as ease of processing and fineness, can be used for any substrate. further,
Since the sensitive layer is laminated on the flattened surface, it is easy to make the thickness of the sensitive layer thin and uniform.
It becomes possible to produce a pattern finely and precisely.

(Embodiment 2) In this embodiment, a method of forming a projecting pattern on a stepped substrate surface by a pattern forming method using a two-layer resist according to the present invention will be described. FIGS. 2A to 2C are process diagrams showing the main points of the present embodiment. Both figures are cross-sectional views.

As shown in FIG. 2A, when a voltage is applied to the sensitive layer 4 from the probe in the atmosphere of silicon, titanium, chromium, etc., an oxide is formed immediately below the probe by an oxidizing agent such as oxygen or water. The substance produced by is used. A two-layer structure is used without using a conductive layer. By applying a voltage from the probe 5 to the sensitive layer 4, an oxide 7 is generated in the sensitive layer 4 immediately below the probe 5 to form a pattern of the oxide 7 (FIG. 2B). Using the mask as a mask, a pattern is transferred to the flattening layer 2 by etching (FIG. 2C).
To form a pattern on the surface.

The present embodiment will be described in further detail below. 0.2
An organic photoresist is deposited as a planarizing layer 2 on the surface of a silicon substrate 1 having a step of μm by 1 μm by a spin coating method in the same manner as in Example 1, and silicon is applied on the surface as a sensitive layer 4 by a sputtering method to 0.10 μm. Laminate. The flattening layer 2 includes polyimide, S
A layer obtained by laminating OG by spin coating or by laminating silicon oxide by sputtering or heating evaporation and flattening by CMP may be used. The sensitive layer 4 is formed of a material other than silicon, such as titanium, chromium, or the like, which generates an oxide immediately below the probe due to oxygen in the atmosphere or water attached to the surface when a voltage is applied from the probe in the atmosphere. Lamination may be performed by a sputtering method or a heating evaporation method. 2A, a voltage of 3 V was applied between the probe 5 and the sensitive layer 4 while maintaining the distance between the tip of the probe 5 and the sensitive layer 4 at 1 nm to 10 nm as shown in FIG. By applying a voltage of 10 V and scanning the probe with 0.8 μm, a width of 0.0
A silicon oxide pattern having a thickness of 5 μm and a length of 0.85 μm is formed. At this time, the surface of the probe 5 is coated with titanium in a thickness of 10 nm to 50 nm as in the first embodiment. The metal covering the probe is chromium, tungsten, platinum,
It can be gold. After that, the prepared pattern is transferred to the sensitive layer 4 by RIE using the prepared silicon oxide pattern as a mask (FIG. 2B). Further, the pattern of the sensitive layer 4 thus manufactured is transferred to the flattening layer 2 by RIE (FIG. 2C). Finally, by etching the substrate 1 using the pattern transferred to the planarization layer 2 as a mask, a projection pattern having a width of 0.06 μm and a length of 0.9 μm can be formed on the surface of the substrate 1.

(Embodiment 3) In this embodiment, a method of forming a groove pattern on a stepped substrate surface by a pattern forming method using a two-layer resist according to the present invention will be described. FIGS. 3A to 3C are process diagrams showing the main points of the present embodiment. Both figures are cross-sectional views.

On the surface of a silicon substrate 1 having a step of 0.2 μm, 1 μm of SOG is deposited as a planarizing layer 2 by a spin coating method in the same manner as in Embodiment 2, and silicon is applied as a sensitive layer 4 on the surface by sputtering to form a surface layer. .01 μm. As the flattening layer 2, in addition to SOG, a layer obtained by laminating a polyimide or a novolak-based resist by spin coating, or by laminating silicon oxide by a sputtering method or a heating evaporation method and flattening by a CMP method as in the first embodiment is used. May be used. In addition, when a voltage is applied from a probe in the atmosphere of niobium, titanium, chromium, etc., in addition to silicon, the sensitive layer is exposed to oxygen in the atmosphere,
Alternatively, a substance in which an oxide is generated immediately below the probe by water adhering to the surface may be stacked by a sputtering method or a heating evaporation method. Fig. 3
As shown in (a), the distance between the tip of the probe 5 and the sensitive layer 4 is 1
A voltage of 10 V to 50 V is applied between the probe 5 and the sensitive layer 4 while keeping the thickness from 10 nm to 10 nm, and the probe 5 is scanned by 0.8 μm to apply 0.1 μm width and 0.9 μm length to the sensitive layer 4.
A silicon oxide pattern having a thickness of μm and a depth of 0.01 μm is formed. At this time, the surface of the probe 5 is coated with titanium in a thickness of 10 nm to 50 nm as in the first embodiment. The metal covering the probe may be chromium, tungsten, platinum, or gold in addition to titanium. Thereafter, the pattern of the silicon oxide is removed from the sensitive layer 4 using a hydrofluoric acid solution to form a groove pattern having a width of 0.1 μm and a length of 0.9 μm on the surface of the sensitive layer 4 (FIG. 3B). ). Further, the pattern of the sensitive layer 4 thus manufactured is transferred to the flattening layer 2 by RIE using oxygen (FIG. 3C). Finally, planarization layer 2
By etching the substrate 1 using the pattern transferred to the substrate as a mask, a projection pattern having a width of 0.08 μm and a length of 0.8 μm can be formed on the surface of the substrate 1.

The technique of performing lithography with a resist having a multilayer structure is known in optical lithography and electron beam lithography as a method for preventing the multiple reflection effect and charge-up, respectively (for example, Japanese Patent Application Laid-Open No. 2-114624).
No.). In the present invention, by forming a resist into a multilayer structure by SP lithography, a processed surface is flattened by a flattening layer, a probe can be scanned at high speed, and a voltage is applied to the probe from the resist layer to achieve high precision. A fine pattern can be produced.

[0020]

According to the present invention, it is possible to perform fine processing which is difficult to process with current optical lithography.

[Brief description of the drawings]

FIG. 1 shows a pattern forming method of the present invention using a three-layer resist structure, in which (a) shows a drawing step, (b) shows a transfer to a conductive layer, and (c) shows a transfer to a flat layer. FIG.

FIG. 2 shows a pattern forming method of the present invention using a two-layer resist structure, in which (a) schematically shows generation of an oxide, (b) shows pattern production, and (c) shows pattern transfer. FIG.

FIGS. 3A and 3B show the steps of Example 3, in which FIG. 3A shows the formation of a silicon oxide pattern, FIG. 3B shows the formation of a groove pattern by removing the silicon oxide pattern, and FIG. FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Flat layer, 3 ... Conductive layer, 4 ... Sensitive layer, 5 ...
Tip, 7 ... oxide.

Claims (16)

[Claims] 1. A pattern forming method, wherein a pattern is formed by using a resist layer having at least a planarizing layer and a sensitive layer and applying a voltage to said sensitive layer by a pattern forming means. 2. The pattern forming device according to claim 1, wherein said flattening layer of said resist layer is formed on a substrate, and said pattern forming means is a probe of a scanning probe microscope. Method. 3. A resist having a three-layer structure including a planarization layer formed on a substrate, a conductive layer formed on the planarization layer, and a sensitive layer formed on the conductive layer. By using a layer, a voltage is applied to the conductive layer by a pattern forming means to form a first pattern on the sensitive layer,
Forming a second pattern on the conductive layer based on the first pattern, forming a third pattern on the planarization layer based on the second pattern, based on the third pattern A pattern forming method, comprising: forming a fourth pattern on a substrate. 4. The pattern forming method according to claim 3, wherein said pattern forming means is a probe of a scanning probe microscope. 5. The pattern forming method according to claim 4, wherein said flattening layer is made of a material which can be anisotropically etched with high resolution. 6. The pattern forming method according to claim 4, wherein the flattening layer is made of an organic coated glass, polyimide, organic photoresist, or silicon oxide. 7. The pattern forming method according to claim 4, wherein said conductive layer is a material capable of forming a thin film having a high uniformity in thickness and capable of performing anisotropic etching with high resolution. 8. The pattern forming method according to claim 4, wherein said conductive layer is made of aluminum, titanium, tungsten, copper, platinum, gold, titanium silica, polypyrrole, or polythiophene. 9. The pattern forming method according to claim 4, wherein said sensitive layer is a resist material from which a thin film having a uniform thickness can be easily formed. 10. The sensitive layer comprises polymethyl acrylate,
The pattern forming method according to claim 4, wherein the method is polyglycidyl methacrylate or iodinated polystyrene. 11. A resist layer having a two-layer structure having a flattening layer formed on a substrate and a sensitive layer formed on the flattening layer. By applying a voltage, a first pattern is formed on the sensitive layer, a second pattern is formed on the planarization layer based on the first pattern, and the substrate is formed based on the second pattern. Forming a third pattern on the substrate. 12. The pattern forming method according to claim 11, wherein said pattern forming means is a probe of a scanning probe microscope. 13. The flattening layer according to claim 12, wherein the flattening layer is made of a material capable of performing anisotropic etching with high resolution.
4. The pattern forming method according to 1. 14. The pattern forming method according to claim 12, wherein the flattening layer is made of organic coated glass, polyimide, organic photoresist, or silicon oxide. 15. The apparatus according to claim 12, wherein the sensitive layer is made of a material whose oxide is generated by oxygen or water.
4. The pattern forming method according to 1. 16. The pattern forming method according to claim 12, wherein said sensitive layer is made of silicon, niobium, titanium or chromium.